JPH08124321A - Method and device for decoding output signals at high speed - Google Patents

Abstract

PURPOSE: To obtain a means in which a high speed maximum liklihood decoding processing is realized. CONSTITUTION: Inputted signals are divided into blocks by a signal distributor 103 and are successively supplied to each one of plural maximum liklihood decoders 104. At each decoder, the signals are stored in a buffer storage device 106 and a decoding processing takes place at a relatively low speed and the result is outputted from a buffer storage device 108 in a parallel manner. Therefore, a maximum liklihood decoder having a necessary operating speed is provided employing a low speed circuit technology. Moreover, the processed results are supplied to the signal processors located after the decoding processings in a parallel manner at a lower speed by controlling serial/parallel conversion within the decoder.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a maximum likelihood decoding method for a binary code string and an apparatus for realizing the method.

[0002]

Signals from the channel outputs of communication and information storage devices have a certain time interval (transmission bit interval).
Each of the signal amplitude values has binary code bit information associated with a certain rule. This channel output signal is converted by the decoding device into the corresponding original binary code sequence. However, since noise and distortion are superimposed on the channel output signal due to various factors during channel transmission, reliability is significantly lowered in code conversion by the decoding device, and in large capacity / high speed communication and information storage / reproduction. , Becomes a big problem.

A maximum likelihood decoder is often used as a means for solving this problem. The maximum-likelihood decoding method selects, as a decoding result, the most likely received signal from all possible combinations of original code strings for a given received signal string. In this case, the code strings are not detected independently of each other, but are detected in consideration of the context of the signals. The Viterbi algorithm is widely used as a means for performing the maximum likelihood sequence estimation process with a finite circuit scale and a calculation amount. The Viterbi algorithm uses a dynamic programming format to efficiently perform maximum likelihood sequence estimation, and details are given in GD Forney Jr., "The Viterbi
Akgorithm, "Proceedings of the IEEE61 (3), March 197
3 (“The Viterbi Algorithm”, Proceedings of IEE) and GD Forney Jr., “Maximu
m-Likelihood sequence estimation of digital sequen
ces in the presence of intersymbol interference, "I
EEE Transaction on Information Theory, vol.IT-18, N
o.3, pp363-378, May 1972 (“Maximum Like Leafed Sequence Estimation of Digital Sequence is in the Presence of
Intersymbol Interference ", IEE Transaction on Information Theory, etc.) have been widely disclosed.

In these methods of maximum likelihood sequence estimation disclosed in the conventional literature, recursive calculation processing is repeated every time a decoded signal is input. That is, the process proceeds in such a manner that a plurality of estimated candidate sequences up to the immediately preceding arriving signal and their likelihoods are held and updated using the information of the new input signal. Then, by keeping the candidate sequence to be held sufficiently long, while observing the convergence and convergence of the initial part between the plurality of candidate sequences, or
The sequential decoding result is determined by the method of selecting the initial part of the candidate sequence having the highest likelihood at the present time, and the result is output. The maximum likelihood sequence estimator described above needs to sequentially select an estimated candidate sequence for a series of input signal sequences and calculate the likelihood. As a configuration for that,
For example, a likelihood calculation for an input signal, an operation determination circuit for adding the calculation result and the likelihood for a past candidate sequence, and selecting a new candidate sequence, a plurality of candidate sequences updated for each input A shift register group for sequentially holding is required. And the decoding form is
When one signal is input to the decoder, the decoding result for the input signal several bits in the past is output with a certain delay.

In other words, in maximum-likelihood decoding (maximum-likelihood sequence estimation), the judgment with respect to the sample signal value at each bit timing is not made only from the single value of the signal value but before and after the signal value to be judged. Estimate using the relationship. This relationship before and after the signal is added when a certain relationship is added to the code before transmission or recording by an error correction coding technique such as a convolutional code, when added at the time of conversion (modulation) from the code to the signal, Alternatively, it is taken into consideration by various factors such as when it is given as a result of signal output by the transfer characteristics of the recording / reproducing system or the transmission system.

[0006]

In the maximum likelihood decoding using the Viterbi algorithm of the prior art, it is required to perform likelihood calculation for each candidate sequence and repeat recursive arithmetic processing for the sequence estimation. To be done. As described above, in the conventional technique, every time one input signal arrives, the likelihood result up to the previous input signal is used to perform a new likelihood update by the input signal and a determination for a new sequence selection. Is required. As a result, it is essentially required that complicated calculation processing regarding likelihood calculation and determination must be completed within one input signal time. At the same time, a fast shift register is needed to hold the candidate sequences that are updated sequentially. Therefore, there has been a limit to the speedup of the conventional maximum likelihood decoding process due to the limitation of the circuit technology. In addition, since the maximum likelihood decoding output is speeded up, a high load is also applied to the subsequent data processing connected to the maximum likelihood decoding output.

An object of the present invention is to eliminate the restriction that has been conventionally generated in order to achieve the speedup of the maximum-likelihood decoding process, and to perform the maximum-likelihood decoding method for a series of signal streams of channel outputs transmitted at high speed. To provide a decoding processing form and apparatus for speeding up the decoding processing using the.

Further, an object of the present invention is to perform a decoding process for a series of signal sequences which are transmitted and output at a high speed substantially at a high speed by using a low speed circuit, and an apparatus for implementing the method. Is to provide.

[0009]

In order to achieve the above object, the present invention divides a series of signals input to a decoder into blocks of a fixed length, and divides the divided signal block into a plurality of maximum likelihood signals. The sequence estimator is sequentially supplied. Each maximum likelihood sequence estimator is provided with a device for storing the supplied signal block, and temporarily holds the supplied signal block. Then, each decoder reads the contents at a speed peculiar to the device and executes the maximum likelihood decoding algorithm. The decoded bit string obtained as a result of the maximum likelihood estimation for each block is sequentially recorded in the register device that records the decoded bit string as it is determined. This register device is also provided for each maximum likelihood sequence estimator, and the decoded bit string corresponding to the signal block supplied to the decoder is finally held therein. The register device that holds this decoded bit is supposed to be able to output each bit in parallel after determining the contents of all bits, and this output information is first supplied to the maximum likelihood sequence estimator as a signal block. By selecting in this order, a series of decoding results corresponding to the signal input to the decoder is obtained.

[0010]

The signal to be decoded is divided into blocks of a predetermined length, the blocks are stored in a plurality of maximum likelihood sequence estimators, and then maximum likelihood sequence estimation is performed, so that a slow maximum likelihood decoding process is performed. Permissible. Further, after the decoding result for each block is completely determined, the decoding result is output in parallel from the decoding circuit, so that the subsequent processing circuits can cope with high-speed signal decoding processing.

That is, according to the present invention, since a series of maximum likelihood decoding processes are divided and processed by a plurality of maximum likelihood decoding devices, the processing is several times faster than when a single maximum likelihood decoding device performs the decoding process. Can be decrypted.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention provides means for converting an input signal sequence into a corresponding code sequence and realizing a signal decoding process for outputting at high speed and with high reliability. The input signal is
The amplitude information in a specific time period holds bit information associated with a certain rule. This amplitude information is detected and converted into a bit code for digital reproduction. Therefore, in many cases, digital signal processing and decoding processing are performed using discrete signal values obtained by sampling signals in this time period. Although the following embodiments of the present invention will be described by using an example of implementation by digital processing, the present invention can be implemented by using an electronic circuit technology of analog signal processing for continuous signals.

FIG. 1 shows a basic configuration for explaining the device of the present invention and its operation.

The signal input from the input terminal 100 is subjected to preprocessing for performing a decoding process by the signal processing device 101 and then input to the decoding device 102. The specific pre-processing in the signal processing device 101 differs depending on the receiving device, the recording / reproducing device, etc. to which the decoding device is applied. As will be described later with reference to FIG. 9, it generally includes a circuit for performing signal amplification and noise removal by a filter, waveform shaping processing of a reproduced signal by an equalization circuit, inter-signal interference removal, and the like. After the signal processing apparatus 101 recovers the signal state of the input signal so that the decoding processing is normally performed, the output signal from the signal processing apparatus 101 is supplied to the decoding apparatus 102 of the present invention. In this embodiment, the signal processing device 101 is provided at the input of the decoding device 102, but it is not limited to this location. For example, they may be provided independently after each output of the signal distribution device 103 described later. The arrangement position of the signal processing device 101 does not relate to the essence of the present invention as long as it performs a preprocessing operation for each input of the maximum likelihood decoding device 104 in the decoding device 102. In the embodiment of the present invention, it is assumed that the signal processing device is arranged on the input side of the signal distribution device 103 and outside the decoding device 102 as an example (FIG. 1).

A first feature of the present invention is that a plurality of maximum likelihood decoding devices 104 are provided in parallel in the decoding device 102. With this configuration, the input signal is divided and the decoding process is performed, whereby the decoding process can be speeded up. Generally, the maximum likelihood decoding device is means for estimating an original transmission code sequence considered to have the highest possibility (maximum likelihood sequence estimation) from the received input signal sequence including noise and distortion, and is usually a Viterbi algorithm. It is done using a dynamic programming format such as. However, the maximum likelihood decoding process requires a recursive process in which the result of the calculation process for each input signal is used for the process of the input signal immediately after, and this point becomes a bottleneck, and one maximum likelihood decoding device In order to perform high-speed maximum-likelihood decoding processing in, there is a limit in circuit technology. In order to solve this problem, a plurality of maximum likelihood decoding devices 104
Therefore, it is a theoretically effective means to divide the input signal sequence, process it in parallel, and effectively increase the operation speed. On the other hand, if a plurality of maximum likelihood decoding devices 102 can operate in parallel with respect to the required operation speed, each maximum likelihood decoding device 102 can be realized at a low speed, and low cost for circuit implementation. Can be realized.

The signal input from the input terminal 100 is pre-processed by the signal processing device 101 and output to the decoding device 102. The decoding device 102 is a signal distribution device 103 that distributes signals input in time series to a plurality of output terminals at predetermined time intervals.
And a maximum likelihood decoding device group 104 that performs maximum likelihood decoding processing on the distributed signals, and a selection device 110 that outputs the outputs from the maximum likelihood decoding device group 104 in a predetermined order.

The output of the signal processing device 101 is the signal distribution device 1
It is divided into blocks of a fixed length (k bits) by 03, and is cyclically supplied to each maximum likelihood decoding device. The signal distribution device 103 detects the input timing of the input bit signal, and changes the maximum likelihood decoding device 104 at the output destination for each bit timing of the kth bit input signal, while converting the signal into blocks for each continuous k bit. Play a part in dividing. Each of the n maximum likelihood decoding devices 104 is supplied with a continuous signal sequence (block) divided into k-bit lengths at a constant cycle, and until the signal distribution device 103 supplies the next signal block. The maximum likelihood decoding process for the supplied signal block is completed in time. The input signal is divided into n maximum likelihood decoding devices (104-1 to 104-n) in blocks and supplied, and in principle, a decoding operation speed n times that of a single maximum likelihood decoding device is realized. can do.

Each maximum likelihood decoding device (104-i, i = 1 ... n)
Is a block distributor 105 that distributes and outputs in parallel the individual signal values that make up the supplied signal block, and an input block buffer memory that holds the distributed individual signal values independently and can output them independently. It has a device 106 and a determiner 107 that performs a maximum likelihood sequence estimation on the input block signal sequence using the signal values stored in the individual storage cells of this input block buffer storage device 106. Thus, in each maximum likelihood decoding device 104-i, by sequentially reading out the signal value from each memory cell of the input block buffer memory device 106 at a predetermined speed, the decoded bit in the signal input at the input terminal 100 The maximum likelihood decoding process that is slower than the transmission rate is allowed.

The output code buffer storage device 108 holds the maximum likelihood sequence estimation result (decoding result) corresponding to this input block signal. The output code buffer storage device 108 stores the result of all decoded bits obtained by the maximum likelihood sequence estimation. The selection device 110 includes the individual maximum likelihood decoding devices 104.
The contents of the output code buffer storage device 108 in -i are obtained, and the input signal block is sequentially selected and output in parallel in the same order as when the input signal block is distributed to each maximum likelihood decoding device 104-i in the signal distribution device 103. . The bit string of the maximum likelihood decoding result of the block stored in the output code buffer storage device 108 corresponds to the signal value string of the input signal block stored in each storage cell of the input block buffer storage device 106. Then, the parallel read line 1 from the output code buffer storage device 108
The decoded bits from 09 are input to the code demodulator 112 in the order selected by the selection device 110, and after the predetermined code bits are demodulated, are output from the output terminal 113 to the higher-level processing device. .

As described above, according to the present invention, the input signals input in time series are divided into predetermined blocks by the signal distribution device 103, and the maximum likelihood decoding device 104-i to which each block corresponds is the maximum. Likelihood decoding is performed and sequentially read in block units. The decoded bit string decoded in block units is read in parallel and demodulated. Therefore, the maximum likelihood decoding device 104 includes a block distributor 105 for performing serial-parallel conversion of an input signal, an input block buffer storage device 106 for holding individual signal values, and an output code for obtaining a decoding result for this. It is characterized in that it has a buffer storage device 108, and decoding results are simultaneously output in parallel from the output code buffer storage device 108 by a parallel read line 109.

FIG. 2 is an explanatory view of the principle of block maximum likelihood sequence estimation according to the present invention. Here, as a specific example,
An example of decoding an input signal having a ternary amplitude of A, 0, -A will be shown. The timing clock 202 is used to identify the sample point 201 at the bit timing of the signal 200. Signal amplitude + A
Alternatively, -A is associated with the bit "1", and the signal amplitude 0 obtained at the sample point is associated with the bit "0" to obtain the decoded bit sequence 220. This signal / code conversion form is
It is often used for recording / reproducing signals such as magnetic recording, and the amplitude values of + A and -A at this time appear alternately between the amplitude values of 0.

Further, in the embodiment of FIG. 2, pulse-shaped + A and
-There is a context that the amplitude value of A appears alternately. Such a context has a transfer characteristic of a partial response class 4 system, and is a form of transfer characteristic that an output signal of a recording / reproducing system used in a magnetic tape device, a magnetic disk device, a VTR device or the like generally has.

A state transition diagram 203 is a diagrammatic representation of the context of this signal for maximum likelihood sequence estimation. The state transition diagram 203 shows the time transition of the signal 200,
Two states of the signal at each time (two states when the polarity of the pulse identified at the sampling point is + A and -A)
Indicates that it changes over time. At each time, the signal 200 can have two states, state P (204) and state N (205). A sampling point 201 of the signal 200 is generated by a timing clock 202, which indicates four types of state transitions by arrows 206 to 209.
Each time one value of is given, the state transits from one of the two states to the other one by one. State P (204) indicates that the polarity of the previous pulse is + A, and state N (205) indicates that the polarity is -A. The arrow of the state transition 206 indicates the transition from the state N (205) to the state P (204), that is, the appearance of the pulse signal of polarity + A at this time. Similarly, the arrow of the state transition 207 represents the transition from the state P (204) to the state N (205), and the polarity at this time-
The appearance of the pulse signal of A is shown. On the other hand, state transition 20
Reference numerals 8 and 209 represent transitions between the same state P (204) and N (205). By not causing a transition between the two states, signal 200 is shown to appear at a signal value of 0 level where no pulse polarity occurs. When the state transition of the state transition diagram 203 is determined, it means that the pattern of the signal that alternates between the polarity + A and the polarity -A can be uniquely determined. By estimating the process of this state transition and associating the decoded bit "1" at the times of the transitions 206 and 207 and the decoded bit "0" at the times of the transitions 208 and 209, the decoded bit sequence 220 is obtained. The maximum likelihood decoding (maximum likelihood sequence estimation) is performed by estimating the state transition most suitable for the signal 200 while obtaining the correspondence between the state transition diagram 203 and the actual signal 200 and obtaining the decoding result corresponding to this. ). In the conventional maximum likelihood decoder, the state transition diagram 203 from the signal 200 is estimated by one decoder. In the present invention, the signal 200 to be judged is divided into blocks having a fixed length, and maximum likelihood estimation is performed within each block. Specifically, the signal 200 and the estimated state transition diagram 203 for the signal 200 are divided into fixed intervals of 5 bits between 6 states like state estimation sections 210a to 210d, and the state transitions are made for each of the divided blocks 211a to 211d. Make an estimate. The state transition estimation of each section (block) 211a to 211d is independently assigned to each of the plurality of maximum likelihood decoding devices shown in FIG. The decoding result obtained from the state transition estimation for each of the divided blocks 211a to 211d is reconfigured in the order of block division, and the decoded sequence
212 is given. Normally, the decoding results for each block are not sequentially rearranged, and after the state estimation in the block is confirmed, the decoding results for the block are collectively output in parallel and transferred to a higher-level process. This eliminates the need for high-speed operation in all implementation circuits after the decoding circuit. As a means for specifically implementing the decoding process of the present invention shown in FIG. 2, the signal distribution device 10 is a means for dividing the signal 200 into blocks 211a to 211d of state estimation sections 210a to 210d.
3, blocks 211a ~ 211d, the means for performing maximum likelihood decoding based on the respective state estimation is the maximum likelihood decoding device 104,
The selecting device 110 corresponds to means for selecting each decoded result in the original order of block division, reading each in parallel, and transferring to the upper processing.

In the case of communication or recording codes, the direct current component or specific frequency component of the recording code is suppressed in advance or the number of consecutive appearances of the code bit "0" or "1" is restricted due to restrictions on the code transmission channel characteristics. For the purpose of limiting the run length for controlling, the operation of converting (modulating) the code to be recorded according to the code conversion rule is often performed. Alternatively, error correction coding may be performed as higher-level processing. In this case, in order to record and reproduce this, the decoded code result is subjected to a code conversion operation reverse to that at the time of recording to re-convert it to the original code (demodulation), or an error coding rule is applied. An operation of inspecting and detecting / correcting an error bit is required. In this case, block coding modulation / error detection / correction that performs modulation / demodulation is often applied for each block unit having a constant code length. The number of bits of the block division unit of the present invention is set to the block code modulation / code applied to this code.
Synchronize with the same length as the error detection and correction processing unit,
By performing the input / output of the demodulation processing in block units, all the processing from the decoding processing to the demodulation / error correction processing to the higher-order processing can be realized by the block parallel low-speed processing. In addition, the processing speed of state transition estimation required for each decoder can be greatly reduced.

By the way, the conventional maximum-likelihood decoder performs decoding according to the context of the signal. In principle, if the signal is divided into blocks and processed, the maximum likelihood is obtained at the front end and the rear end of the block. Sequence estimation becomes difficult. Therefore, in the conventional decoding process, if the maximum likelihood decoder is used, it is difficult to parallelize the signal by block division. When performing the maximum likelihood decoding processing in block units of the present invention using the conventional technique,
Near the start of processing within each divided block (front end)
, There is no signal information before that, so the reliability of decoding is remarkably reduced, and the state transition is not estimated because the signal information after that is not obtained near the end (rear end) of the block processing. There will be problems such as confirmation. In the present invention, the block maximum likelihood sequence estimation processing is performed by solving the problem with the configuration shown in the following embodiments.

First, the sequence estimation procedure performed in the conventional maximum likelihood estimator will be described with reference to FIG. 8 for comparison. As a specific example, the signal and decoding rules are shown in FIG.
Is the same as that described in. Signal 801 shows the true correct signal pattern, while real signal 802
Distortion such as noise is superimposed on each sample point, and a signal level fluctuation occurs in the normal discrimination amplitude level. This real signal
The state transition diagram 803 is estimated from the 802 by the maximum likelihood sequence, and the decoded sequence 8
To obtain 00, the Viterbi algorithm is generally used, and the following procedure is repeated for each sample point to estimate the state transition. Given the sample value y (k) at time k, the state transition estimation is
It is performed as in (1) and (2).

(1) Whether the transition (path) to the state P (822a) at time k is due to the state P (821a) at time k-1 (path 1, 831a) or the state N (821b). It is decided whether it is one (pass 2, 831c). Therefore, the cumulative likelihood M_P for reaching the state P (821a) at the immediately preceding time k-1
(k-1), cumulative likelihood M_N (k-1) to reach state N (821b),
Square error E1 of signal amplitude value 0 and signal value y (k) indicated by path 1
(k), and the squared error E2 (k) of the signal amplitude value + A and the signal value y (k) indicated by path 2 is obtained (Equation 1) Total likelihood for path 1: E1 (k) + M_P (k -1) However, E1 (k)
= (y (k) -0) ^ 2 (Equation 2) Total likelihood for path 2: E2 (k) + M_N (k-1) where E2 (k)
Evaluate = (y (k) -A) ^ 2, select the path with the smaller total likelihood,
Replace the cumulative likelihood M_P (k) at the next time with the selected total likelihood. That is, (Equation 3) M_P (k) = Min (E1 (k) + M_P (k-1), E2 (k) + M_N (k-1)), where Min (A, B) is A and B An operation for selecting a smaller one is shown.

(2) Transition (path) to state N (822b)
From state P (821a) at time k-1 (paths 3, 8
31d), it is determined from the state N (821b) (path 4, 831b). Similar to (1), the cumulative likelihood M_P (k-1), M
_N (k-1), squared error E3 (k) between signal amplitude value -A and signal value y (k) shown by path 3, and signal amplitude value 0 and signal value y shown by path 4
Obtain the squared error E4 (k) of (k) (Equation 4) Total likelihood for path 3: E3 (k) + M_P (k-1) where E3 (k) =
(y (k)-(-A)) ^ 2 (Equation 5) Total likelihood for path 4: E4 (k) + M_N (k-1) where E4 (k) =
Evaluate (y (k) -0) ^ 2, select the overall likelihood for the smaller path, and replace the next cumulative likelihood M_N (k) with the selected overall likelihood. That is, (Equation 6) M_P (k) = Min (E3 (k) + M_P (k-1), E4 (k) + M_N (k-1)) The process according to the above steps (1) and (2) is illustrated. The actual signal 80 in the example shown in 8
When applied to the block of 2, the result of the state transition is
It becomes like the path indicated by the bold line in the state transition diagram 803.

However, the above operations (1) and (2) are repeated for each input of the sample value y (k) of the signal, and the result of the previous sample value is the cumulative likelihood M_P (k) and M_N (k). Is processed recursively through. Cumulative likelihood M_P (k) until input of the next sample value
Since M and N_N (k) must be updated, the series of processes (1) and (2) above must be completed by the next input. Here, the processing speed limit of maximum likelihood sequence estimation occurs.

Therefore, in order to improve the effective processing speed of the maximum likelihood decoding beyond this limit, it is necessary to divide the signal to be decoded into blocks and perform parallel processing, as described in the above embodiment. is there.

As shown in FIG. 8, the series of thick line paths described in the state transition diagram 803 corresponding to the state estimation section 833b are
It is the estimation result of the state transition determined by the maximum likelihood. However, the state estimation section 832a has the first cumulative likelihood M_P.
The estimation result may change depending on the setting of (0) and M_N (0), and the state estimation section 833c is a part where the path cannot be determined yet. Therefore, when the conventional maximum likelihood estimation algorithm is applied as it is to the divided blocks, it is difficult to make the estimation with the reliability of the maximum likelihood in the decoding of all the intervals in the block. Initial cumulative likelihood
Regardless of the settings of M_P (0) and M_N (0), in order to obtain the maximum likelihood sequence estimation result, at least one pass 2 or pass 3, that is, between the state P and the state N from the start of estimation. Must undergo a transition. In FIG. 8, the branch state estimation 834a including the transition between the states P and N appears in the state estimation section of 833a. By this route selection, the path started from the state P is aborted, and the subsequent paths are compared with those started from the state on the same side (state N in this case). Therefore, in subsequent relative likelihood comparisons, the first cumulative likelihood M_P
Likelihood can be determined regardless of the initial settings of (0) and M_N (0). On the other hand, since the branch state estimation 834a appears even in the state estimation section of 833c, the paths before that are
One path to state P will survive. By the appearance of these two branch state estimations 834a and 834c, FIG.
The bold line path corresponding to the state estimation section 833b of is defined. In order to obtain a path that is determined with the maximum likelihood in this way, branch state estimations 834a and 834c must appear before and after that, and the transition between state P and state N is included in the process before and after the decoding block. Must be done.

To determine the paths at both ends of the state estimation section,
It is realized using the methods of (1) and (2).

(1) The length of each decoded block is set longer than the block length 833b for which a code sequence is to be obtained, that is, the block length for implementing the maximum likelihood estimation sequence is larger than the length of the target decoded sequence 804. The reliability of the decoded sequence 804 can be increased by taking In order to maximize the decoding reliability in the decoding sequence 804, at least 1 should be set in each of the estimation sections 833a and 833c added before and after.
It should include one pass 2 or pass 3. That is,
A code string in which a bit "1" always appears in these two intervals is used. For example, as a code to be used, a modulation code in which the maximum bit interval of bit “1” (maximum 0 run length) is k bits is used, and estimated sections 833a and 833c to be added before and after the target section (833b) It is necessary and sufficient if the length is larger than k.

FIG. 3 shows an embodiment specifically showing the method of dividing the signal into blocks. In FIG. 3, the signal 200 and the state transition diagram 203 are the same examples as in FIG. With respect to the maximum likelihood estimation section blocks 210a to 210d, the length of the blocks 310 to 312 actually supplied to each maximum likelihood decoder is set to be large.
For example, the block 311 has surplus evaluation bits added so as to include path branches 321a and 321b indicating a change in state before and after the original maximum likelihood estimation section length 322b configured by the decoding result 323,
The block length 322a is provided as a signal sample. In this block length 322a, the bit "1" is always made to appear at least once in the surplus bits added before and after the maximum likelihood estimation section 322b due to the zero run length limitation of the modulation code. In the maximum likelihood estimation of the surplus bits added before and after this, the path branch 321a or 321b always occurs. As described above, decoding errors that can occur in principle at both ends of the maximum likelihood estimation interval are absorbed by the error occurrences in these two path branches 321a and 321b. Therefore, there is no influence on the decoding result of the block 322a which is the original decoding target.

The block maximum likelihood estimation of the embodiment shown in FIG.
Since they are supplied adjacent to each other in time, and there are overlapping portions between signal blocks, the decoding process is not always efficient.

(2) An embodiment in which the maximum likelihood decoding is performed by dividing the signal sequence into non-overlapping blocks will be described with reference to FIG. The present embodiment is an example of using a code in which the number of appearances of the bit "1" in each block or whether the number of appearances is even or odd is limited. By this, it is specified in advance in which state the state transition of each block starts and in which state it ends. If the start state and end state of the block are predetermined, the above-mentioned theoretical decoding error occurring at both ends of the block can be avoided. In the example of FIG. 4A, the block 408a
The number of bits "1" in ~ 408d (the number of occurrences of signal peak + A or -A, in other words, the number of transitions between state P and state N in state transition diagram 402) is always an even number. , An example in which the codes used are restricted will be shown. In order to limit the number of bits "1" in a block, each block is composed of a block obtained by adding one parity bit to the original decoded bit. Bit "1" in the block
Each block 408a-40 by limiting the number of
State transition diagram 40 that passes through at each start point 406a to 406d of 8d
2 states above can be identified. For example, in the state transition diagram 402, the state N is always passed at each starting point 406a to 406d of the block. Therefore, at the start of maximum likelihood estimation of each block, the cumulative likelihood of reaching each state can be set appropriately.

FIG. 4 (b) is a diagram for explaining a concrete processing procedure for each block in FIG. 4 (a). As shown in FIG. 4A, when the starting state of each block is specified, the polarity of the non-zero signal pulse that first appears in a given block is uniquely specified. In the example of this FIG. 4, the transition between states P and N that occurs first in each block is limited from the N side to the P side, so that the + A amplitude pulse always appears first. FIG. 4B is for explaining the signal estimation of each block in detail. Here, in starting the estimation of the state transition diagram, two states P (403)
And state N (404), the cumulative likelihood M_P for each state
(0) and M_N (0) are initialized to 0 and the decoding process starts,
The first + A signal pulse 415 cannot be determined with an appropriate likelihood. In other words, the first signal pulse 415 is
The result is likely to cause a decoding error. Therefore, in order to give an appropriate likelihood difference to the initial values of the cumulative likelihoods M_P (0) and M_N (0), the additional signal point 411 of the signal value -A which is the passing condition of the state N (404) is A pseudo signal is added immediately before the actual signal 410 indicating the maximum likelihood estimation section. This is because such an additional signal point 411 may actually be added before the signal sample sequence of the block to be decoded, or the cumulative likelihood obtained when such an additional signal point 411 is input. The normal maximum likelihood estimation process may be started with the values of M_P (k) and M_N (k) as initial values.
As a result of the above processing, the state transition diagram for the actual signal 417 is shown in FIG.
13 is estimated. In this figure, the state paths after the final branch path 412 are undetermined. This is because the transition between the state P (403) and the state N (404) up to that point is confirmed only once, but from the first condition that an even number of transitions exist in the block, The decision path 414 is determined to be the correct path. Alternatively, the decision path 414 can be established as the correct path due to the constraint that the last state of the block (starting state of the next block) must end in state N (404).

It is easy to generalize the above embodiment to the multi-state state transition estimation. In order to uniquely limit the transit state transition at the start and end between blocks, a certain rule is set in the code to be used, or a specific bit string is inserted between blocks, etc. Can be realized.

FIG. 7 shows a circuit configuration for implementing the maximum likelihood decoding in block units shown in FIGS. 3 and 4. Specifically, it shows a configuration example of the maximum likelihood decoding device 104 in FIG. Input terminal of the block distributor 105 from the signal distributor 103 of FIG.
One block of continuous signal value is supplied to 700. The block distributor 105 synchronizes the supplied continuous signal values with the bit clock timing 699 and sequentially stores the individual signal values in the respective memory cells forming the input block buffer memory device 106. In each maximum likelihood decoding device of the present embodiment, the contents of each storage cell of the input block buffer storage device 106 are read out to perform maximum likelihood sequence estimation. The device for this purpose is the buffer selection device 701. Through this selection circuit 701, the maximum likelihood decoding process is performed on the contents of each storage cell of the input block buffer storage device 106. The signal value y (k) read from the memory cell is calculated by calculating the squared error values E1 (k) to E4 (k) corresponding to the state paths 1 to 4 into four squared error calculation devices.
702a to 702d, state P and state N
Of the cumulative likelihoods M_P (k-1) and M_N (k-1) of the above equations (1) (2) (4) (5) are performed by the adders 703a to 703d. Equations (3) and (6) that compare the results to obtain the minimum value
The comparison operation of is performed by the comparators 704a and 704b. Each comparator 70
Cumulative likelihoods M_P (k) and M_N selected in 4a and 704b
(k) is stored in the cumulative likelihood registers 705a and 705b. In addition, it is determined which of the two inputs of the comparators 704a and 704b is selected, that is, which of the paths 1 and 2 and the paths 3 and 4 is selected as the paths leading to the states P and N, respectively. Registers 705a and 70
The decoded bit results “0” and “1” are stored in each of 5b. At this time, the position of the storage cell of the input block buffer storage device 106 to be processed and the recording bit position of the decoding register are associated with each other by the counter 710 and the address is designated. When pass 2 or pass 3 is selected, the value before the recording bit position of one of the decoding registers is
It is replaced by the content of the corresponding bit in the other decoding register. To perform this series of decoding register update processing,
The register updating devices 708a and 708b. Finally, after the processing is completed for all of the input block buffer storage device 106, one of the decoding registers 706a and 706b is selected by the selection circuit 707, and the contents of the selected decoding register 706a or 706b are output in parallel.

In order to perform the maximum likelihood decoding of FIG. 3 using the maximum likelihood decoding device 104 having the above configuration, the input block buffer storage device 106 has a block length corresponding to 322a of FIG.
Of the contents of the selected decoding shift register 705a or 705b, only the portion corresponding to 322b is read in parallel through the selection circuit 707. The selection circuit 707 corresponds to the selection circuit 110 in FIG. Further, in order to perform the maximum likelihood decoding of FIG. 4, the signal value corresponding to the additional signal 411 is recorded as the content of the first storage cell of the input block buffer storage device 106,
After the processing is completed, the contents of the decoding shift register 705a or 705b on the side corresponding to the final state are output in parallel. The structural feature of this embodiment is that it has a two-block distributor 105, an input block buffer storage device 106, and a buffer selection device 701.
The point is that the contents of the decoding shift register 705a or 705b are read simultaneously in parallel.

In FIG. 4, the maximum likelihood sequence estimation at the end of the block was possible by limiting the number of bits "1" in the block. Therefore, if the number of bits "1" in the block cannot be limited, it is not possible to uniquely specify the passing state of the state transition diagram at the start of the block. In order to proceed with the estimation independently for each block, it is necessary to advance a plurality of state transitions assuming the start from each state. In the embodiment shown below, each state transition assuming the start from each state is performed, and at the time when the maximum likelihood estimation process of the previous block performed by another decoder is completed, refer to the result,
Select from which state the state transition started was correct.

FIG. 5 shows a concrete example of the block maximum likelihood estimation when the code to be used cannot be restricted.

FIGS. 5 (a) and 5 (b) are for estimating the state transition for the same input block signal, assuming that the starting states are the state N and the state P, respectively. Similar to the example of FIG. 4 (b), the amplitude value -A is set before the actual signal estimation ranges 501 and 503.
The maximum likelihood estimation is advanced assuming that the additional signal points 502 and 504 of + A and + A are added, and the state transition diagrams 505 and 506 are obtained. In this case, there is a 1-bit difference between the decoding results 508 and 509 obtained from the respective state transition diagrams. The correct result is either 508 or 509. In order to select one of the decoding results, the state of the final branch path 515 of the state estimation result of the previous block (FIGS. 5 (c) and 5 (d)) is referred to. If the final branch path 515 is estimated as shown in FIG. 5 (c), the decision path 516 may be established (transition end in state N). ) Is connected. To determine the likelihood between the connected blocks, the signal value y (p) (51
7) and the signal value y (k) which causes the start branch path 516 of FIG. 5 (a), the condition of (Equation 7) y (k) -y (p)> + A is checked. When the condition of (Equation 7) is satisfied, the likelihood of passing through the decision paths 516 and 517 is greater in the final branch path 516 of FIG. 5 (c) and the start branch path of FIG. 5 (a). Therefore, the decoding result of bit "1" is assigned to each of these two branch points.

On the contrary, if the final branch path 519 is estimated as shown in FIG. 5D, the decision path 520 is established (state P).
However, as the next block,
As shown in FIG. 5 (b), similarly to the above, the signal value y (p) (517) that produces the final branch path 515 of FIG. 5 (d) and the start branch path 516 of FIG. 5 (b) are produced. Check the condition of (Equation 8) y (k) -y (p) <-A with the signal value y (k). When the condition of (Equation 8) is satisfied, the likelihood of passing through the decision paths 520 and 521 is greater in the final branch path 516 of FIG. 5 (d) and the start branch path of FIG. 5 (b). Therefore, the decoding result of bit "1" is assigned to each of these two branch points. The above formula (Formula 7) or (Formula 8)
When the condition of is not satisfied, by assigning bit "0" to the part of the undetermined branch path, it is possible to perform the decoding that is consistent with respect to the maximum likelihood sequence estimation among all the blocks. Further, as shown in the state transition diagrams 505 and 506, even if the start of transition estimation is started from different states, the estimated transition diagrams match as the estimation proceeds. That is, the two estimated transition diagrams of Fig. 5 (a) and Fig. 5 (b)
The difference between 505 and 506 is that the start branch path 51 is different.
There are only 6 occurrence positions. Therefore, in the path estimation of both, from the time when the state of the estimated transition matches after the branch path first appears, only one of the state transition estimation processes needs to be advanced, and the other state transition estimation result is The same one as the one of the estimation results may be continuously output. In this way, the estimated results of the two state transitions are collated, it is detected that the two match, and the maximum likelihood decoding process based on the state transition estimation after the detection is performed by one circuit. Increase the operating efficiency of
It is possible to suppress power consumption and the like.

FIG. 6 shows a circuit configuration for specifically realizing the block maximum likelihood estimation of FIG. The circuit configuration shown in FIG. 6 corresponds to each maximum likelihood decoding device 104 in the embodiment of FIG. In this embodiment, the sample values of the signal blocks input from the input terminal 500 (the output of the signal distribution device 103 in FIG. 1) are respectively input block buffer storage devices 50.
Data is sequentially stored in each of the 2 storage cells by block distribution 501 (corresponding to 105 in FIG. 1). The signal value of each storage cell can be read out individually via the output line 503,
It is input to the maximum likelihood sequence estimators 504a and 504b, respectively. The two maximum likelihood sequence estimators 504a and 504b are provided by the decision units 505a and 505b.
The maximum likelihood sequence estimation assuming the two starting states respectively corresponding to FIGS. 5 (a) and 5 (b) is realized by the same principle configuration as the technique shown in FIG. The contents of each storage cell 502 (corresponding to 106 in FIG. 1) are sequentially processed. Then, the determination units 505a and 505b
Then, the value of the bit of the decoding result whose state transition has been determined is written to the corresponding bit position in the decoding registers 507a and 507b. Therefore, by the instructions of the determination units 505a and 505b, the register bit position is designated through the address lines 511a and 511b, and the bit information is designated at the designated bit position in the decoding registers 507a and 507b through the register write devices 506a and 506b. Write. The comparison detector 516 constantly compares the results of the estimated state transitions of the two maximum likelihood sequence estimators 504a and 504b, and with respect to the input value from the storage cell of the same input block buffer storage device 502, both, It detects that the results of the estimated state transitions match, and instructs to stop the operation of the maximum likelihood sequence estimator 504b after this matching detection. At the same time, the address switch 517 causes the decoding register 507b
The input address line 511b is switched to 511a, and the same recording is made in the subsequent decoding registers 507a and 507b based on the estimation result of the determination unit 504a. The determination units 505a and 505b are shown in FIG.
Branch address registers 508a and 508b are provided for recording the positions of the start branch paths in (a) and FIG. 5 (b), respectively. Similarly, pointer registers 509a and 50a respectively storing the positions of the final branch paths shown in FIGS. 5 (c) and 5 (d).
9b is provided, and a series of state transition estimation processing is performed by the determination unit 505a.
As a result of termination at 505b, this records the bit position of the final branch path. At the same time, the state of the final branch path at this time is stored in the state registers 510a and 510b respectively, and referring to this, the state of the final branch path in this block is shown in FIGS. 5 (c) and 5 (d). It is possible to know which case. To determine the decoding result of the start branch path of the block, the state transition estimation connected to this is referred to from the state of the last branch path of the previous block from the terminal A1 of the previous block decoder, and the maximum likelihood sequence estimation is performed. Which of the branch address registers 508a and 508b corresponding thereto is selected by the selector 521, and the formula (Equation 7 ) Or the value corresponding to y (k) in (Equation 8) is read by the selector 523. The decision circuit 523 executes the decision of the equation (Equation 7) or (Equation 8) with the value of y (p) referred to by the terminal A2 from the previous block decoder, and sets the decoding result for the start branch path to 523a. Instructed by 523b and written in the decryption registers 507a and 507b. (Write bit positions are indicated on address lines 513a and 513b). Further, the output 523c of the determination circuit 523 also gives the decoding result for the final branch path of the previous block. On the other hand, the content of the address pointer 509a of the determination unit 504 is referred to by the selector 519,
The signal value corresponding to the final branch path of this block is read from the storage cell of the input block buffer storage device 502 and sent to the decoding device of the next block through the terminal A2. Similarly, the state of the final branch path of the main block indicated by the state register 510a is sent to the next block decoding device through the terminal A2 and processed in the same manner. By completing the above processing, the decoded bit string corresponding to the signal block stored in the input block buffer storage device 502 is set in the decoding register 507a or 507b. Of the two decoding registers 507a and 507b, the selector 524 selects the content of the decoding register on the side corresponding to the state of the branch path indicated by the terminal A1 of the previous block decoder. Then, the data can be output to the output terminal 525 by reading each bit in parallel. By providing a plurality of decoders with the above configuration in parallel and performing decoding by perfect maximum likelihood sequence estimation for each block, it is possible to significantly speed up decoding processing without degrading decoding performance. is there.

FIG. 9 shows an embodiment in which the decoding device of the present invention is applied to a magnetic recording / reproducing device. A signal reproduced from the recording medium 901 through the reproducing head 902 is amplified to a predetermined signal level by the amplifier 903, and the analog filter 90
After removing the noise by 4, it is sampled into discrete signal values through an analog / digital converter 905. The discrete signal value is waveform-shaped by the digital filter 906 and then supplied to the decoding device 102 of the present invention. Decryption device
In 102, a signal distribution device 103 divides a continuous discrete signal value into blocks, which are supplied to a maximum likelihood decoding device 104 provided in parallel to perform decoding processing respectively. Then, the decoding results individually read from the parallel reading line 109 are selected by the selection device 110.
Are sequentially selected with the parallel output line 111 to the code demodulation circuit 112.
And the data is transferred to the upper recording system controller 907 after demodulation processing. By the decoding device 102 of the present invention, the data processing and the transfer after the decoding process are parallelized, and the speed of the reproducing device is increased.

[0047]

As described above, the maximum likelihood decoding device capable of operating at a higher speed than the single operation speed is provided by combining circuits in which the operation speed is limited by the operation clock and other restrictions when operating independently. be able to. Further, since the decoding result is obtained in parallel output, parallel processing is possible after this decoding device, and the circuit operation as a whole becomes faster than the time series signal processing.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a basic configuration of the present invention.

FIG. 2 is a diagram illustrating the principle of block maximum likelihood sequence estimation.

FIG. 3 is an example of block maximum likelihood decoding according to the present invention.

FIG. 4 is a second embodiment of block maximum likelihood decoding according to the present invention.

FIG. 5 shows a third embodiment of block maximum likelihood decoding according to the present invention.

FIG. 6 is an embodiment showing a specific configuration of a decoding device 104.

FIG. 7 is a diagram illustrating an embodiment of a maximum likelihood decoding device.

FIG. 8 is a diagram illustrating sequence estimation by a conventional maximum likelihood estimator.

FIG. 9 is a diagram illustrating the configuration of a magnetic recording / reproducing apparatus using the present invention.

[Explanation of symbols]

500 ... Input terminal, 501 ... Block distributor, 502 ... Input block buffer storage device, 503 ... Output line, 504a ^- b ... Maximum likelihood sequence estimator, 505a ^- b ... Judgment part, 506a ^- b ... Register writing device, 507a ^- b ... decoding register, 508a ^- b ... branch address register, 509a ^- b ... pointer register, 510a ^- b ... status register, 511,512,513,518a ^- b ... address lines, 514a ^- b ... write lines, 515a ^- b ... output line, 516 ... Comparison detector, 523 ... Judgment circuit, 519,522 ... Data selector, 516a ... Selection instruction signal, 5
17, 521, 523, 524 ... Selector, 523a ^- c ... Write instruction signal line, 524a ... Selection signal line, 525 ... Output terminal.

Claims (16)

[Claims] 1. In a communication or storage channel, 2
A method of decoding an original code string by estimating a maximum likelihood string from discrete timing values of an output signal based on a binary code string,
The discrete timing value sequence of sequentially input signals is divided into signal blocks of a predetermined length, and each of the signal blocks is independently subjected to decoding processing by maximum likelihood sequence estimation to obtain the original code sequence, A decoding method characterized in that a code string for the signal block is output in an order in which the signal block is divided to obtain a composite signal value string corresponding to the original code string. 2. The length of the signal block is k + 1 bits or more when the maximum number of consecutive bits "0" in the binary code string to be used is k bits. Decryption method described in. 3. The decoding method according to claim 2, wherein decoding is performed by adding at least k + 1 surplus signal value sequences continuous before and after the signal block. 4. The composite processing line, wherein fixed length code bits are added to the signal block so that the number of code bits "1" in a code block corresponding to the signal block is limited to a predetermined number. The decoding method according to claim 1, wherein the decoding method is performed. 5. In a communication or storage channel, 2
A device for decoding an original code string by estimating a maximum likelihood string from discrete timing values of an output signal based on a binary code string,
Means for dividing the sequentially input binary coded signal sequence into signal blocks of a predetermined length; means for sequentially supplying to each of a plurality of maximum likelihood sequence estimators provided with the signal block as a unit; A code bit of a decoded code string output from each of the likelihood sequence estimators is input in parallel, and means for sequentially selecting the parallel output results of the sequentially selected decoded code strings and outputting them in parallel is provided. Characterizing decoding device. 6. The maximum number of consecutive bits "0" in the binary code string is k bits, and the length of the signal block is k.
The decoding device according to claim 5, wherein decoding is performed using the signal block divided into a length of +1 bit or more. 7. The decoding apparatus according to claim 5, wherein decoding is performed using a new signal block to which k + 1 or more surplus signal value sequences continuous before and after the signal block are added. . 8. A means for generating a code block by adding fixed-length code bits so that the number of code bits "1" becomes a predetermined number in the signal block, and a decoding process is performed using the code block. The decoding device according to any one of claims 5 to 7, which is performed. 9. The maximum likelihood sequence estimator sequentially outputs first storage means for storing each discrete signal value forming the supplied signal block and contents of the first storage means. Means for performing maximum likelihood sequence determination, second storage means for storing the decoded code bit string from the obtained maximum likelihood sequence determination result, and each bit of the decoded code bit sequence stored in the second storage means. 9. The decoding device according to claim 5, further comprising means for outputting in parallel. 10. The maximum likelihood sequence estimator sets a different initial state to obtain a plurality of maximum likelihood sequence determination results for input unit signal blocks, and a plurality of maximum likelihood sequence determination results. A plurality of storage means for respectively storing, a comparison detection means for detecting a match of the plurality of maximum likelihood sequence determination results, and a maximum likelihood sequence determination result of 1 when the maximum likelihood sequences match The initial state of the signal block is determined based on the result of the maximum likelihood sequence estimation of the signal block one unit before, and the maximum likelihood sequence determination result having the initial state that matches the determined initial state is stored. 10. A selection means for selectively outputting is provided.
The decoding device according to any one of 1. 11. A communication receiver comprising the decoding device according to any one of claims 5 to 10. 12. A storage device having the decoding device according to claim 5 mounted therein. 13. The decoding method according to claim 4, wherein the predetermined number is an odd number. 14. The decoding method according to claim 4, wherein the predetermined number is an even number. 15. The decoding device according to claim 8, wherein the predetermined number is an odd number. 16. The decoding device according to claim 8, wherein the predetermined number is an even number.