JPH08124102A - Write driver circuit - Google Patents

Abstract

PURPOSE: To provide a write driver circuit capable of speedily operating the writing even under a low power source voltage. CONSTITUTION: This circuit is provided with first and second PNP input transistors QP1, QP2 whose bases are supplied with a pair of complementary input signals respectively and first and second NPN output transistors Q1, Q2 in inverted Darlington state. A first resistance elements R1 is provided between the emitter of the PNP transistor and the collector of corresponding NPN output transistor and a second resistance element Ra is provided between the collector common for the first and the second NPN output transistors Q1, Q2 and a power source. Clamping voltages are supplied to collectors of the first and the second PNP transistors QP1, QP2 and third and fourth NPN output transistors Q3, Q4 connected respectively to the first and second NPN output transistors Q1, Q2 in serial and complementarily subjected to switch-controls are provided. Thus, an inductive head is driven by consituting a bridge circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read / write integrated circuit, for example, for a composite head using an MR (magnetoresistive effect element) head as a read head and an inductive head as a write head. It is related to the technology that is effectively used.

[0002]

2. Description of the Related Art As an example of a drive circuit for a current control type magnetic head, there is an ISC S.C.
Session 17 / Disc-Drive Electronics / Paper (ISSCC "94 SESSION17 / DISK-DRIVE ELCTR
ONICS / PAPER) FA17.6, PP. There are 286 to 287. In this circuit, as shown in FIG. 13, a pair of transistors in the upper stage is composed of PNP transistors QP1 and QP2, and a pair of transistors in the lower stage is composed of NPN transistors Q3 and Q4. QP1 and Q4 are turned on to pass a current through the magnetic head L, and the low level of the input signal WDN turns on the transistors QP2 and Q3 so that a current flows through the magnetic head L in the opposite direction.

[0003]

In the current control type magnetic head drive circuit described above, since the upper transistor uses the PNP transistors QP1 and QP2, the NPN transistor is used to pass the necessary drive current. It is impossible to use a transistor having a larger size than that of the case where it is used, and the head terminal voltage cannot be raised above the power supply voltage VCC. When the head terminal voltage is small as described above, it takes time to release the energy stored in the inductance component of the magnetic head when the write current is switched, and the high speed operation is limited. Further, the damping resistor provided for optimizing the braking of the write current at the time of switching the current causes a problem that a useless current flows in a steady state and a substantial write current flowing in the magnetic head is reduced.

The inventors of the present application have considered using an inverted Darlington circuit composed of a PNP transistor and an NPN transistor as the upper write transistor. In this case, in addition to the problems described above, in a read / write integrated circuit in which a plurality of write drivers are mounted, in order to write position data (servo data) on a plurality of magnetic disks at high speed. It is convenient to provide a multi-servo write operation in which all the magnetic heads are operated at the same time to perform the writing operation at the same time. However, in a system in which the number of magnetic disk surfaces is smaller than the number of write driver circuits mounted in the read / write integrated circuit, the head terminals corresponding to such write drivers are opened, and the above-mentioned inverted Darlington is used. It has been clarified that the use of the circuit causes a problem that a large write current flows in the PNP transistor on the input side, which exceeds the current allowable value.

An object of the present invention is to provide a write driver circuit capable of high speed write operation even under a low power supply voltage. Another object of the present invention is to provide a write driver circuit capable of multi-servo write operation. Still another object of the present invention is to provide a write driver circuit that enables setting of a write current with high accuracy. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the first and second PNP input transistors having a pair of complementary input signals respectively supplied to their bases are provided with the first and second NPN output transistors in the inverted Darlington configuration, and the corresponding PNP input is provided. A first resistance element is provided between the emitter of the transistor and the collector of the NPN output transistor, and a second resistance element is provided between the common collector of the first and second NPN output transistors and the power supply voltage. Is provided, and a clamping voltage is supplied to the collectors of the first and second PNP transistors, and the first and second NPs are provided.
Third and fourth NPN output transistors, which are connected in series with the N output transistor and are switch-controlled in a complementary manner, are provided, and the connection point of the first and third output transistors and the second and fourth outputs are provided. The inductive head is connected between the connection point of the transistor and the first and second output terminals, respectively.

[0007]

According to the above means, the voltage between the output terminals at the time of current switching can be set higher than the power supply voltage in accordance with the withstand voltage between the base and the emitter of the NPN transistor, so that the write current can be switched at high speed. In the circuit opened in the multi-servo write operation, the current is limited by the first resistance element provided in the emitter of the PNP transistor.

[0008]

1 is a circuit diagram of an embodiment of a write driver circuit according to the present invention. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The write amplifier 51 in the write driver circuit of this embodiment uses an inverted Darlington circuit 41 composed of a PNP transistor QP1 and an NPN transistor Q1 as one upper side circuit. That is, one input signal WD1 is supplied to the base of the PNP transistor QP1, and the collector output of this transistor QP1 is supplied to the base of the NPN transistor Q1. The upper side circuit on the other side has the same configuration as the above PNP.
An inverted Darlington circuit 42 including a transistor QP2 and an NPN transistor Q2 is used.
An input signal WD1N, which is the inverse of the input signal WD1, is supplied to the base of the PNP transistor QP2. That is, the input signals WD1 and WD1N are complementary input signals.

In this embodiment, in the circuit which is opened in the multi-servo write operation, in order to prevent a large write current from flowing in the PNP transistor QP1 or QP2, the emitter resistance R1 is respectively applied to the emitters of the transistors QP1 and QP2. And R2 are provided. The power supply voltage VCC is supplied to the collectors of the NPN transistors Q1 and Q2 and the emitter resistors R1 and R2 via a resistor Ra.

The emitter of the transistor Q1 is provided with a lower side NPN transistor Q3 which is switch-controlled complementarily thereto. Similarly, the transistor Q2
The emitter of is provided with a lower NPN transistor Q4 whose switch is complementarily controlled. These transistors Q1 to Q4 form a bridge circuit, and the input signal WD2 is supplied to the base of the transistor Q3.
The input signal WD2N is supplied to the base of the transistor Q4.

For example, the input signals WD1 and WD2 are at a low level, and the other input signal WD1 having a complementary relationship with it.
When N and WD2N are at the high level, the PNP transistor QP1 is turned on and a base current is passed through the NPN transistor Q1, so that the transistor Q1 is also turned on. At this time, the NPN transistor Q4 is turned on by the high level of the input signal WD2N, and the write current Iw flows from the output terminal X to the output terminal Y as shown in FIG. The inverted Darlington circuit 41 serves as a current source, and the current value of the write current Iw is determined by the voltage of the input signal WD1 and the resistance Ra.

When the write current Iw as described above is flowing, the bias current ISW1 and the base current of the NPN transistor Q1 flow in the PNP transistor QP1. The current value of these combined currents is set small, and accordingly, the element area of the PNP transistor QP1 is formed small. Since only a small current as described above flows through the emitter resistor R1, the voltage drop there is small, and most of the voltage corresponding to the input signal WD1 is applied to the resistor Ra. As a result, in the normal operating state, the input signal WD1
The current value of the write current Iw is determined by the voltage and the resistance Ra.

Contrary to the above, when the input signals WD1 and WD2 are at high level and the other input signals WD1N and WD2N which are complementary to each other are at low level, the PNP transistor QP2 is turned on and the NPN transistor QP2 is turned on.
Since the base current flows through the transistor Q2, this transistor Q2 is also turned on. At this time, the input signal WD
The NPN transistor Q3 is turned on by the high level of 2N, and the write current Iw flows from the output terminal Y to the output terminal X in the opposite direction to that shown in FIG. Similarly to the above, the inverted Darlington circuit 42 functions as a current source, and the current value of the write current Iw in the reverse direction is similarly determined by the voltage of the input signal WD2 and the resistance Ra.

Although not particularly limited, in this embodiment, the bias currents ISW1 and ISW2 are made to flow corresponding to the corresponding input signals WD1 and WD1N, respectively. That is, the PNP transistor QP
Since the operating speed of 1 and QP2 is slow, a bias circuit 31 for pulling out the base is provided. When the input signal WD1 is low level, a transistor QP for receiving it
The current ISW1 is caused to flow by the bias circuit 31 composed of the current mirror type NPN transistors Q5 and Q6.
The inverted Darlington circuit consisting of 1 is turned on at high speed. This also applies to the other bias circuit 32.

FIG. 4 is a schematic block diagram of an embodiment of a read / write integrated circuit equipped with a write driver circuit according to the present invention. Although not particularly limited, the read / write integrated circuit 61 includes eight magnetic heads L.
The write driver circuits # 0 to # 7 corresponding to are mounted. However, not all circuits are used when it is incorporated into the system. For example,
In a system with three magnetic disks 81, one
Since a total of six write drivers # 0 to # 5, two on each of the upper surface and the lower surface, are used, the output terminals 91 of the two write drivers # 6 and # 7 are in a high impedance state.

In a magnetic disk drive using a read / write integrated circuit including a plurality of write hiber circuits, at least position data (servo data) is written on all disks before shipment. At this time, since it takes time to write the servo data for each disk one by one and the efficiency is low, it is convenient to provide a multi-servo write function of simultaneously operating all the magnetic heads to write the servo data at one time.

FIG. 2 is a circuit diagram of the unused write driver circuit. That is, the magnetic head L as a load is not connected to the output terminals X and Y. When the multi-servo write function as described above is provided, a write current flows in the write driver circuit to which the magnetic head L is not connected, as in the write driver circuit to which another magnetic head L is connected. To be

In the state where the magnetic head is not connected as described above, the input signal WD1 goes low and the PNP transistor QP1 is turned on. Accordingly, even if the transistor Q1 is turned on, the emitter of the transistor Q1 is in a high impedance state. If so, all the write current Iw will flow through the PNP transistor QP1. In the circuit to which the magnetic head L is connected as described above, the PNP transistor QP1 is the transistor Q1.
Since only the base current and the bias current ISW1 are passed, it is formed with a small size. Therefore,
If the normal write current flows through the transistor QP1 as it is, it exceeds the allowable current value and is destroyed.

In this embodiment, the resistor R1 is connected to the emitter of the PNP transistor QP1 in order to prevent such element destruction. As described above, when the output terminal is in the high impedance state, the write current flows in the PNP transistor on the input side, and the input voltage W
Resistors R1 and Ra are inserted in series with respect to D1. That is, the current Iw ′ flowing at this time is made small like Ra / (R1 + Ra) of the normal write current Iw, and the element breakdown as described above can be prevented.

FIG. 3 is a circuit diagram of another embodiment of the write driver circuit according to the present invention. In this embodiment, the resistors R1 and R2 are shared to reduce the number of elements. That is, the emitters of the PNP transistors QP1 and QP2 are made common and the common resistor R1 is connected. In this embodiment, one of the inverted Darlington circuits 41 and 42 is always in the off state when the other is in the on state according to the complementary input signals WD1 and WD1N. This makes it possible to replace the resistors R1 and R2 with one resistor R1 or R2 as described above.

In the embodiment of FIG. 1 or 3, the inverted Darlington circuits 41 and 42 are provided with voltage clamp circuits 21 and 22, respectively, for the following reason. That is, when the input signals WD1 and WD2 are low level and the input signals WD1N and WD2N are high level, the write current Iw flows from the output terminal X to the output terminal Y as shown in FIG. When the input signals WD1 and WD2 are switched to the high level and the input signals WD1N and WD2N are switched to the low level from this state, PN
P transistor QP1 and NPN transistor Q1 and Q
4 is turned off, and PNP transistors QP2 and NP
The N transistors Q2 and Q3 are turned on, and the write current Iw is switched so as to flow in the opposite direction.

When the write current Iw is inverted at high speed,
A counter electromotive voltage of L · dIw / dt is generated between the head terminals X and Y. The voltage at the output terminal X is 0V + the transistor Q3 depending on the ON state of the transistor Q3.
The collector-emitter voltage VCE becomes about 0.4V. The voltage of the output terminal Y rises with reference to the voltage of the output terminal X, and since the NPN transistor Q2 is in the ON state, its base potential also rises correspondingly.
At this time, the voltage clamp circuit 22 is provided to prevent the PNP transistor QP2 from being saturated.

That is, the collector potential of the PNP transistor Q2 (base of the transistor Q2) is fixed at the clamp voltage VCP + VBEQP6. The voltage at the output terminal Y can be further increased even if the base of the transistor Q2 is voltage clamped as described above. The voltage of the output terminal Y to which the emitter of the transistor Q2 is connected is
The reverse withstand voltage between the base and the emitter of the transistor Q2 can be increased as much as the reverse withstand voltage allows.

As shown in the voltage waveform diagram of FIG. 7, the back electromotive force can be increased to a voltage higher than the power supply voltage VCC, and the product of the voltage level and time releases the energy stored in the inductance component. Done. By raising the voltage to a voltage higher than the power supply voltage VCC as in this embodiment, the energy stored in the inductance component can be released within a shorter time, and the write current can be switched in the opposite direction at high speed. Can be Note that, in FIG. 7, the latter half shows the voltage VY of the output terminal Y as described above.

In a normal manufacturing process, the breakdown voltage between the base and emitter of the transistor Q2 can be set to 8-9V.
Even when the power supply voltage VCC is as low as 5V, the voltage VX-VY across the magnetic head is approximately 10V.
Since it can be made higher than the above, even when the power source voltage is as low as 5V, current switching can be performed at high speed as in the case of using a high voltage as 12V. Therefore, if the withstand voltage of the base and emitter of the transistors Q1 and Q2 is made higher, the write current can be substantially switched correspondingly at high speed.

FIG. 5 is a circuit diagram of another embodiment of the write driver circuit according to the present invention. In this embodiment, the bias circuit 21 in the embodiment of FIGS.
And 23 are replaced by resistors RSW1 and RSW2, respectively. That is, by setting the resistance value to be large with respect to the voltage applied to the resistors RSW1 and RSW2, the bias current ISW1 which is substantially constant current,
The ISW2 can be made to flow. If necessary, the bias currents ISW1 and ISW2 may be respectively formed by combining the bias circuits 21 and 22 and the high resistances RSW1 and RSW2 as in the embodiment of FIG. 1 or FIG.

FIG. 8 shows a circuit diagram of another embodiment of the write driver circuit according to the present invention. In this embodiment, a damping resistor RD is provided at each of the output terminals X and Y.
1 and RD2 are provided. In this embodiment, in order to efficiently obtain the write current, the damping resistors RD1 and RD2 are not provided between the power supply voltage VCC as in the conventional case, but a diode DD as a unidirectional element.
1, DD2 connected in series with the output terminal X,
It is provided between Y and the voltage sources VD1 and VD2 that are changed corresponding to the respective input signals WD1 and WD1N.

The write current Iw becomes a secondary indicial response due to the inductance component, resistance component and parasitic capacitance of the magnetic head. The damping resistors RD1 and RD2 are provided in order to brake it and optimize it as shown in the waveform diagram of FIG. If the damping resistors RD1 and RD2 are provided between the output terminals X and Y and the power supply voltage VCC as in the conventional case, a reactive current flows in the damping resistor provided at the low-level side output terminal. . This reactive current has a low level of about 0.4 V at the output terminal as described above, so (VCC-0.4)
It is a size that cannot be ignored like / RD1.

In this embodiment, instead of connecting the damping resistors RD1 and RD2 to the fixed power supply voltage VCC as in the conventional case, the damping resistors RD1 and RD2 are connected between the voltage sources VD1 and VD2 which change according to the input signals WD1 and WD1N. It should be provided. For example, when the input signals WD1 and WD2 are low level and the input signals WD1N and WD2N are high level, the voltage VD1 is high level and VD2 is low level. In this way, when the write current is passed from the output terminal X to the output terminal Y, the voltage VD2 corresponding to the output terminal Y on the low level side is at the same low level as that of the output terminal Y, so a reactive current flows there. I can do it.

In this embodiment, the diodes DD1 and DD are
Since 2 is inserted in series, damping resistance RD
1 and RD2, when the current is not desired to flow, the voltage VD1
And VD2 may be set to low level. Such voltage V
Depending on the low level of D1 and VD2, the above diode DD
1 and DD2 are turned off, and the damping resistors RD1 and RD2 can be disconnected from the output terminals X and Y.

FIG. 9 shows a specific circuit diagram of an embodiment of the write driver circuit according to the present invention. In this embodiment, a concrete circuit of the voltage sources VD1 and VD2 to which the damper resistors RD1 and RD2 are connected is shown. NPN emitter follower transistors Q9 and Q10 are provided at the collectors of the PNP transistors QP3 and QP4 that drive the bias circuit, and the damping resistors RD1 and RD2 are connected to the emitters of these transistors Q9 and Q110.

As described above, when the input signals WD1 and WD2 are at the low level and the input signals WD1N and WD2N are at the high level, the transistor QP3 is turned on and the 3VF formed by the series diodes D1 to D3.
(VG is a forward voltage) is a high level voltage VD
1 is supplied to the dipping resistor RD1. On the other hand, since the transistor QP4 is turned off by the high level of the input signal WD1N, the transistor Q10
Turns off and no current flows through the damping resistor RD2. That is, even if the low-level potential corresponding to the low level of the output terminal Y is not set as described above,
Even if the current path is cut off as described above, the same effect can be obtained.

In this embodiment, the input signal WD2 supplied to the bases of the lower output transistors Q3 and Q4.
The circuit forming WD2N and WD2N is also shown. Input signal W
D1 and WD1N are PNP transistors QP7 and QP8.
Supplied to the base of. The emitters of these transistors QP7 and QP8 have emitter resistors R7 and R, respectively.
8 is provided, and a load resistance is provided between the collector and the ground potential of the circuit. In the figure, the resistance inserted between the base and emitter of the output transistors Q3 and Q4 is the collector load resistance of the transistors QP7 and QP8.

The voltage WD2 supplied to the base of the transistor Q3 is P when the input signal WD1N is supplied to the base.
The input signal is inverted by the NP transistor QP8 and changes in phase with the input signal WD1. In addition, the voltage WD2 supplied to the base of the transistor Q5
N is inverted by the PNP transistor QP7 whose input signal WD1 is supplied to the base, and the input signal W
It is an input signal that changes in phase with D1N. Further, the bias circuit includes a current mirror circuit as described above and a high resistance R.
It is composed of resistors R5 and R6 corresponding to SW1 and RSW2.

FIG. 10 shows a concrete circuit diagram of an embodiment of the write driver circuit according to the present invention. In this embodiment, the write current Iw and the bias current ISW are
1, a specific circuit for setting ISW2 is shown. In this embodiment, the currents Iw and ISW are determined by a substantial current mirror circuit. That is, the transistor Q forming the inverted Darlington circuit
P1, Q1 and PN configured similar to QP2 and Q2
P-transistors QP1 'and Q1' and QP2 'and Q2'
As a resistance provided to the resistor Ra, a resistance 10 × Ra having a resistance value 10 times that of the resistance Ra and a resistance 10 × R1 having a resistance value 10 times that of the resistances R1 and R2 are provided. , 10 × R2 are connected respectively.

In the collectors of the transistors Q1 'and Q2', the constant current of the constant current source IN1 set to 1/10 of the write current Iw is supplied in a complementary manner corresponding to the complementary input data D and DN. And the transistor QP1 '
And 1 of the bias current ISW to the collectors of QP2 '
The constant current of the constant current source IP1 set to 10 is supplied in a complementary manner corresponding to the complementary input data D and DN. Transistor QP1 'through which the constant current Iw / 10 flows
(Or QP2 ') and the PNP transistor QP1 of the inverted Darlington circuit that forms the write current.
Since the base of (QP2) is made common and the resistance ratio of the resistors R1 and Ra provided on the emitter side is set to 10: 1 as described above, it is output from the emitter of the transistor Q1 or Q2. The write current Iw is set to 10 times the current of the constant current source IN1 with high accuracy.

That is, in the semiconductor integrated circuit, the transistors QP1, QP1 'and Q1 are not affected by the manufacturing process.
And Q1 ′ can be matched with high accuracy, and the ratio of the resistance values can be formed with high accuracy, so that the write current Iw and the bias current ISW can be set with high accuracy. Transistors QP9 and Q
P10 is a total of four PNs that share the above base.
This is for absorbing the base currents of the P-transistors so that the above current ratio is not affected by these base currents. As a result, a stable write operation can be performed without being affected by fluctuations in the power supply voltage.

FIG. 11 shows a concrete circuit diagram of an embodiment of the operating current setting section in the write driver circuit according to the present invention. In this embodiment, the write current source forms a reference constant current. The write current source applies a constant voltage formed using the base and emitter of the transistor Q to an external resistor Rext connected via an external terminal to form a desired reference constant current Iwc. When such an external resistor Rext is used, it is possible to compensate for the process variation of the constant voltage and set an arbitrary write current corresponding to the magnetic disk device in which it is mounted.

This reference constant current Iwc is converted into a pushing current by a current mirror circuit composed of PNP transistors QP11 and QP12, and is made to flow to the NPN transistor Q11. The constant currents IP1 and IP2 are formed by the transistor Q11 and the transistors Q13 and Q14 in the current mirror form. That is,
When the transistors Q11, Q12, and Q13 have the same emitter size, by setting the resistance ratio of the emitter resistors provided in the emitters to a desired ratio, the current set with a high accuracy ratio with respect to the reference current Iwc is set. IP1 and IN1 can be obtained. Transistor Q
Reference numeral 12 operates as a supply source of the base currents of the transistors Q11, Q13 and Q14 in the current mirror form as described above, and sets the current ratio with high accuracy.

In this embodiment, the constant current as described above is I
A stable clamp voltage VCP is formed using wc. That is, the diodes D7 and D8 are connected in series to the collector of the PNP transistor QP12, and the base-emitter voltage of the transistors Q11 and Q12 and the forward voltage of the diodes D7 and D8 are about 2VF + 2VBE.
To form the clamp voltage VCP.

The above constant currents IP1 and IN1 are supplied to the emitters of the differential transistors Q15, Q16 and Q17, Q18 which form the current switch circuit. Complementary write data D and DN are supplied to the bases of these differential transistors Q14, Q17 and Q15, Q18. That is, the transistors Q14 and Q15 correspond to the constant current sources IP1 and IN1 of the embodiment shown in FIG. 10, and the transistors Q16 and Q18 correspond to the constant current sources IP1 and IN1.

The constant currents IP1 and IN1 switched by the input data D and DN as described above are supplied to circuits similar to the inverted Darlington circuit (QP1 ', Q1 and resistor 10 × R) constituting the upper side circuit of the write driver.
a, 10 × R1) and (QP2 ′, Q2 and resistance 10 × R
a, 10 × R2), and the transistor QP1 ′
Input signals WD1 and WD1N are formed from the bases of QP2 'and QP2', and are supplied to the above-described write driver circuit indicated by a black box in FIG. The clamp voltage VCP is also supplied to the voltage clamp circuits 21 and 22 included in the write driver circuit.

FIG. 12 is a block diagram showing an embodiment of a read / write integrated circuit in which the write driver circuit according to the present invention is mounted and its external circuit. The read / write integrated circuit IC according to the present invention comprises a plurality of head circuits. That is, in addition to the MR head 1 and its read preamplifier 2 shown in FIG.
An R head and its read preamplifier are provided, and one postamplifier output circuit 8 is provided for each of these eight circuits.
Are provided in common. The read preamplifier 2 in the figure also includes a level shift 3.

A pair of output signals of the post-amplifier output circuit 8 is supplied to an AGC (automatic gain control) amplifier 11 via a capacitor having a relatively large capacitance value so as to cut a DC output offset. This AGC amplifier 11
The output signal of is waveform-shaped by the waveform shaping circuit 12,
The pulse converting circuit 13 transmits the pulse signal to a higher-order circuit such as a magnetic disk control circuit.

In order to increase the storage capacity of the magnetic disk device, a plurality of the read / write integrated circuit ICs are mounted, and the postamplifier output circuit 8 outputs the postamplifier output circuit of another read / write integrated circuit. The terminals are commonly connected. The post-amplifier output circuit 8 has a tri-state output function so that only the output signal of the selected read / write integrated circuit is transmitted to the AGC amplifier through the capacitor. In other words, the output of the postamplifier output circuit 8 of the read / write integrated circuit IC placed in the non-selected state is set to the high impedance state.

The write system circuit included in the read / write integrated circuit comprises a frequency dividing circuit 6 and a write driver circuit 7. The output of the frequency dividing circuit 6 is commonly transmitted to the input of a plurality of write drivers 7, and the write driver 7 corresponding to the magnetic head selected by the selection signal is activated to drive the magnetic head 5. The frequency dividing circuit 6 is
The current source is made into a small current when not writing to reduce power, and a normal current is made to flow only when writing. That is, a minute current is supplied to the frequency dividing circuit 6 when not writing. At the time of writing, the normal operating current is supplied to the frequency dividing circuit 6. An abnormality detection circuit 9 detects an abnormality such as disconnection or short circuit of the MR head 2 or the magnetic head 5. The mode switching circuit switches between the write mode and the read mode.

The functions and effects obtained from the above-mentioned embodiment are as follows. (1) First and second NPs in inverted Darlington form with respect to the first and second PNP input transistors whose complementary pair of input signals are respectively supplied to the bases.
An N output transistor is provided, and a first resistance element is provided between the emitter of the corresponding PNP input transistor and the collector of the NPN output transistor.
And a second resistance element between the common collector of the second NPN output transistor and the power supply voltage,
Clamping voltage is supplied to the collectors of the first and second PNP transistors, and third and fourth NPN output transistors connected in series with the first and second NPN output transistors and complementarily switch-controlled. And a connection point between the first and third output transistors and a connection point between the second and fourth output transistors, respectively.
By connecting an inductive head between them as an output terminal of, the voltage between the output terminals at the time of current switching can be set higher than the power supply voltage corresponding to the withstand voltage between the base and emitter of the NPN transistor. High-speed switching of the current is possible, and in the circuit that is opened in the multi-servo write operation, the PNP
The effect that the current is limited by the first resistance element provided in the emitter of the transistor is obtained.

(2) By the current limiting operation of the above (1), it is possible to use the first and second PNP transistors having a small size and simultaneously operate a plurality of write drivers to have a multi-servo write function. The effect of being able to be obtained is obtained.

(3) A damping resistance element is provided between the first and second output terminals and the first and second power sources that form a voltage that changes corresponding to the input signals corresponding to the first and second output terminals. By connecting in series with a unidirectional element that allows a current to flow from the power supply terminal to the output terminal, it is possible to obtain an effect that a reactive current can be prevented from constantly flowing through the dipping resistor.

(4) An inverted Darlington circuit composed of a PNP type input transistor which receives a pair of complementary input signals and an NPN transistor whose collector output is supplied to the base, and a constant voltage provided in the collector of the PNP transistor. A voltage source circuit formed of a diode in series to form a voltage to be supplied to the damping resistance element, and the current passing through the diode in series is supplied to the current mirror circuit to output its output current to the first and second By using it as the bias current for extracting the base current of the NPN transistor No. 2, the effect that the reactive current due to the damping resistance can be reduced and the current switching operation can be speeded up can be obtained.

(5) The first and second PNP transistors, the first and second NPN transistors, and the first and second PNP transistors
1'and 2'having substantially the same configuration as the resistance element of FIG.
Of PNP transistor and NPN transistor and 1'and 2'resistive elements, and the respective resistance values of the 1'and 2'resistive elements are desired for the first and second resistive elements. Set to have a large ratio of
The first and second constant currents are switched and supplied by a differential current switching circuit that receives complementary input signals to the first 'PNP transistor and NPN transistor and the second' PNP transistor and NPN transistor. Thus, it is possible to obtain the effect that the write current and the bias current set with high accuracy can be obtained.

(6) Arbitrary writing is performed by forming the first and second constant current sources so as to have a predetermined current ratio by a current mirror circuit based on a reference current set by an external resistor. The effect that the current and the bias current can be formed with high precision can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, FIG.
In the first embodiment, the constant current I is applied to only one circuit by the differential transistors Q15 to Q18 for switching the current.
Since P1 and IN1 do not flow, resistors 10xRa and 10x
R1 may be commonly used. That is, the number of elements may be reduced by using a circuit similar to that of the embodiment of FIG. The number of heads connected to the read / write integrated circuit can be arbitrarily set as required. The present invention can be widely used as a write driver circuit.

[0055]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the first and second PNP input transistors having a pair of complementary input signals respectively supplied to their bases are provided with the first and second NPN output transistors in the inverted Darlington configuration, and the corresponding PNP input is provided. A first resistance element is provided between the emitter of the transistor and the collector of the NPN output transistor, and a second resistance element is provided between the common collector of the first and second NPN output transistors and the power supply voltage. Is provided, and a clamping voltage is supplied to the collectors of the first and second PNP transistors, and the first and second NPs are provided.
Third and fourth NPN output transistors, which are connected in series with the N output transistor and are switch-controlled in a complementary manner, are provided, and the connection point of the first and third output transistors and the second and fourth outputs are provided. By connecting the transistor connection point to the first and second output terminals, respectively, and connecting the inductive head between them, the voltage between the output terminals at the time of current switching becomes the withstand voltage between the base and emitter of the NPN transistor. Correspondingly, since it can be set higher than the power supply voltage, the write current can be switched at high speed, and in the circuit opened in the multi-servo write operation, the current is limited by the first resistance element provided in the emitter of the PNP transistor. it can.

By the above current limiting operation, a plurality of write drivers can be simultaneously operated by using the small-sized first and second PNP transistors to provide a multi-servo writing function.

The first and second output terminals and the first voltage forming variable voltage corresponding to the input signals respectively corresponding to the first and second output terminals
Between the second power source and the second power source, a damping resistance element and a unidirectional element that allows a current to flow from the power source terminal to the output terminal are connected in series, so that the dipping resistance is constantly disabled. The electric current can be stopped.

An inverted Darlington circuit composed of a PNP type input transistor for receiving a pair of complementary input signals, an NPN transistor whose collector output is supplied to the base, and a collector of the PNP transistor are provided to form a constant voltage. A voltage source circuit including a diode in series forms a voltage to be supplied to the damping resistance element, and the current passing through the diode in series is supplied to the current mirror circuit to output the output currents of the first and second diodes.
By using it as the bias current for extracting the base current of the NPN transistor, it is possible to reduce the reactive current due to the damping resistor and to speed up the current switching operation.

The first and second PNP transistors, the first and second NPN transistors, and the first 'and second' PNPs having substantially the same structure as the first and second resistance elements.
Transistor and NPN transistor and first ', second'
The resistance value of each of the first 'and second' resistance elements is set so as to have a desired large ratio with respect to the first and second resistance elements. Of P
NP transistor and NPN transistor and second P '
A differential current switching circuit that receives complementary input signals switches the first and second constant currents to the NP transistor and the NPN transistor, and supplies them by switching to supply the write current and bias current set with high accuracy. be able to.

By forming the first and second constant current sources so as to have a predetermined current ratio by a current mirror circuit based on a reference current set by an external resistor, an arbitrary write current and bias can be obtained. The current can be formed with high accuracy.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a write driver circuit according to the present invention.

FIG. 2 is a circuit diagram of a write driver circuit according to the present invention in an unused state.

FIG. 3 is a circuit diagram showing another embodiment of the write driver circuit according to the present invention.

FIG. 4 is a schematic configuration diagram showing an embodiment of a read / write integrated circuit equipped with a write driver circuit according to the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the write driver circuit according to the present invention.

FIG. 6 is a current waveform diagram for explaining an example of the operation of the write driver circuit according to the present invention.

FIG. 7 is a voltage waveform diagram for explaining an example of the operation of the write driver circuit according to the present invention.

FIG. 8 is a circuit diagram showing another embodiment of the write driver circuit according to the present invention.

FIG. 9 is a specific circuit diagram showing an embodiment of a write driver circuit according to the present invention.

FIG. 10 is a specific circuit diagram showing another embodiment of the write driver circuit according to the present invention.

FIG. 11 is a specific circuit diagram showing an embodiment of the operating current setting section in the write driver circuit according to the present invention.

FIG. 12 is a principal block diagram showing an embodiment of a read / write integrated circuit according to the present invention.

FIG. 13 is a circuit diagram showing an example of a conventional write driver circuit.

[Explanation of symbols]

21, 22 ... Voltage clamp circuit, 31, 32 ... Bias circuit, 41, 42 ... Inverted Darlington circuit, 51 ... Write amplifier, 61 ... Read / write integrated circuit, 81 ... Magnetic disk, 91 ... Open output, QP1
... QP12 ... PNP transistor, Q1-Q16 ... NP
N transistor, Ra, R1 to R8 ... Resistor, L ... Magnetic head, D1-8 ... Diode, 1 ... MR head, 2 ... Read amplifier (sense amplifier), 3 ... Level shift, 4 ...
Timing adjusting circuit, 5 ... Writing head (inductive head), 6 ... Dividing circuit, 7 ... Write driver,
8 ... Post-amplifier output circuit, 9 ... Abnormality detection circuit, 10 ...
Mode switching circuit, 11 ... AGC amplifier, 12 ... Waveform shaping circuit, 13 ... Pulsing circuit, 14 ... Write correction circuit, 1
5 ... Upper device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noriaki Hatanaka 2880 Kozu, Odawara-shi, Kanagawa Hitachi Storage Systems Division (72) Inventor Masaki Yoshinaga 2326 Imai, Ome, Tokyo Hitachi Device Development Co., Ltd. In the center (72) Inventor Hiroshi Nagaya 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Go Hirose 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Invention Yuji Soga 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Prefecture, Hitachi Computer Engineering Co., Ltd. (72) Tadao Kaji, 2326, Imai, Ome, Tokyo, Hitachi Device Development Center, Hitachi Ltd.

Claims (7)

[Claims] 1. A first and second PNP input transistor having complementary base signals supplied to respective bases thereof, and a collector of said first and second PNP input transistors having respective bases supplied thereto. First and second NPN output transistors, first resistive elements provided between the emitters of the first and second PNP input transistors and the collectors of the first and second NPN output transistors, respectively, and The second resistance element provided between the common collectors of the first and second NPN output transistors and the power supply voltage, and the first and second NPN output transistors are connected in series, respectively. Third and fourth NPN output transistors which are switch-controlled in a complementary manner by the inverted signal of the input signal, and the first and third
And a connection point of the second and fourth output transistors as a first output terminal and a second output terminal, respectively, and an inductive head is connected between them. circuit. 2. The collector of the first and second PNP input transistors is provided with a voltage clamp circuit for clamping to a voltage such that the PNP input transistor is not saturated. Write driver circuit. 3. A damping resistance element and the above-mentioned damping resistance element are provided between the first and second output terminals and the first and second power supply sources that form a voltage that changes corresponding to input signals respectively corresponding to the first and second output terminals. The write driver circuit according to claim 1 or 2, wherein a unidirectional element that allows a current to flow from the power supply terminal to the output terminal is provided in series. 4. A PNP type input transistor which receives the input signal, and an N whose collector output is supplied to the base.
An inverted Darlington circuit composed of a PN transistor and a voltage source circuit composed of a diode in series provided in the collector of the PNP transistor to form a constant voltage form a voltage supplied from the emitter of the NPN transistor to the damping resistance element. At the same time, the current that has passed through the series-shaped diode is supplied to the current mirror circuit, and the output current of the current mirror circuit is used as the bias current for extracting the base currents of the first and second NPN transistors. 4. The write driver circuit according to claim 3, wherein. 5. The pair of complementary input signals have substantially the same configuration as the first and second PNP transistors, the first and second NPN transistors, and the first and second resistance elements. First 'and second' PNP transistors and N
It is composed of a PN transistor and first 'and second' resistive elements, and the respective resistance values of the first 'and second' resistive elements have a desired large ratio with respect to the first and second resistive elements. And the first and second constant PNP transistors and NPN transistors and the second 'PNP transistor and NPN transistor are set by the differential current switching circuit for receiving complementary input signals. 5. The write driver circuit according to claim 1, wherein the write driver circuit is formed by switching and supplying an electric current. 6. The first and second constant current sources are formed by setting a reference current set by an external resistor to a predetermined current ratio by a current mirror circuit. The write driver circuit according to claim 5. 7. The write driver circuit is paired with a read amplifier which receives a signal from an MR head, and a plurality of circuits are formed by one semiconductor integrated circuit device, and all the write driver circuits are simultaneously activated. 7. The write driver circuit according to claim 1, claim 2, claim 4, or claim 6, which has a write mode.