JPH08116073A - Compound semiconductor wafer and semiconductor device - Google Patents
Compound semiconductor wafer and semiconductor deviceInfo
- Publication number
- JPH08116073A JPH08116073A JP6250561A JP25056194A JPH08116073A JP H08116073 A JPH08116073 A JP H08116073A JP 6250561 A JP6250561 A JP 6250561A JP 25056194 A JP25056194 A JP 25056194A JP H08116073 A JPH08116073 A JP H08116073A
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- layer
- compound semiconductor
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- semiconductor layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、キャリアー濃度の高い
p+ 型化合物半導体層とキャリアー濃度の高いn+ 型化
合物半導体層とを接合してトンネル接合を形成した化合
物半導体ウエハ及び半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor wafer and a semiconductor device in which a tunnel junction is formed by joining a p + type compound semiconductor layer having a high carrier concentration and an n + type compound semiconductor layer having a high carrier concentration.
【0002】[0002]
【従来の技術】図6は従来の半導体装置の断面図であ
る。2. Description of the Related Art FIG. 6 is a sectional view of a conventional semiconductor device.
【0003】同図に示すように半導体装置は、キャリア
ー濃度の高いp+ 型化合物半導体層1とキャリアー濃度
の高いn+ 型化合物半導体層2とを接合してトンネル接
合(p+ n+ 接合)を有する化合物半導体ウエハ3を形
成し、化合物半導体ウエハ3を所定の大きさに切断した
後両半導体層1、2に電極4、5を接合したものであ
る。As shown in the figure, in a semiconductor device, a p + type compound semiconductor layer 1 having a high carrier concentration and an n + type compound semiconductor layer 2 having a high carrier concentration are joined to form a tunnel junction (p + n + junction). Is formed, the compound semiconductor wafer 3 is cut into a predetermined size, and then the electrodes 4 and 5 are bonded to both semiconductor layers 1 and 2.
【0004】[0004]
【発明が解決しようとする課題】ところで上述した従来
の半導体装置は、各半導体層の成長過程や電極に配線等
を接続する際等に熱を加えた場合、p+ 型化合物半導体
層とn+ 型化合物半導体層との間の界面でドーパントが
拡散することにより、p+ n+ 接合の界面(p+ n+ 界
面)の各ドーパントの急峻性が悪くなり、それに伴いp
+ n+ 界面のキャリアー濃度が低くことから、I−V
(電流−電圧)特性においてトンネルピーク電流が低下
してしまう。By the way, in the conventional semiconductor device described above, when heat is applied during the growth process of each semiconductor layer or when connecting wiring or the like to the electrodes, the p + type compound semiconductor layer and the n + type compound semiconductor layer Since the dopant diffuses at the interface with the type compound semiconductor layer, the steepness of each dopant at the interface of the p + n + junction (p + n + interface) becomes poor, and p
Since the carrier concentration at the + n + interface is low, I-V
In the (current-voltage) characteristic, the tunnel peak current is reduced.
【0005】図7に従来のp+ n+ 接合構造で作製した
トンネル接合でのI−V特性の測定結果を示す。同図に
おいて横軸は電圧(V)を示し、縦軸は電流密度(mA
/cm2 )を示している。また、実線L3 が熱処理前
で、破線L4 が熱処理後の測定結果を示している。FIG. 7 shows the measurement results of the IV characteristics of the tunnel junction manufactured with the conventional p + n + junction structure. In the figure, the horizontal axis represents voltage (V) and the vertical axis represents current density (mA
/ Cm 2 ). The solid line L 3 shows the measurement result before the heat treatment, and the broken line L 4 shows the measurement result after the heat treatment.
【0006】同図より熱処理前のピーク電流密度は12
mA/cm2 であり、熱処理後ではわずか1.4mA/
cm2 と熱処理前の1割程度となってしまう。From the figure, the peak current density before heat treatment is 12
mA / cm 2 and only 1.4 mA / after heat treatment
This is about 10% of that before the heat treatment, which is cm 2 .
【0007】そこで、本発明の目的は、上記課題を解決
し、I−V特性におけるピーク電流密度を高く、熱を加
えてもピーク電流密度が低下しない化合物半導体ウエハ
及び半導体装置を提供することにある。Therefore, an object of the present invention is to solve the above problems and to provide a compound semiconductor wafer and a semiconductor device which have a high peak current density in the IV characteristic and do not decrease in the peak current density even when heat is applied. is there.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するため
に本発明は、キャリアー濃度の高いp+ 型化合物半導体
層とキャリアー濃度の高いn+ 型化合物半導体層とを接
合してトンネル接合を形成した化合物半導体ウエハにお
いて、p+ 型化合物半導体層とn+ 型化合物半導体層と
の間にi層を形成したものである。In order to achieve the above object, the present invention forms a tunnel junction by joining a p + type compound semiconductor layer having a high carrier concentration and an n + type compound semiconductor layer having a high carrier concentration. In this compound semiconductor wafer, the i layer is formed between the p + type compound semiconductor layer and the n + type compound semiconductor layer.
【0009】上記構成に加え本発明は、p+ 型化合物半
導体層とi層との間の界面にp型ドーパントをδドープ
し、かつ、i層とn+ 型化合物半導体層との間の界面に
n型ドーパントをδドープしたものである。In addition to the above structure, the present invention provides the interface between the p + type compound semiconductor layer and the i layer with δ-doped p-type dopant, and the interface between the i layer and the n + type compound semiconductor layer. Δ-doped with an n-type dopant.
【0010】上記構成に加え本発明は、化合物半導体層
がGaAs又はAlX Ga1-X Asである。In addition to the above structure, in the present invention, the compound semiconductor layer is GaAs or Al X Ga 1-X As.
【0011】上記構成に加え本発明は、p+ 型化合物半
導体層のキャリアー濃度の範囲が1×1018cm-3〜1
×1021cm-3であり、n+ 型化合物半導体層のキャリ
アー濃度の範囲が5×1017cm-3〜8×1018cm-3
であり、i層の膜厚が3nm〜30nmである。In addition to the above constitution, the present invention provides a p + type compound semiconductor layer having a carrier concentration range of 1 × 10 18 cm -3 to 1.
× 10 21 cm −3 , and the carrier concentration range of the n + type compound semiconductor layer is 5 × 10 17 cm −3 to 8 × 10 18 cm −3.
And the film thickness of the i layer is 3 nm to 30 nm.
【0012】本発明は、キャリアー濃度の高いp+ 型化
合物半導体層とキャリアー濃度の高いn+ 型化合物半導
体層とを接合してトンネル接合を形成し両化合物半導体
層に電極を設けた半導体装置において、p+ 型化合物半
導体層とn+ 型化合物半導体層との間にi層を形成した
ものである。The present invention relates to a semiconductor device in which a p + type compound semiconductor layer having a high carrier concentration and an n + type compound semiconductor layer having a high carrier concentration are joined to form a tunnel junction and electrodes are provided on both compound semiconductor layers. , The p + type compound semiconductor layer and the n + type compound semiconductor layer are formed with an i layer.
【0013】上記構成に加え本発明は、p+ 型化合物半
導体層とi層との間の界面にp型ドーパントをδドープ
し、かつ、i層とn+ 型化合物半導体層との間の界面に
n型ドーパントをδドープしたものである。In addition to the above structure, the present invention provides that the interface between the p + type compound semiconductor layer and the i layer is δ-doped with a p type dopant, and the interface between the i layer and the n + type compound semiconductor layer. Δ-doped with an n-type dopant.
【0014】上記構成に加え本発明は、化合物半導体層
がGaAs又はAlX Ga1-X Asである。In addition to the above structure, in the present invention, the compound semiconductor layer is GaAs or Al X Ga 1-X As.
【0015】[0015]
【作用】上記構成によれば、p+ 型化合物半導体層とn
+ 型化合物半導体層との間にi層を形成したので、熱を
加えた場合でもドーパントの拡散が抑止される。p+ 型
化合物半導体層とi層との間にp型ドーパントをδドー
プし、i層とn+ 型化合物半導体層との間にn型ドーパ
ントをδドープすることにより、さらに高いキャリア濃
度層を形成することができ、ピーク電流密度が大幅に向
上する。According to the above construction, the p + type compound semiconductor layer and the n +
Since the i layer is formed between the + type compound semiconductor layer and the + type compound semiconductor layer, diffusion of the dopant is suppressed even when heat is applied. By p-doping a p-type dopant between the p + -type compound semiconductor layer and the i layer and δ-doping an n-type dopant between the i layer and the n + -type compound semiconductor layer, a higher carrier concentration layer can be obtained. It can be formed and the peak current density is significantly improved.
【0016】化合物半導体層がAlX Ga1-X Asの場
合、p+ 型AlX Ga1-X As層及びn+ 型AlX Ga
1-X As層のキャリアー濃度をそれぞれ1×1018cm
-3以上、5×1017cm-3以上とすることでトンネル効
果が現れ、i層の膜厚を3nmより厚くすることによっ
てドーパントの拡散を小さくすることができ、かつ、3
0nmより薄くすることによって高いピーク電流密度が
得られる。When the compound semiconductor layer is Al x Ga 1 -x As, the p + type Al x Ga 1 -x As layer and the n + type Al x Ga are formed.
The carrier concentration of the 1-X As layer is 1 × 10 18 cm, respectively.
-3 or more and 5 × 10 17 cm -3 or more, the tunnel effect appears, and by increasing the thickness of the i layer to more than 3 nm, the diffusion of the dopant can be reduced, and 3
Higher peak current density can be obtained by making the thickness thinner than 0 nm.
【0017】[0017]
【実施例】以下、本発明の一実施例を添付図面に基づい
て詳述する。An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
【0018】図1は本発明の化合物半導体ウエハを用い
た半導体装置の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of a semiconductor device using the compound semiconductor wafer of the present invention.
【0019】化合物半導体ウエハ9は、p型GaAs基
板11の上にp型GaAs層(以下「p層」という。)
12、p+ 型GaAs層(以下「p+ 層」という。)1
3、i型GaAs層(以下「i層」という。)14、n
+ 型GaAs層(以下「n+ 層」という。)15及びn
型GaAs層(以下「n層」という。)16が順に積層
されたものであり、p+ 層13とi層14との間の界面
にp型ドーパント18がδドープされ、かつ、i層14
とn+ 層15との間の界面にn型ドーパント19がδド
ープされている。そして、p型GaAs基板11の裏面
にはp側電極10が形成され、n層16の表面にはn側
電極17が形成されている。The compound semiconductor wafer 9 has a p-type GaAs layer (hereinafter referred to as "p layer") on a p-type GaAs substrate 11.
12, p + type GaAs layer (hereinafter referred to as “p + layer”) 1
3, i-type GaAs layer (hereinafter referred to as "i layer") 14, n
+ Type GaAs layer (hereinafter referred to as "n + layer") 15 and n
Type GaAs layers (hereinafter referred to as “n layers”) 16 are sequentially stacked, and the interface between the p + layer 13 and the i layer 14 is δ-doped with the p-type dopant 18 and the i layer 14
The n-type dopant 19 is δ-doped at the interface between the n + layer 15 and the n + layer 15. Then, the p-side electrode 10 is formed on the back surface of the p-type GaAs substrate 11, and the n-side electrode 17 is formed on the surface of the n-layer 16.
【0020】次に図1に示した半導体装置の製造方法に
ついて述べる。Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described.
【0021】p型GaAs基板11の上に、p層12と
p+ 層13とを順次成長させ、このp+ 層13の表面に
p++型のδドープを行う。その上にi層14を成長さ
せ、i層14の表面にn++型のδドープを行う。さらに
その上にn+ 層15、n層16を順次成長させる。これ
らのGaAs層11、12、13、14、15、16
は、MOCVD(Metal Organic Chemical Vapor Deposi
tion) 法により成長させる。p層12、p+ 層13、i
層14、n+ 層15及びn層16の厚さは、各々0.5
μm、25nm、5nm、25nm、1μmとする。G
aAs層の成長温度は、p+ 層が500℃でありその他
の層10、17、18、19は約650℃である。[0021] On the p-type GaAs substrate 11, p layer 12 and the p + layer 13 and successively grown, performs δ doped p ++ type on the surface of the p + layer 13. The i layer 14 is grown thereon, and the surface of the i layer 14 is subjected to n + + type δ doping. Further thereon, an n + layer 15 and an n layer 16 are sequentially grown. These GaAs layers 11, 12, 13, 14, 15, 16
Is MOCVD (Metal Organic Chemical Vapor Deposi
growth) method. p layer 12, p + layer 13, i
The thicknesses of the layer 14, the n + layer 15 and the n layer 16 are each 0.5
μm, 25 nm, 5 nm, 25 nm, 1 μm. G
The growth temperature of the aAs layer is 500 ° C. for the p + layer and about 650 ° C. for the other layers 10, 17, 18, and 19.
【0022】また、p層12、p+ 層13、i層14、
n+ 層15及びn層16のキャリアー濃度はそれぞ1×
1018cm-3、5×1019cm-3、8×1018cm-3、
1×1018cm-3とする。Further, the p layer 12, the p + layer 13, the i layer 14,
The carrier concentration of each of the n + layer 15 and the n layer 16 is 1 ×
10 18 cm -3 , 5 × 10 19 cm -3 , 8 × 10 18 cm -3 ,
It is set to 1 × 10 18 cm −3 .
【0023】ドーパント層18、19はp層にZn、p
+ 層にC、n+ 層及びn層にSiを使用する。またp++
型のδドープにはCを、n++型のδドープにはSiを使
用する。Cのδドープはp+ 層13成長後、温度500
℃の下、AsH3 (水素化砒素)の流量を小さくし、V
/III 比を約1.6から約0.8に下げることによって
行う。The dopant layers 18 and 19 are made of Zn, p
+ Using the Si C, the n + layer and n layer to layer. See p ++
C is used for the type δ-doping, and Si is used for the n ++ type δ-doping. Δ-doping of C is performed at a temperature of 500 after the growth of the p + layer 13.
The temperature of AsH 3 (arsenic hydride) is reduced at
By reducing the / III ratio from about 1.6 to about 0.8.
【0024】一方、Siのδドープはi層14成長後、
温度約650℃の下、AsH3 を4.5×10-4mol
/min、Si2 H6 (ジシラン)を2.5×10-7m
ol/minの流量で10分間流すことによって行う。On the other hand, the δ-doping of Si is performed after the i layer 14 is grown.
At a temperature of about 650 ° C., AsH 3 was added at 4.5 × 10 −4 mol.
/ Min, Si 2 H 6 (disilane) 2.5 × 10 -7 m
It is performed by flowing for 10 minutes at a flow rate of ol / min.
【0025】ところで、p型GaAs基板11のサイズ
は約25mm×25mmで、厚さは約350μmであ
る。そしてp側電極10の材料にはAuZnを、n側電
極17の材料にはAuGeを使用した。p側電極10及
びn側電極17は、トンネル接合の接合面積が約0.8
mm×0.8mmとなるように形成した。By the way, the size of the p-type GaAs substrate 11 is about 25 mm × 25 mm, and the thickness is about 350 μm. AuZn was used as the material of the p-side electrode 10 and AuGe was used as the material of the n-side electrode 17. The p-side electrode 10 and the n-side electrode 17 have a tunnel junction junction area of about 0.8.
It was formed to have a size of mm × 0.8 mm.
【0026】次に実施例の作用を述べる。Next, the operation of the embodiment will be described.
【0027】p+ 層13とn+ 層15との間にi層14
を形成したので、各半導体層15、16の成長過程や電
極10、17の配線接続等で熱を加えた場合でもドーパ
ントの拡散が抑止される。またp+ 層13とi層14と
の間にp型ドーパント18をδドープし、i層14とn
+ 層15との間にn型ドーパント19をδドープするこ
とにより、さらに高いキャリアー濃度層を形成すること
ができ、ピーク電流密度が大幅に向上する。An i layer 14 is provided between the p + layer 13 and the n + layer 15.
Therefore, the diffusion of the dopant is suppressed even when heat is applied during the growth process of the semiconductor layers 15 and 16 and the wiring connection of the electrodes 10 and 17. Further, a p-type dopant 18 is δ-doped between the p + layer 13 and the i layer 14, and the i layer 14 and the n layer 14 are n-doped.
By δ-doping the n-type dopant 19 with the + layer 15, a higher carrier concentration layer can be formed, and the peak current density is significantly improved.
【0028】図2に、図1に示した半導体装置を、上述
した条件で作製したトンネル接合のI−V特性の測定結
果と、トンネル接合を約700℃で2時間熱処理を行っ
たときのI−V特性の結果を示す。同図において横軸は
電圧(V)を示し、縦軸は電流密度(A/cm2 )を示
している。FIG. 2 shows the measurement results of the IV characteristics of the tunnel junction manufactured under the above-mentioned conditions for the semiconductor device shown in FIG. 1 and I when the tunnel junction was heat-treated at about 700 ° C. for 2 hours. The result of -V characteristic is shown. In the figure, the horizontal axis represents voltage (V) and the vertical axis represents current density (A / cm 2 ).
【0029】同図より成長過程における温度650℃×
20分に対してもピーク電流密度として630A/cm
2 もの大きな値が得られた(実線L1 )。また、700
℃×2時間の熱処理後でもピーク電流密度は約37%低
下しただけであり、図6、7の従来例と比較しても数十
万倍もの非常に大きなピーク電流密度が得られた(破線
L2 )。From the figure, the temperature in the growth process is 650 ° C. ×
Peak current density of 630 A / cm for 20 minutes
A value as large as 2 was obtained (solid line L 1 ). Also, 700
Even after the heat treatment at ℃ × 2 hours, the peak current density was only reduced by about 37%, and a very large peak current density of hundreds of thousands of times was obtained compared with the conventional example of FIGS. L 2 ).
【0030】ここで本実施例の化合物半導体ウエハ及び
半導体装置の最適条件について説明する。Optimum conditions for the compound semiconductor wafer and semiconductor device of this embodiment will be described below.
【0031】図3に、図1に示した半導体装置のp+ 層
のキャリアー濃度を変化させたときのピーク電流密度の
測定結果を示す。横軸はキャリアー濃度p(cm-3)を
示し、縦軸はピーク電流密度(A/cm2 )を示す。FIG. 3 shows the measurement results of the peak current density when the carrier concentration of the p + layer of the semiconductor device shown in FIG. 1 was changed. The horizontal axis represents the carrier concentration p (cm −3 ) and the vertical axis represents the peak current density (A / cm 2 ).
【0032】p+ 層のキャリアー濃度を1×1017cm
-3から1×1021cm-3の範囲内で変化させると、1×
1018cm-3以上のキャリアー濃度のとき、ピーク電流
密度が得られた。但し、n+ 層のキャリアー濃度は8×
1018cm-3とした。The carrier concentration of the p + layer is 1 × 10 17 cm
-3 to 1 × 10 21 cm -3 in the range of 1 ×
The peak current density was obtained when the carrier concentration was 10 18 cm −3 or more. However, the carrier concentration of the n + layer is 8 ×
It was set to 10 18 cm -3 .
【0033】同様に図4にn+ 層のキャリアー濃度を変
化させたときのピーク電流密度の測定結果を示す。横軸
はキャリアー濃度n(cm-3)を示し、縦軸はピーク電
流密度(A/cm2 )を示す。Similarly, FIG. 4 shows the measurement results of the peak current density when the carrier concentration of the n + layer was changed. The horizontal axis represents the carrier concentration n (cm −3 ) and the vertical axis represents the peak current density (A / cm 2 ).
【0034】n+ 層のキャリアー濃度を1×1017cm
-3から8×1018cm-3の範囲内で変化させると、5×
1017cm-3以上のキャリアー濃度のとき、ピーク電流
密度が得られた。但し、p+ 層のキャリアー濃度は5×
1019cm-3とした。The carrier concentration of the n + layer is 1 × 10 17 cm
-3 to 8 × 10 18 cm -3 , 5 ×
The peak current density was obtained when the carrier concentration was 10 17 cm -3 or more. However, the carrier concentration of the p + layer is 5 ×
It was set to 10 19 cm -3 .
【0035】また、図5にi層の膜厚を2〜100nm
の範囲内で変化させたときのI−V特性におけるピーク
電流密度を示す。横軸はi層の膜厚(nm)を示し、縦
軸はピーク電流密度(A/cm2 )を示す。Further, in FIG. 5, the film thickness of the i layer is 2 to 100 nm.
The peak current density in IV characteristic when changing in the range of is shown. The horizontal axis represents the film thickness (nm) of the i layer, and the vertical axis represents the peak current density (A / cm 2 ).
【0036】i層の膜厚が3〜30nmの範囲内で10
0A/cm2 以上の高いピーク電流密度を得ることがで
きた。但し、p+ 層及びn+ 層のキャリアー濃度はそれ
ぞれ5×1019cm-3、8×1018cm-3である。The thickness of the i-layer is 10 within the range of 3 to 30 nm.
A high peak current density of 0 A / cm 2 or more could be obtained. However, the carrier concentrations of the p + layer and the n + layer are 5 × 10 19 cm −3 and 8 × 10 18 cm −3 , respectively.
【0037】ところで太陽電池の上にさらに太陽電池を
成長させる場合、太陽電池と太陽電池を接続する際に、
電気抵抗を小さくするための方法として、トンネル接合
の使用が考えられる。しかし、トンネル接合の上にさら
に太陽電池を成長させるために、その成長温度によって
トンネル特性が現れにくくなっていた。しかし本実施例
の化合物半導体ウエハ又は半導体装置を用いることによ
り、ピーク電流密度を高くすることができ、熱に対して
もトンネル特性の劣化を抑えることができたことによっ
て、太陽電池同士の接続において電気抵抗を小さくする
ことが可能になった。従って太陽電池を直列に接続する
ことによって出力電圧の高い太陽電池を作製することが
できる。By the way, when a solar cell is further grown on the solar cell, when connecting the solar cell and the solar cell,
The use of tunnel junctions can be considered as a method for reducing the electric resistance. However, in order to further grow the solar cell on the tunnel junction, the growth temperature makes it difficult for the tunnel characteristics to appear. However, by using the compound semiconductor wafer or the semiconductor device of this example, it was possible to increase the peak current density and suppress the deterioration of the tunnel characteristics even with respect to heat. It has become possible to reduce the electrical resistance. Therefore, a solar cell with a high output voltage can be manufactured by connecting the solar cells in series.
【0038】以上において本実施例によれば、p+ 層と
n+ 層との間にi層を形成したので、I−V特性におけ
るピーク電流密度が高くなると共に、熱が加わったとし
てもp+ n+ 界面のキャリアー濃度の拡散が起こりにく
くなるため急峻性が保たれやすくなり、またp+ 層とi
層、i層とn+ 層との間にそれぞれのドーパントをδド
ープすることによって高キャリアー濃度層が得られ、I
−V特性におけるピーク電流密度を高くすることが可能
である。As described above, according to the present embodiment, since the i layer is formed between the p + layer and the n + layer, the peak current density in the IV characteristic is increased, and even if heat is applied, p Since the diffusion of carrier concentration at the + n + interface is less likely to occur, steepness is easily maintained, and the p + layer and i
Layer, the high carrier concentration layer is obtained by δ-doping each of the dopants between the i layer and the n + layer.
It is possible to increase the peak current density in the −V characteristic.
【0039】尚、本実施例ではp型化合物半導体基板上
に、順番にp+ 型、i型、n+ 型化合物半導体を成長さ
せた場合で説明したが、順番にn+ 型、i型、p+ 型化
合物半導体を成長させてもよい。また、本実施例では化
合物半導体としてGaAsを用いたが、これに限定され
るものではなくInX Ga1-X AsY P1-Y を用いても
よい。[0039] Incidentally, the p-type compound semiconductor substrate in this embodiment, the order to the p + -type, i-type, have been described in the case where the grown n + -type compound semiconductor, sequentially n + -type, i-type, A p + type compound semiconductor may be grown. Although GaAs is used as the compound semiconductor in the present embodiment, the compound semiconductor is not limited to this, and In x Ga 1-x As y P 1-y may be used.
【0040】[0040]
【発明の効果】以上要するに本発明によれば、次のよう
な優れた効果を発揮する。In summary, according to the present invention, the following excellent effects are exhibited.
【0041】(1) p+ 型化合物半導体層とn+ 型化合物
半導体層との間にi層を形成したので、熱を加えた場合
でもドーパントの拡散が抑止され、I−V特性における
ピーク電流密度を高くでき、熱を加えてもピーク電流密
度が低下しない。(1) Since the i layer is formed between the p + type compound semiconductor layer and the n + type compound semiconductor layer, the diffusion of the dopant is suppressed even when heat is applied, and the peak current in the IV characteristic is increased. The density can be increased and the peak current density does not decrease even if heat is applied.
【0042】(2) p+ 型化合物半導体層とi層との間に
p型ドーパントをδドープし、i層とn+ 型化合物半導
体層との間にn型ドーパントをδドープすることによ
り、さらに高いキャリア濃度層を形成することができ、
ピーク電流密度が大幅に向上する。(2) By δ-doping a p-type dopant between the p + -type compound semiconductor layer and the i layer, and δ-doping an n-type dopant between the i layer and the n + -type compound semiconductor layer, It is possible to form a higher carrier concentration layer,
The peak current density is greatly improved.
【図1】本発明の化合物半導体ウエハを用いた半導体装
置の一実施例の断面図である。FIG. 1 is a cross-sectional view of an example of a semiconductor device using a compound semiconductor wafer of the present invention.
【図2】図1に示した半導体装置のI−V特性の結果を
示す図である。FIG. 2 is a diagram showing a result of IV characteristics of the semiconductor device shown in FIG.
【図3】図1に示した半導体装置のp+ 層のキャリアー
濃度を変化させたときのピーク電流密度の測定結果を示
す図である。3 is a diagram showing a measurement result of a peak current density when the carrier concentration of the p + layer of the semiconductor device shown in FIG. 1 is changed.
【図4】図1に示した半導体装置のn+ 層のキャリアー
濃度を変化させたときのピーク電流密度の測定結果を示
す図である。FIG. 4 is a diagram showing measurement results of peak current densities when the carrier concentration of the n + layer of the semiconductor device shown in FIG. 1 was changed.
【図5】図1に示した半導体装置のi層の膜厚を2〜1
00nmの範囲内で変化させたときのI−V特性におけ
るピーク電流密度を示す図である。5 is a diagram showing the thickness of the i layer of the semiconductor device shown in FIG.
It is a figure which shows the peak current density in an IV characteristic when changing in the range of 00 nm.
【図6】従来の半導体装置の断面図である。FIG. 6 is a cross-sectional view of a conventional semiconductor device.
【図7】従来のp+ n+ 接合構造で作製したトンネル接
合でのI−V特性の測定結果を示す図である。FIG. 7 is a diagram showing measurement results of IV characteristics in a tunnel junction manufactured with a conventional p + n + junction structure.
10 p側電極 11 p型GaAs基板 12 p型GaAs層(p層) 13 p+ 型化合物半導体層(p+ 層) 14 i層(i型GaAs層) 15 n+ 型化合物半導体層(n+ 層) 16 n型GaAs層(n層) 17 n側電極10 p-side electrode 11 p-type GaAs substrate 12 p-type GaAs layer (p layer) 13 p + type compound semiconductor layer (p + layer) 14 i layer (i-type GaAs layer) 15 n + type compound semiconductor layer (n + layer) ) 16 n-type GaAs layer (n layer) 17 n-side electrode
Claims (7)
体層とキャリアー濃度の高いn+ 型化合物半導体層とを
接合してトンネル接合を形成した化合物半導体ウエハに
おいて、上記p+ 型化合物半導体層と上記n+ 型化合物
半導体層との間にi層を形成したことを特徴とする化合
物半導体ウエハ。1. A compound semiconductor wafer by joining a high p + -type compound having carrier concentration semiconductor layer and the high carrier concentration n + -type compound semiconductor layer to form a tunnel junction, the p + -type compound semiconductor layer and the A compound semiconductor wafer, wherein an i layer is formed between the n + type compound semiconductor layer and the n + type compound semiconductor layer.
の間の界面にp型ドーパントをδドープし、かつ、上記
i層と上記n+ 型化合物半導体層との間の界面にn型ド
ーパントをδドープした請求項1記載の化合物半導体ウ
エハ。2. The interface between the p + -type compound semiconductor layer and the i layer is δ-doped with a p-type dopant, and the interface between the i layer and the n + -type compound semiconductor layer is n-doped. The compound semiconductor wafer according to claim 1, which is δ-doped with a type dopant.
X Ga1-X Asである請求項1又は2記載の化合物半導
体ウエハ。3. The compound semiconductor layer is GaAs or Al.
The compound semiconductor wafer according to claim 1, which is X Ga 1-X As.
濃度の範囲が1×1018cm-3〜1×1021cm-3であ
り、上記n+ 型化合物半導体層のキャリアー濃度の範囲
が5×1017cm-3〜8×1018cm-3であり、上記i
層の膜厚が3nm〜30nmである請求項3記載の化合
物半導体ウエハ。4. The carrier concentration range of the p + type compound semiconductor layer is 1 × 10 18 cm −3 to 1 × 10 21 cm −3 , and the carrier concentration range of the n + type compound semiconductor layer is 5 × 5. × 10 17 cm −3 to 8 × 10 18 cm −3 , and the above i
The compound semiconductor wafer according to claim 3, wherein the film thickness of the layer is 3 nm to 30 nm.
体層とキャリアー濃度の高いn+ 型化合物半導体層とを
接合してトンネル接合を形成し両化合物半導体層に電極
を設けた半導体装置において、上記p+ 型化合物半導体
層とn+ 型化合物半導体層との間にi層を形成したこと
を特徴とする半導体装置。5. A semiconductor device in which a p + type compound semiconductor layer having a high carrier concentration and an n + type compound semiconductor layer having a high carrier concentration are joined to form a tunnel junction and electrodes are provided on both compound semiconductor layers, A semiconductor device comprising an i layer formed between a p + type compound semiconductor layer and an n + type compound semiconductor layer.
の間の界面にp型ドーパントをδドープし、かつ、上記
i層と上記n+ 型化合物半導体層との間の界面にn型ド
ーパントをδドープした請求項5記載の半導体装置。6. The interface between the p + -type compound semiconductor layer and the i layer is δ-doped with a p-type dopant, and the interface between the i layer and the n + -type compound semiconductor layer is n-doped. The semiconductor device according to claim 5, wherein the type dopant is δ-doped.
X Ga1-X Asである請求項6記載の半導体装置。7. The compound semiconductor layer is GaAs or Al.
The semiconductor device according to claim 6, which is X Ga 1-X As.
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JP25056194A JP3312506B2 (en) | 1994-10-17 | 1994-10-17 | Compound semiconductor wafer and semiconductor device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100384597B1 (en) * | 2000-11-20 | 2003-05-22 | 주식회사 옵토웰 | Method of fabricating Tunnel junction layer |
JP2011523208A (en) * | 2008-05-27 | 2011-08-04 | ユニヴァーシティー オブ ノートル ダム デュ ラック | Method and apparatus for millimeter wave detector with Sb compound based backward diode |
JP2013183159A (en) * | 2012-02-29 | 2013-09-12 | Boeing Co:The | Solar cell with delta doping layer |
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JPS6437060A (en) * | 1987-08-03 | 1989-02-07 | Nippon Telegraph & Telephone | Semiconductor element |
JPH01192112A (en) * | 1988-01-27 | 1989-08-02 | Mitsubishi Electric Corp | Manufacture of negative resistance semiconductor element |
JPH02246284A (en) * | 1989-03-20 | 1990-10-02 | Fujitsu Ltd | Pin photodiode |
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JPS6260271A (en) * | 1985-09-10 | 1987-03-16 | Sanyo Electric Co Ltd | Photovoltaic device |
JPS6437060A (en) * | 1987-08-03 | 1989-02-07 | Nippon Telegraph & Telephone | Semiconductor element |
JPH01192112A (en) * | 1988-01-27 | 1989-08-02 | Mitsubishi Electric Corp | Manufacture of negative resistance semiconductor element |
JPH02246284A (en) * | 1989-03-20 | 1990-10-02 | Fujitsu Ltd | Pin photodiode |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100384597B1 (en) * | 2000-11-20 | 2003-05-22 | 주식회사 옵토웰 | Method of fabricating Tunnel junction layer |
JP2011523208A (en) * | 2008-05-27 | 2011-08-04 | ユニヴァーシティー オブ ノートル ダム デュ ラック | Method and apparatus for millimeter wave detector with Sb compound based backward diode |
JP2013183159A (en) * | 2012-02-29 | 2013-09-12 | Boeing Co:The | Solar cell with delta doping layer |
JP2018107453A (en) * | 2012-02-29 | 2018-07-05 | ザ・ボーイング・カンパニーThe Boeing Company | Solar cell with delta doping layer |
US10944022B2 (en) | 2012-02-29 | 2021-03-09 | The Boeing Company | Solar cell with delta doping layer |
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