JPH08111697A - Multilevel shaped-waveform formation circuit - Google Patents

Abstract

PURPOSE: To miniaturize, economize and stabilize the circuit by separating a modulated wave before band limit into binary rectangular wave systems each with two unknowns, and component waveform outputs are added and synthesized, to which the prescribed band limit is performed, corresponding to the respective systems. CONSTITUTION: Symbol data IH, IL, QH and QL of four bits of 16QAM inputted to four shift registers of a shift register part 1 are parallelly applied to an address switching circuit 2 and outputted while being successively switched in time division manner. That output of (k) bits is applied to a component waveform forming ROM 4 as an address. Then, the stored band limited waveform is read out according to a scan address from a sample counter 3 and data held in a register 5 and the data of IL (QL) from the ROM 4 are added by an adder 6. Next, the data of an I phase are held in a register 7 and the data of a Q phase are held in a register 8. The output of this register 8 is shifted for one bit and fed back to the input of the adder 6, and an octenary rectangular wave is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulation circuit used in a transmitter of a digital communication system, and particularly to 16QAM (Quadrature Amplitude Modulation).
Used for digital modulation circuits such as 64QAM, 256QAM, 64QAM, etc., and 4 levels, 8 levels, 16 levels, etc., which have a constant pitch between adjacent levels, 4 × 2 ⁿ (n = 0,
1, 2 ...) The symbol data of the multi-valued square wave sequence is input, and the multi-level level shaped waveform generation circuit for generating a shaped waveform with band limitation applied to the square wave sequence is improved.

[0002]

2. Description of the Related Art FIG. 1 is an array diagram of modulation symbols of 16QAM which is one of digital modulation methods. In the figure, the horizontal axis and the vertical axis respectively represent the in-phase component I and the quadrature component Q of the two quadrature modulation waveforms, and as shown in the figure,
The modulation symbols are the intersections (16 points marked with a circle) of vertical and horizontal straight lines showing the four values of ± 3a and ± a on each axis. In the case of FIG. 1, the level difference between adjacent modulation symbols on each axis is constant at 2a. FIG. 2 is an explanatory diagram showing a four-valued square wave sequence before band limitation. As shown in FIG. 2, the time-dependent change in the data level of the I-phase or the Q-phase before band limitation is four values (± 3a, ± a) having a change period of one symbol time length T.
It becomes the square wave series.

As a method of generating a four-valued level-shaped waveform in which the above-mentioned four-valued square wave sequence is band-limited, a conventional four-valued square wave signal shown in FIG. 2 is generated, and band-limiting low-pass filtering is performed. Waveform output of the kth symbol of the band limitation for all combinations of the above four-valued square wave sequences of intersymbol interference symbol length (put as k symbols) due to band limitation Is calculated in advance and stored in a ROM, and this is read out to perform D / A conversion by digital processing.

[0004]

However, in the method using analog processing, since the low-pass filter for band limiting is of high order, the circuit scale becomes large, and when analog elements are used, environmental changes and There is a problem in miniaturization, economicization, and stabilization, such as not being suitable for use in ICs, in addition to requiring compensation and fine adjustment for aging. Further, the method by digital processing is excellent in miniaturization, economy, and stability, but if the number of D / A conversion samples per symbol is S, the capacity of the ROM used (words for D / A conversion) The number is S × 4 ^k words. In this way, as the inter-symbol interference symbol length k due to band limitation increases, the capacity becomes huge, which makes it difficult to realize.

The object of the present invention is to provide 16QAM and 64QAM.
Bandwidth-restricted 4-level, 8-level, 16
Values, etc., which generate a 4 × 2 ⁿ (n = 0,1,2 ...) multi-level level shaping waveform by a digital processing method.
Provided is a multilevel level shaping waveform generation circuit which eliminates the problems of miniaturization, economicization, and stabilization that occur in the analog processing, and eliminates the obstacle of the exponential increase in memory capacity that occurs in the conventional digital processing method. Especially.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a modulated waveform before band limitation is separated into a binary binary square wave series, and a predetermined band limited component waveform output corresponding to each of them is output. Is read from the component waveform generation ROM and added and synthesized to generate a desired 4 × 2 ⁿ value level shaping waveform. That is, symbol data (4 + 2 × n bits) indicating the level of each symbol of 4 × 2 ^n- valued square waves of I and Q2 phases before band limitation is input at each symbol timing and sequentially shifted, and k bits ( (k is an inter-symbol interference symbol length due to band limitation), a shift register unit for outputting parallel data which is a binary sequence, and the k-bit binary sequence parallel data is symbol timing × the number of samples × (4 + 2 × n bits) An address switching circuit for sequentially switching and outputting in a time division manner at a timing of 1, a sample counter for generating a scan address for sampling one symbol period as one cycle, and a binary square wave sequence with band limitation of one symbol period. Store it in advance,
A component waveform generation ROM that outputs the corresponding binary square wave sequence according to the output of the sample counter using the output from the address switching circuit as an address, and the component waveform generation R
A first register for temporarily holding the output from the OM, an output of the component waveform generation ROM, and an adder for adding and synthesizing the output of the first register or another output from a register in the subsequent stage, and the addition Register for temporarily holding the addition result of the I-phase component of the addition result of the adder, and the other output for temporarily holding the addition result of the Q-phase component of the addition result of the adder and adding to the adder And a fourth register that temporarily holds the outputs of the second and third registers and outputs them simultaneously, and outputs of the fourth and fifth registers as analog values. And a first and a second D / A converters for converting the output into a multi-valued level shaped waveform output of the I phase and the Q phase.

[0007]

FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 denotes a shift register unit having a plurality of shift registers, and symbol data (4 + 2 × n bits) indicating the level of each symbol of a 4 × 2 ^n- valued square wave of each of I and Q2 phases before band limitation. ) Is input for each symbol timing and sequentially shifted, and parallel data that is a binary sequence of k bits (k is an inter-symbol interference symbol length due to band limitation) is output. The number of shift registers of the shift register unit 1 corresponds to the type of input symbol data, and when the value is four-valued (16QAM), the number of symbol data is four.
Since there are 4 types, there are 6 types of symbol data when there are 8 values (64QAM), and there are 8 types when there are 16 values (256QAM) because there are 8 types of symbol data. Reference numeral 2 denotes an address switching circuit, which sequentially outputs the k-bit binary series parallel data input from the shift register unit 1 in a time division manner at a timing of symbol timing × number of samples × (4 + 2 × n bits). .

Reference numeral 3 denotes a sample counter, which generates and outputs a scan address for sampling with one symbol period as one cycle from the input of the sampling clock sclk. Reference numeral 4 denotes a component waveform generation R in which a binary square wave sequence with band limitation in one symbol section is stored in advance.
OM. Reference numeral 5 is a register for temporarily holding the output from the component waveform generation ROM 4. 6 is a component waveform generation RO
This is an adder that adds and combines the output of M4 and the output from the register 5 or the register 8 and alternately outputs the addition results of the I phase and the Q phase. Reference numeral 7 is a register for temporarily holding the addition result of the I phase of the adder 6. Reference numeral 8 is a register that temporarily holds the addition result of the Q phase of the adder 6. Reference numerals 9 and 10 denote registers, and I input to the D / A converters 11 and 12.
Make sure that the phase and Q phase data are the same.

Next, the operation of the present invention will be described. First,
Generation of 16QAM (four-valued square wave sequence) will be described. A 16QAM symbol is represented by 4 bits in total, 2 bits for each of I phase and Q phase, and these 4 bits are IH and I
L, QH, QL. The 4-bit symbol data is input to the four shift registers of the shift register unit 1 at each symbol timing, and sequentially shifted at the symbol timing to output k-bit data. k
The bit data is switched and output by the address switching circuit 2 in the order of IH, IL, QH, and QL in a time division manner during one sample clock. The component waveform generation ROM 4 outputs a band-limited binary square wave series (with a level of ± a) corresponding to k-bit data. Register 5 is IH, Q
Component waveform generation ROM 4 corresponding to H k-bit data
Hold the output from. Because IH at the next adder 6
Since IL and QH and QL must be added, IH (QH) is held in register 5 once,
This is to perform addition with the IL (QL) output next.

In order to generate a four-valued square wave sequence (levels ± 3a, ± a), as shown in FIG. 4, IH and QH, which were levels of ± a, are doubled and converted to a level of ± 2a. And ± a
By adding to the IL and QL of the level of ± 3a,
A level of ± a can be generated. Alternatively, by converting IL and IQ at the level of ± a to the level of ± (1/2) a,
By adding to the IH and QH of the level of ± (3 /
2) Levels of a and ± (1/2) a can be generated, and when this is taken as a ratio, it becomes equal to the levels of ± 3a and ± a. That is, by converting the binary square wave sequence into a ratio of 1: 2 (output of the register 5 in FIG. 3) and performing addition and synthesis, ± 3a,
Four values of ± a are generated. Here, in order to convert ± a into ± 2a or ± (1/2) a, the output from the register 5 is shifted by 1 bit to the MSB (most significant bit) side or the LSB (least significant bit) side. It can be easily converted. This can be done by shifting the wiring from the register 5 to the adder 6 by 1 bit. For example, if the output of the register is 01010
(10 in decimal) If the binary number is shifted by 1 bit and connected to the adder 6, the input of the adder is 1010.
It becomes 0 (20 in decimal) and the input value is doubled.

Since the addition result of the adder 6 is alternately output in the order of I phase and Q phase, the addition result of I phase is latched by the register 7, and then the addition result of Q phase is latched by the register 8. . Then, the I-phase and Q-phase data are simultaneously latched in the registers 9 and 10 so that the D / A converter 1
Input to 1 and 12, respectively. Register 5 and register 8
When the register 5 is outputting, the register 8 is not output, and conversely, when the register 8 is outputting, the register 5 cannot be output.
In this way, from the D / A converters 11 and 12, ± 3
A four-value shaped waveform of a and ± a is output.

Next, the generation of 64QAM (octal square wave sequence) will be described. A symbol of 64QAM has 6 bits, that is, 3 bits each for I phase and Q phase (IH, I
M, IL, QH, QM, QL)
The number of shift registers in the shift register unit 1 in FIG. 3 is six. Eight-valued square wave is ± 7a, ± 5a, ± 3a, ± a
Level is required. The k-bit data from the shift register unit 1 is IH, IM, I in the address switching circuit 2.
The signals are output in the order of L, QH, QM, QL and input as a k-bit address. From the component waveform generation ROM 4, the corresponding band-limited binary square wave sequences are output.

Next, as in the case of the above 16QAM generation, the I-phase and the Q-phase are sequentially added by the adder 6. When IH (QH) is latched in the register 5 and IM (QM) is added, the level values of ± 3a and ± a are obtained, and this is latched in the register 8. This result is shifted by 1 bit, fed back to the adder 6 and doubled to obtain ± 6a and ± 2a. The output of the register 8 and the output IL of the ROM 4 which is the level value of ± a
By adding and synthesizing (QL), desired levels (± 7a, ± 5a, ± 3a, ± a) can be generated as shown in FIG. When adding the output of register 8 and IL (QL),
The output of the register 5 is not output by the enable signal. When adding the output of the ROM 4 and the output of the register 5, the register 8 is enabled. If the final addition result is I-phase data, it is latched in the register 7, and if it is Q-phase data, it is latched in the register 8 and then simultaneously latched in the registers 9 and 10, and D /
It is input to the A converters 11 and 12.

Next, 256QAM (16-valued square wave series)
Will be described. The symbol of 256QAM is
Each of the 8 bits, I phase, and Q phase is represented by 4 bits, and the 8 bits are IH, IMH, IML, IL, QH, QM.
H, QML, QL. Therefore, the shift register unit 1
The number of shift registers is 8. Also in this case 16Q
Component waveform generation RO as in the case of AM and 64QAM
The output of M4 is IH, IMH, IML, IL, QH, Q.
It is output in the order of MH, QML and QL. And this is added in order. First, IH is latched in the register 5. Next, the IMH from the ROM 4 and the IH of the register 5 are added. The result is latched in the register 8. Next RO
The IML from M4 and the output of register 8 are added. At this time, the connection from the register 8 to the adder 6 is shifted by 1 bit and connected, and the register 5 is not output. The addition result is latched in the register 8 again. Next, the IL from the ROM 4 and the output of the register 8 are added. Since this result is I-phase data, it is latched in the register 7. The same calculation is performed for the Q phase, and the result is latched in the register 8. And at the same time register 9,
It is latched by 10 and input to D / A converters 11 and 12.

As described above, in the generation of the 4 × 2 ^n- valued square wave sequence, the outputs of the component waveform generation ROM 4 are added once, and then the
It can be generated by repeating addition of the addition result by shifting it by 1 bit and feeding it back.

The memory capacity of the ROM that performs the above operation is
If the number of samples per symbol is S, the input sequence for determining one symbol is a k-bit binary sequence,
It becomes S × 2 ^k . This value is S × 4 in the case of the conventional method.
^It is compressed 1 / k times as much as ^k words, indicating that the memory capacity is significantly reduced.

[0017]

By carrying out the present invention, 4 × 2 ⁿ
Since the generation of the value level shaped waveform can be realized by the generation based on the digital processing of the binary component waveform and the addition synthesis,
The problems of miniaturization, economicization, and stabilization that occur in conventional analog processing are solved, and exponential increase in memory capacity, which is an obstacle in the conventional digital processing method, is avoided, so that it is easy to realize. . Also, by feeding back and adding, it is possible to generate a 4 × 2 ⁿ level shaping waveform without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a symbol point arrangement diagram of 16QAM.

FIG. 2 is an explanatory diagram of a four-valued square wave sequence before band limitation.

FIG. 3 is a diagram showing a configuration example of the present invention.

FIG. 4 is an explanatory diagram of generation of a four-valued square wave sequence according to the present invention.

FIG. 5 is an explanatory diagram of generation of an octal square wave sequence according to the present invention.

[Explanation of symbols]

 1 shift register unit 2 address switching circuit 3 sample counter 4 component waveform generation ROM 5 register 6 adder 7, 8, 9, 10 register 11, 12, D / A converter

Claims (1)

[Claims] 1. Each of four I and Q2 phases before band limitation
× 2 ⁿ values Symbol data (4 + 2 × n bits) indicating the level of each symbol of a square wave is input at each symbol timing and sequentially shifted, and a binary value of k bits (k is an intersymbol interference symbol length due to band limitation). A shift register unit for outputting parallel data as a sequence, and an address switching circuit for sequentially switching and outputting the k-bit binary sequence parallel data at a timing of symbol timing × number of samples × (4 + 2 × n bits) , A sample counter for generating a scan address for sampling one symbol period as one cycle, and a band-limited binary square wave sequence for one symbol period are stored in advance, and an output from the address switching circuit is stored. A component waveform raw which outputs the corresponding binary square wave sequence according to the output of the sample counter as an address. ROM
And a first register for temporarily holding the output from the component waveform generation ROM, the output of the component waveform generation ROM, and the output of the first register or another output from a register at a subsequent stage are added and synthesized. An adder; a second register for temporarily holding the addition result of the I-phase component of the addition result of the adder; a temporary holding of the addition result of the Q-phase component of the addition result of the adder; A third register which is used as the other output to be added to the second register, fourth and fifth registers which temporarily hold the outputs of the second and third registers respectively and simultaneously output, and the fourth and fifth registers And a second D / A converter for converting the respective outputs of the above to analog values to obtain multi-level level shaped waveform outputs of I-phase and Q-phase.