JPH08111377A - Integrated circuit and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a highly accurate small-sized high capacity integrated circuit and a fabrication method thereof. CONSTITUTION: The method for fabricating an integrated circuit comprises a step for making a recess 21 in a compound semiconductor substrate, a step for forming an MIM capacitor 51a on the lower surface of the recess 21, a step for covering the surface with a resist except the MIM capacitor 51a and a predetermined region on the compound semiconductor substrate, and a step for coating the resist and the predetermined region with an electrode material to form the gate electrode 11 of a compound semiconductor transistor 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro-monolithic integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIGS. 7 and 9 (f) show, for example, N. Ayaki,
FIG. 1 is a cross-sectional view showing a conventional integrated circuit (IC) disclosed in et al., Proc. 1988 GaAs IC Symposium, P101 to 104. This integrated circuit is a monolithic microwave integrated circuit (MMIC (Monolithic Microwave IC)). ). And this monolithic microwave integrated circuit is
(Metal-Insulator-Metal) A capacitor and a compound semiconductor transistor are integrated and formed on a compound semiconductor (GaAs) substrate.

In FIGS. 7 and 9F, 1b is a compound semiconductor substrate (GaAs substrate), and 20 is a compound semiconductor substrate 1.
The substrate recesses 10a and 10b formed on the substrate b are made of AuG.
Ohmic electrode made of e / Ni / Au, 11 is Ti /
A gate electrode made of Al / Mo. Also, 23 is T
i / Mo / Ti / Au / Mo is a lower metal, 40 is a dielectric thin film (SiN film), and 14d is an upper metal made of Ti / Au. Furthermore, 14a, 14b, 14c, 1
4e is a wiring metal made of Ti / Au, 120 and 150 are passivation films (SiON films), and 160 is Ti / A.
u is a feed layer metal, 170 is an Au air bridge, 140a, 140b, 141c, 142c, 14
0d and 140e are contact holes.

As described above, the compound semiconductor transistor 50 is formed by forming the gate electrode 11, the ohmic electrode 10a and the ohmic electrode 10b on the compound semiconductor substrate 1b.

The lower metal 23 and the upper metal 14d
And the dielectric thin film 40 form an MIM capacitor 52. Here, the upper metal 14d serves as an upper electrode of the MIM capacitor 52 and also serves as a lead wiring of the MIM capacitor 52. And this MI
The M capacitor 52 is the compound semiconductor transistor 5 described above.
There is a high step with respect to 0.

By the way, the following points are required for the MIM capacitor 52 used in the monolithic microwave integrated circuit. That is, R when used in the microwave band
It is required that the F loss is small, that it has sufficient reliability (lifetime) with respect to RF voltage and that it does not cause dielectric breakdown.

First, in order to satisfy the requirement of
3. The film thickness of the wiring metal 14 is sufficiently thick. For example, when the microwave of the monolithic microwave integrated circuit is 10 GHz, the film thickness of 2500 angstroms or more is used.

In order to satisfy the above requirement, the wiring is drawn from the upper electrode (wiring metal 14) of the MIM capacitor 52 by the above air bridge 170 to concentrate the electric field at the pattern edge of the lower metal 23. To prevent.
Further, the dielectric thin film 40 has an S that is less likely to be electrically deteriorated.
An iN film is used. For example, in order to obtain a withstand voltage of 100 V or more, the SiN film may have a film thickness of 1500 Å or more. By using this SiN film, the MIM capacitor 52 has a capacitance of 400 pf / mm ^{2 under} the above conditions.

Next, a method of manufacturing a conventional monolithic microwave integrated circuit will be described. In the conventional method for manufacturing a monolithic microwave integrated circuit, the compound semiconductor transistor 50 is manufactured first, and then the MIM capacitor 51 is manufactured. Details thereof will be described below with reference to FIG.
This will be described with reference to the sectional views shown in (a) to (f) and FIGS. 9 (a) to (f).

First, as shown in FIG. 8 (a), ohmic electrodes 10a and 10b are formed on the compound semiconductor substrate 1c by vapor deposition lift-off, and then a resist 90 is applied to the compound semiconductor as shown in FIG. 8 (b). It is formed on the substrate 1c. After that, as shown in FIG. 8C, the compound semiconductor substrate 1c is etched to form a substrate recess 20.
As a result, the compound semiconductor substrate 1 having the substrate recess 20 is formed.
b is formed. Further, Ti, Al, and Mo are sequentially deposited on such a compound semiconductor substrate 1b to form a metal film (Ti / Al / Mo) 110 on the resist 90, and the gate electrode 11 is formed on the substrate recess 20. Form on top. As a result, the compound semiconductor transistor 50 is manufactured on the compound semiconductor substrate 1b.

After that, as shown in FIG. 8 (d), the resist 90 is lifted off together with the metal film 110 and removed from the compound semiconductor substrate 1b. As shown in FIG. 8 (e),
A passivation film 121 is deposited on the compound semiconductor substrate 1b from which the resist 90 has been lifted off. After depositing the passivation film 121, a resist 30 is formed on the passivation film 121 as shown in FIG. On such a compound semiconductor substrate 1b, Ti, M
O, Ti, Au, and Mo are sequentially deposited, and a metal film (Ti / Mo / Ti / is formed on the resist 30 as shown in FIG. 9A).
The Au / Mo) 230 is formed and the lower metal 23 is formed on the passivation film 121. Then, as shown in FIG. 9B, the resist 3 is formed together with the metal film 230.
After 0 is lifted off, a dielectric thin film 41 is deposited on the passivation film 121 and the lower metal 23, as shown in FIG. 9 (c). After that, the passivation film 121 and the dielectric thin film 41 are removed from the ohmic electrode 10a, the ohmic electrode 10b, and the gate electrode 11 to remove the contact holes 140a, 140b, and 14a.
1c and 142c are formed. As a result, as shown in FIG. 9D, the passivation film 120 and the dielectric thin film 40 are
And are formed. Furthermore, after forming each contact hole,
Wiring metals 14a, 14b, 14c, on the dielectric thin film 40,
14e and the upper metal 14d are formed, and part of the wiring metals 14a, 14b, 14c are formed in the contact holes 140a, 140b, 141c, 142c. As a result, as shown in FIG. 9 (d), the ohmic electrode 10
a, 10b, the gate electrode 11, and the lower metal 23
Is connected to the wiring metals 14a, 14b, 14c, and the MIM capacitor 52 is manufactured on the compound semiconductor substrate 1b.

Then, as shown in FIG. 9 (e), a part of the surface of the dielectric thin film 40 and the wiring metals 14a, 14b, 14 are formed.
A passivation film 151 is formed on the surface of c and the surface of the upper metal 14d. After forming the passivation film 151, a part of the passivation film 151 on the upper metal 14d and the wiring metal 14e is removed to form contact holes 140d and 140e. As a result, the passivation film 150 provided with the contact holes 140d and 140e is formed. After that, the power supply layer metal 160 connects the upper metal 14d and the wiring metal 14e, and further, the air bridge 170 is provided on the power supply layer metal 160 to form the monolithic microwave integrated circuit shown in FIG. 9 (f). .

[0013]

Since the conventional micro-monolithic integrated circuit and the manufacturing method thereof are configured as described above, the MIM capacitor 52 is further formed in order to form the circuit with higher integration. There are the following problems in achieving high performance.

In the conventional manufacturing method, the lower metal 23 is formed after steps such as a lift-off step and resist removal, and then the dielectric thin film 40 is formed. At this time, many foreign substances, oxides, etc. in the lift-off process, the resist removal process, and the like are sandwiched at the interface between the lower metal 23 and the dielectric thin film 40. In order to prevent the occurrence of dielectric breakdown due to such foreign matters and oxides, in the conventional circuit, the dielectric breakdown voltage of the dielectric thin film 40 must be made sufficiently large, and the dielectric breakdown voltage of the MIM capacitor 52 should be the same. It must be well above the RF voltage. For example, the thickness of the dielectric thin film 40 is set to 1500 angstroms or more, and the RF voltage of the MIM capacitor 52 is set to 10 to 10.
When 20 V is obtained, the dielectric withstand voltage of the dielectric thin film 40 must be 100 V or more, even though the RF voltage is 10 to 20 V. Therefore, there is a problem that the film thickness of the dielectric thin film 40 becomes large and it is difficult to further improve the performance of the MIM capacitor 52.

After the compound semiconductor transistor 50 is formed, the lower metal film 23a and the dielectric thin film 41 are continuously formed as in the method of manufacturing an integrated circuit shown in the sectional views of FIGS. 10 (a) to 10 (c). It is considered that the thickness of the dielectric thin film 40 can be reduced by depositing and removing these unnecessary portions by etching. However, when this method is used, when the lower metal film 23a is removed from the passivation film 121, a part of the lower metal film 23a cannot be completely removed, and a step portion such as the gate electrode 11 of the compound semiconductor transistor 50 is not removed. Will remain. As described above, the unnecessary metal left on the step portion causes not only a short circuit in the wiring but also a stray capacitance. Therefore, this method cannot be used in the microwave circuit. Further, if the passivation film 121 is planarized and then the dielectric thin film 41 is deposited thereon, the lower metal 23 can be removed from the passivation film 121 without leaving the unnecessary metal. However, in this case, the passivation film 121
In the end, not only is the circuit increased in size, but the parasitic capacitance is increased and it cannot be used in the microwave circuit.

In the conventional micro-monolithic integrated circuit and its manufacturing method, the dielectric thin film 40 has BaSrTi whose εr is much larger than that of the SiN film.
There is a problem that substances such as O ₃ , SrTiO ₃ and TaO cannot be used. Because BaSrTi
The film formation of O ₃ requires a temperature of 600 ° C. or higher, and this temperature exceeds the upper temperature limit of the compound semiconductor transistor 50, so that the compound semiconductor transistor 50 is deteriorated when the MIM capacitor 52 is formed. Is.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to prevent foreign matter from being mixed into a passive element or an active element, so that the passive element or the active element has a unit area per unit area. It is an object of the present invention to obtain a method of manufacturing an integrated circuit that can increase the capacity. Another object of the present invention is to obtain an integrated circuit manufacturing method capable of accurately manufacturing a transistor electrode.

Further, according to the present invention, the above passive element or active element can be manufactured at a temperature higher than the heat resistant temperature of a transistor on the same substrate, and an integrated circuit capable of increasing the capacitance per unit area of the passive element or active element can be manufactured. Aim to get a way.

Further, according to the present invention, even if a passive element or an active element is formed on a substrate before a transistor, a high performance of the passive element or the active element and the transistor can be obtained. The purpose is to obtain a manufacturing method.

A further object of the present invention is to obtain an integrated circuit capable of reducing or eliminating the step difference between the passive element or active element and the transistor. Another object of the present invention is to obtain an integrated circuit capable of increasing the capacitance of passive elements or active elements.

[0021]

A method for manufacturing an integrated circuit according to the present invention (claim 1) is a method for manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrated on a substrate. A step of forming the substrate having a high step portion and a low step portion, and a step of forming the passive element or the active element in the low step portion of the substrate,
A step of covering the passive element or the active element and the substrate with a resist, and removing a portion of the resist covering a required area of the high step portion to form the resist with an electrode pattern of the transistor. A step of patterning to have, an electrode material is deposited on the patterned resist and the required region, and then the resist and the electrode member on the resist are removed by lift-off, and And a step of forming the electrode on a required region.

An integrated circuit according to the present invention (claim 2) is
In an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, the substrate has a high step portion and a low step portion, and the passive element or the active element has the low step portion. It is characterized in that the transistor is provided in a portion, and the transistor is provided in the high step portion.

An integrated circuit according to the present invention (claim 3) is
In the integrated circuit (claim 2), the height of the passive element or the active element from the low-step portion is equal to or less than the height of the transistor from the low-step portion. is there.

A method for manufacturing an integrated circuit according to the present invention (claim 4) is a method for manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrally formed on a substrate. The method is characterized by including a step of forming an element on the substrate and a step of forming the transistor on the substrate after forming the passive element or the active element.

The method for manufacturing an integrated circuit according to the present invention (claim 5) is the same as the method for manufacturing the integrated circuit (claim 4), wherein the step of forming the passive element or the active element on the substrate comprises: First on the same area of the substrate surface
To n-th (n is an arbitrary integer of 1 or more) film-like bodies are laminated in this order, and then the parts other than the part of each film-like body formed on a required region on the substrate are removed. Is to form the passive element or active element on the required region, and the step of forming the transistor on the substrate after forming the passive element or active element,
It is characterized in that the transistor is formed in a region on the substrate other than the required region.

The method for manufacturing an integrated circuit according to the present invention (claim 6) is the same as the method for manufacturing the integrated circuit (claim 4), wherein the step of forming the passive element or the active element on the substrate comprises: The passive element or the active element is the first
The step of forming the transistor on the substrate after forming the passive element or the active element on the substrate at the second temperature of the first temperature or less And is formed on the above substrate.

An integrated circuit according to the present invention (claim 7) is
In an integrated circuit in which a passive element or active element and a transistor are integrated and formed on a substrate, the passive element or active element is a capacitor, and the dielectric of the capacitor is higher than the temperature at the time of forming the transistor. BaSrTiO ₃ , SrTiO ₃ , formed on the substrate,
Alternatively, it is made of TaO.

A method of manufacturing an integrated circuit according to the present invention (claim 8) is a method of manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate. Forming the passive element or the active element having the electrode of 1) on the substrate, covering the passive element or the active element and the substrate with a resist, and a required region of the substrate of the resist. Patterning the resist so as to have the electrode pattern of the transistor, and depositing an electrode material on the patterned resist and on the required region, and then lifting off. By removing the resist and the electrode member on the resist from the substrate by forming a transistor electrode on the required region. When, is characterized in that comprises a step of the thin-film over the thickness of the thickness of the metal member electrodes after the lift-off is formed on a thin film-like electrodes of the.

A method for manufacturing an integrated circuit according to the present invention (claim 9) is the same as the method for manufacturing an integrated circuit (claim 8), wherein the passive element or the active element has a thin film electrode on its upper end. The thickness of the metal member is equal to or larger than the thickness of the thin-film electrode, and the RF loss of the capacitor is equal to or smaller than a predetermined value.

An integrated circuit according to the present invention (claim 10)
Is an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, wherein the passive element or the active element has a thin film electrode on the upper end thereof, and the above-mentioned electrode is formed on the electrode. It is characterized in that a metal member having a thickness equal to or larger than the thickness of the electrode is provided.

An integrated circuit according to the present invention (claim 11)
In the integrated circuit (claim 10), the passive element or the active element is a capacitor having a thin-film electrode on its upper end, and the metal member has a thickness equal to or larger than the thin-film electrode. And the thickness of the capacitor is such that the RF loss of the capacitor is not more than a predetermined value.

[0032]

According to the present invention (Claim 1), in a method of manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrally formed on a substrate, a high step portion and a low step portion are formed. The step of forming the substrate, the step of forming the passive element or the active element in a low-level portion of the substrate, the step of covering the passive element or the active element and the substrate with a resist, and the resist A step of removing a portion covering a required area of the high-level portion and patterning the resist so as to have an electrode pattern of the transistor; and on the patterned resist and the required area. A step of depositing an electrode material on the substrate and then removing the resist and the electrode member on the resist by lift-off to form the electrode on the required region. Therefore, the height of the resist from the high step portion is reduced by the amount of the step between the high step portion and the low step portion, and the more accurate the electrode pattern is, the lower the height. It is formed.

In the present invention (claim 2), in the integrated circuit in which the passive element or the active element and the transistor are integrally formed on the substrate, the substrate has a high step portion and a low step portion. However, since the passive element or the active element is provided in the low step portion and the transistor is provided in the high step portion, the passive element or the active element is formed in the low step portion. Then, this and the substrate are covered with a resist, and then, a portion of the resist covering a required area on the high step portion is removed, so that the resist has an electrode pattern of the transistor. By patterning, and further by depositing an electrode member on the resist and on the required region to form an electrode of the transistor in the region, it is possible to form the high-level portion of the resist. The height can be reduced within minute level difference between the high-stage portion and said lower stage portion.

In the present invention (claim 3), in the integrated circuit (claim 2), the height of the passive element or the active element from the low step portion is the transistor from the low step portion. Since the height is less than or equal to the height of the resist, the passive element or the active element is formed in the low step portion, and this and the substrate are covered with a resist, and then the high step portion of the resist. The portion covering the required region above is removed, the resist is patterned to have the electrode pattern of the transistor, and an electrode member is further deposited on the resist and the required region, By forming the electrode of the transistor in the region,
The height of the resist from the high step portion can be determined according to the height of the transistor being formed.

According to the present invention (claim 4), in a method for manufacturing an integrated circuit in which a passive element or active element and a transistor are integrated on a substrate, the passive element or active element is placed on the substrate. Since the step of forming the transistor and the step of forming the transistor on the substrate after forming the passive element or the active element are included, the passive element or the active element can be activated without a constraint for protecting the transistor. An element can be formed.

In the present invention (Claim 5), in the method for manufacturing an integrated circuit (Claim 4), the step of forming the passive element or the active element on the substrate is performed in the same region on the surface of the substrate. First to n-th (n is an arbitrary integer of 1 or more) film-like bodies are laminated in this order, and thereafter, a portion of each film-like body formed on a required region on the substrate. Except that the passive element or the active element is formed on the required region by removing the above, and the step of forming the transistor on the substrate after the passive element or the active element is formed is the required step. Since the transistor is formed in a region on the substrate other than the region of, like the method of manufacturing the integrated circuit of the conventional example,
There is no need to remove the resist over the transistor during formation of the passive or active device.

According to a sixth aspect of the present invention, in the method for manufacturing an integrated circuit according to the fourth aspect, the step of forming the passive element or the active element on the substrate includes the step of forming the passive element or the active element. The step of forming the transistor on the substrate after forming the passive element or the active element on the substrate at a temperature of 1 Since it is formed on the substrate at a temperature, even if the passive element or the active element is formed at the first temperature, the transistor is protected from the influence of this temperature.

According to the present invention (claim 7), in an integrated circuit in which a passive element or active element and a transistor are integrated on a substrate, the passive element or active element is a capacitor, and the dielectric The body is formed of BaSrTiO ₃ , SrTiO ₃ , or T formed on the substrate at a temperature higher than that for forming the transistor.
Since it is made of aO, the capacitance of the capacitor is larger than that when SiN is used for the dielectric.

The present invention (claim 8) is a method for manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, wherein the passive element has a thin film electrode on the upper end thereof. Alternatively, a step of forming an active element on the substrate, a step of covering the passive element or the active element and the substrate with a resist, and a portion of the resist covering a required region of the substrate are removed. Patterning the resist so as to have the electrode pattern of the transistor, and depositing an electrode material on the patterned resist and on the required region, and then lift-off from the substrate to the resist. A step of removing the electrode member on the resist and forming an electrode of the transistor on the required region; Since the step of forming a metal member having a thickness equal to or greater than the thickness of the thin film electrode on the thin film electrode, the height of the resist is lower by the thin amount of the thin film electrode. As a result, the more accurate the electrode pattern is formed.

According to the present invention (Claim 9), in the method for manufacturing the integrated circuit (Claim 8), the passive element or the active element is a capacitor having a thin film electrode on the upper end thereof, and the metal is Since the thickness of the member is equal to or greater than the thickness of the thin film electrode and the thickness of the capacitor is such that the RF loss of the capacitor is equal to or less than a predetermined value, the height of the resist is equal to the thin film electrode. And the RF loss of the capacitor is sufficiently reduced by the metal member.

In the present invention (claim 10), an integrated circuit in which a passive element or active element and a transistor are integrated and formed on a substrate, wherein the passive element or active element has a thin film electrode on its upper end. With
Since a metal member having a thickness equal to or greater than the thickness of the electrode is provided on the electrode, the passive element or the active element is formed, and this and the substrate are covered with a resist, and then the After removing a portion of the resist covering a required area, the resist is patterned to have an electrode pattern of the transistor, and an electrode member is further deposited on the resist and the required area. Then, the resist and the electrode member on the resist are lifted off to form the electrode of the transistor in the region, and then the metal member can be formed on the thin film electrode.

According to the present invention (Claim 11), in the integrated circuit (Claim 10), the passive element or the active element is a capacitor having a thin film electrode on the upper end thereof, and the thickness of the metal member. Is greater than or equal to the thickness of the thin-film electrode, and is a thickness such that the RF loss of the capacitor is equal to or less than a predetermined value. Therefore, the passive element or the active element is formed, and this and the substrate are With a resist, and then removing a portion of the resist covering a required area, patterning the resist so as to have the electrode pattern of the transistor, and further forming an electrode member on the resist and on the resist. After depositing on the required region, the resist and the electrode member on the resist are lifted off to form the electrode of the transistor in the region, and then the upper portion. On thin-film electrode can form the metal member, also, RF loss of the passive elements or active elements, equal to or less than a predetermined value by the wiring.

[0043]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 and 3 (i) show an integrated circuit (IC) of the first embodiment.
2 is a cross-sectional view showing a monolithic microwave integrated circuit (MMIC (Monolithic Micromove I).
C)). In this monolithic microwave integrated circuit, a MIM (Metal-Insulator-Metal) capacitor and a compound semiconductor transistor are connected to a compound semiconductor (GaA).
s) It is formed integrally on a substrate.

1 and 3 (i), 1 is the compound semiconductor substrate (GaAs substrate), 20 and 21 are substrate recesses formed in the compound semiconductor substrate 1, and 10a and 10b are ohmic electrodes (AuGe / Ni). / Au) and 11 are gate electrodes (Ti / Al / Mo). These electrodes and the substrate recess 20 are the same as those described in the above-mentioned conventional example. Since the compound semiconductor substrate 1 has the substrate recess 21, the compound semiconductor substrate 1 has the substrate recess 21.
There are a low step portion formed of the bottom surface of the compound semiconductor substrate and a high step portion formed of a region on the compound semiconductor substrate 1 without the substrate recesses 20 and 21. In this way, the gate electrode 11, the ohmic electrode 10a, and the ohmic electrode 10b are formed in the high-level portion on the compound semiconductor substrate 1 to form the compound semiconductor transistor 50.

Further, 2 is an insulating film (SiO film) provided on the substrate recess 21, 3 is a lower metal (Ti / Pt) provided on the insulating film 2, and 4 is a lower metal 3 provided on the lower metal 3. Dielectric thin film (SiN film), 6 is an upper metal (Ti / Pt) provided on a part of the upper surface of the dielectric thin film 4, and 7 is a part of the upper surface of the dielectric thin film 4 and the upper metal 6. It is a passivation film (SiO film) provided on the side surface and the side surface near the upper metal 6 of the wiring metal 5c described later. In this way, the lower metal 3 and the upper metal 6 and the dielectric thin film 4 constitute the MIM capacitor 51. And
Since the MIM capacitor 51 is provided on the bottom surface of the substrate recess 21, that is, in the low-level portion of the compound semiconductor substrate 1, the height of the passivation film 7 on the upper end of the MIM capacitor 51 is the ohmic electrode. 10a, 10
b and the height of the gate electrode 11 or less. The film thickness of the upper metal 6 is the RF of the MIM capacitor 51.
It is a thickness that can sufficiently reduce loss. The area of the upper surface of the upper metal 6 is smaller than the area of the upper metal of the MIM capacitor used in the conventional monolithic microwave integrated circuit. However, the thickness of the dielectric thin film 4 is smaller than the thickness of the dielectric thin film of the MIM capacitor 52 used in the conventional monolithic microwave integrated circuit.
Since it is configured to be sufficiently thin, the MIM capacitor 51
Is the MIM of the conventional monolithic microwave integrated circuit.
Its capacitance is larger than that of the capacitor 52.

Here, when the engraving depth of the substrate recess 21 is 7,000 Å, the film thickness of each film forming the MIM capacitor 51 is the insulating film 2 S.
The thickness of the iN film is 500 Å, the thickness of the Ti film of the lower metal 3 is 500 Å, the thickness of the Pt film of the lower metal 3 is 2500 Å, and the thickness of the SiN film of the dielectric thin film 4 is 1000 Å. The Ti film of the metal 6 has a film thickness of 500 Å, the Pt film of the upper metal 6 has a film thickness of 2500 Å, and the SiO film of the passivation film 7 has a film thickness of 1000 Å. That is, the height of the MIM capacitor 51 is 8500 angstroms, which is 1500 angstroms, and the MIM capacitor 51 is projected from the surface of the high step portion of the compound semiconductor substrate 1.

12 is a passivation film (Si
The passivation film 12 covers a part of the surface of the compound semiconductor substrate 1, the surface of the compound semiconductor transistor 50, the surface of the MIM capacitor 51, and the surface of the passivation film 7. Further, the film thickness of the passivation film 12 is such that its withstand voltage is larger than the withstand voltage of the dielectric thin film 4, and is larger than the film thickness of the insulating film 2. 55a
Is a contact hole provided in the passivation film 12 and located in a part of the upper surface of the ohmic electrode 10a,
55b is provided in the passivation film 12, a contact hole located in a part of the upper surface of the ohmic electrode 10b, 13b is provided in the passivation film 12,
The contact hole is located on a part of the upper surface of the gate electrode 11. Further, 56b is provided in the passivation films 7 and 12 and the dielectric thin film 4, a contact hole located in a part of the upper surface of the lower metal 3, 55c is provided in the passivation films 7 and 12, and the upper metal 6 is a contact hole provided on the entire upper surface of 6.

One end of 13 is provided in the contact hole 13a, and wiring metal 5a connected to the gate electrode 11 has one end in the contact hole 55a and is connected to the ohmic electrode 10a. The wiring metal 5b is a wiring metal whose one end is provided in the contact hole 55b and is connected to the ohmic electrode 10b, and the other end is provided in the contact hole 56b and which is connected to the lower metal 3. Furthermore, 5
One end of c is provided in the contact hole 55c,
The wiring metal 5d is connected to the upper metal 6 and has the other end connected to the power supply layer metal 16 described later. One end of the wiring metal 5d is connected to the power supply layer metal 16. The wiring metals 5a, 5b, 5c and 5d are formed by providing an Au layer on the Ti layer.

Reference numeral 15 is a passivation film (SiON film) which covers the wiring metals 5a, 5b, 5c and 5d together with the passivation film 12. Reference numeral 56c is a contact hole provided on the passivation film 15 and located on a part of the upper surface of the wiring metal 5c, and 55d is a contact hole provided on the passivation film 15 and located on a part of the upper surface of the wiring metal 5d. is there.

Further, 16 is a wiring metal 5c and a wiring metal 5d.
The above-mentioned power supply layer metal (Ti / Au) connected to
, 17 are air bridges (Au) provided on the metal 16 of the power feeding layer. The power supply layer metal 16 and the air bridge 17 prevent the concentration of the electric field at the pattern edge of the lower metal 3 as in the case of the conventional monolithic microwave integrated circuit.

Next, a method of manufacturing the monolithic microwave integrated circuit of the first embodiment will be described. In the method of manufacturing the monolithic microwave integrated circuit of the first embodiment, MI
The M-capacitor 51 is manufactured first, and then the compound semiconductor transistor 50 is manufactured. The details will be described below with reference to FIGS. 2 (a) to (i) and FIGS. 3 (a) to (i). It demonstrates using each sectional drawing shown.

First, as shown in FIG. 2A, the compound semiconductor substrate is etched to form a compound semiconductor substrate 1a having a substrate recess 21 formed therein. For example, if the depth of the substrate recess 21 is 7,000 Å,
The compound semiconductor substrate is etched for 700 seconds with a 50: 1 mixture of tartaric acid and hydrogen peroxide solution.

Then, as shown in FIG. 2 (b), a SiO film, a Ti film, a Pt film, and a SiN film are successively deposited in this order on the compound semiconductor substrate 1a to form a compound semiconductor substrate. 1, an insulating film (SiO film) 2a, a lower metal film (Ti film, / Pt film) 3a, and a dielectric film (SiN).
Film) 4a is formed.

After the dielectric film 4a is formed, as shown in FIG. 2 (c), except for a region having a low step portion on the dielectric film 4a,
A resist 35 is formed. After formation of the resist 35, FIG.
As shown in (d), a Ti film and a Pt film are deposited in this order on the compound semiconductor substrate 1a provided with the resist 35, and a metal film (Ti film, / Pt film) is formed on the resist 35. 60
And the upper metal (Ti film, / Pt film) 6 is formed on the dielectric film 4a in the above-mentioned certain region. After forming the metal film 60 and the upper metal 6, as shown in FIG. 2 (e),
The resist 35 is lifted off together with the metal film 60, and further, as shown in FIG. 2F, an SiO film is deposited on the upper surface and side surfaces of the upper metal 6 and the upper surface of the insulating film 7a to form the insulating film 7a. To form. After forming the insulating film 7a, as shown in FIG. 2 (g), a resist 36 is formed and the MIM capacitor 51a to be formed in the substrate recess 21 is patterned. After patterning the MIM capacitor 51a, the insulating film 7a and the dielectric film 4 are patterned according to this pattern.
a, the lower metal film 3a, and the insulating film 2a are etched, and then the resist 36 is removed by an O ₂ asher. As a result, as shown in FIG.
Each film other than a predetermined area on the bottom surface of the substrate, that is, the resist 3
Each film except under 6 is removed, and the MIM capacitor 51a is formed in a predetermined region on the substrate recess 21. The etching of the insulating film 7a and the dielectric film 4a is performed by CHF3 + O.
Performed by RIE using ₂ gases. Also, lower metal 3
Is etched by milling Ar ions, and the insulating film 2a is etched in the same manner as the insulating film 7a and the dielectric film 4a.

After forming the MIM capacitor 51a, as shown in FIG.
As shown in (i), a resist 37 is formed, and further,
A is formed on the compound semiconductor substrate 1a and the resist 37.
The uGe film, the Ni film, and the Au film are sequentially deposited in this order.
As a result, the metal film 10 is formed on the resist 37, and ohmic electrodes 10a and 10b are formed in the respective regions on the compound semiconductor substrate 1a not covered with the resist 37. After that, as shown in FIG. 3 (a), the resist 37 is lifted off together with the metal film 10, and then the ohmic electrodes 10a and 10b are sintered at about 400.degree. At this time, the already formed MIM capacitor 51a is made of a material having high heat resistance such as SiN, SiO, Ti, Pt, and the upper metal 6 and the dielectric thin film 4b are covered by the passivation film 7b. Therefore, the MIM capacitor 51a is not deteriorated by sintering.

After sintering at about 400 ° C., FIG.
As shown in (b), a resist 38 is formed on the compound semiconductor substrate 1a by covering the MIM capacitor 51a and the compound semiconductor substrate 1a with a resist, and then forming a resist pattern of a gate on the resist. To do. The height of the resist 38 from the above-mentioned high step portion is slightly higher than the height of the gate electrode 11. For example, the engraving depth of the substrate recess 21 is set to 7,000.
If the height of the MIM capacitor 51a is set to 8500 angstroms and the thickness of the MIM capacitor 51a is set to FIG.
The thickness of the resist 38 from the high step portion of the compound semiconductor substrate 1 is about 0.5 μm. This value is the same as that when the compound semiconductor substrate 1a does not have the MIM capacitor 51a, that is, the MIM capacitor 51a.
Compound semiconductor transistor 5 without being affected by the height of
The thickness of the resist 38 around 0 is determined.
In the case where the depth of the substrate recess 21 and the height of the MIM capacitor 51 are as described above, the distance between the side surface of the resist 36 and the side surface of the substrate recess 21 shown in FIG. 1-2 considering the alignment margin and machining accuracy
It suffices if it is μm.

After forming the resist 38 and before forming the gate electrode 11, the compound semiconductor substrate 1a is subjected to isotropic etching to form a substrate recess 20 shown in FIG. 3 (c). Thereby, the compound semiconductor substrate 1 is formed. After forming the compound semiconductor substrate 1, as shown in FIG. 3C, a Ti film, an Al film, and a Mo film are sequentially formed on the resist 38 and on the compound semiconductor substrate 1 not covered with the resist 38 in this order. Then, a metal film (Ti film /
Al film / Mo film) 11a is formed, and the gate electrode 11 is formed on a required region of the bottom surface of the substrate recess 20. As a result, the compound semiconductor transistor 50 is formed in a high step portion of the compound semiconductor substrate 1.

After forming the gate electrode 11, the resist 38 is lifted off together with the metal film 11a as shown in FIG. 3 (d). After the lift-off, as shown in FIG. 3E, the passivation film 12 is formed on a part of the surface of the compound semiconductor substrate 1, the surface of the compound semiconductor transistor 50, and the MIM.
It adheres to the surface of the capacitor 51.

After formation of the passivation film 12, FIG.
After forming the contact hole 13a shown in (f),
The wiring metal 13 is connected to the gate electrode 11. Wiring metal 1
After the connection of 3, the contact hole 55 shown in FIG.
a, 55b, 56b, 55c are formed. As a result, the MIM capacitor 51 is formed on the bottom surface of the substrate recess 21.

After formation of these contact holes, FIG.
As shown in (g), the wiring metals 5a, 5b, 5c, 5d are patterned to form the wiring metals 5a, 5b, 5c, 5d on the passivation film 12, and one end of the wiring metal 5a is ohmic. The wiring metal 5c is connected to the electrode 10a, one end of the wiring metal 5b is connected to the ohmic electrode 10b, and the other end of the wiring metal 5b is connected to a part of the lower metal 3.
One end of is connected to the upper metal 6. After forming each wiring metal,
As shown in FIG. 3 (h), wiring metal 5a, 5b, 5c, 5
d, the wiring metal 13, and the passivation film 1
The passivation film 15a is deposited on a part of the upper surface of the second layer.
After depositing the passivation film 15a, contact holes 56c and 55d shown in FIGS. 1 and 3 (i) are formed in the passivation film 15a. As a result, the passivation film 15 is formed. After that, the power supply layer metal 16
The air bridge 17 is formed on the power feeding layer metal 16 by connecting to the wiring metal 5c and the wiring metal 5d. As a result, the monolithic microwave integrated circuit of Example 1 is manufactured.

As described above, in the integrated circuit of the first embodiment,
Since the compound semiconductor substrate 1 has the substrate recess 21, the MIM capacitor 51 is provided on the bottom surface of the substrate recess 21, and the compound semiconductor transistor 50 is provided in a high-level portion of the compound semiconductor substrate 1, the compound semiconductor The height of the MIM capacitor 51 from the high step portion of the substrate 1 can be reduced within the step difference between the high step portion and the bottom surface of the substrate recess 21. As a result, when the gate electrode 11 is formed,
Since the height of the resist 38 from the above-mentioned high step portion can be reduced and the height of the resist 38 can be reduced, the resist 38
The shape of the gate pattern formed can be made accurate, which has an effect that the gate electrode 11 having an accurate shape can be formed at an accurate position. When an element that does not use the power feeding layer metal 16 and the air bridge 17 is used instead of the MIM capacitor 51, the projections on the surface of the integrated circuit can be made small, and the integrated circuit can be made thin and compact.

Further, in the integrated circuit of the first embodiment, the height of the MIM capacitor 51 from the bottom surface of the substrate recess 21 is larger than that of the compound semiconductor transistor 50 from the bottom surface of the substrate recess 21.
Since the height of the resist 38 is less than or equal to the height of the MIM capacitor 51, the height of the resist 38 from the high step portion can be determined according to the height of the gate electrode 11 regardless of the height of the MIM capacitor 51.

In the method of manufacturing the integrated circuit of the first embodiment, the lower metal film 3a is formed before the compound semiconductor transistor 50 is formed, and the dielectric film 4a is formed on the lower metal film 3a. Furthermore, since the upper metal 6 is formed subsequent to the dielectric film 4a, the lower metal film of the MIM capacitor is deposited on the compound semiconductor substrate as in the conventional integrated circuit manufacturing method, and then the above compound is formed. It is not necessary to remove the resist from the semiconductor substrate or to perform the lift-off process, which allows foreign matter and oxides in the lift-off process, the resist removal process, and the like to be removed from the lower metal film 3a.
Between the dielectric thin film 4 and the dielectric thin film 4, and as a result, dielectric breakdown due to foreign matter or oxide is suppressed,
The thickness of the dielectric thin film 4 can be reduced, and the MIM capacitor 51
Can increase the capacitance of the MIM capacitor 51.
There is an effect that the area of can be reduced.

Further, in the method of manufacturing the integrated circuit of the first embodiment, the insulating film 2a, the lower metal film 3a, the dielectric film 4a, the upper metal 6, and the insulating film 7a are formed on the compound semiconductor substrate 1a, and then these are formed. Of the film other than the formation region of the MIM capacitor 51 is removed, and the MI in the formation region is removed.
Since the M capacitor 51 is formed and then the compound semiconductor transistor 50 is formed in the region where each of the above films is removed, the lower metal film and the dielectric film are formed as in the method of manufacturing the integrated circuit shown in FIG. Even if the film is continuously formed, the passivation film on the surface of the compound semiconductor transistor 50 is not covered by the portion of the lower metal film to be removed, and as a result, a residue when removing the lower metal film 3a is generated. Since it does not remain on the passivation film 12, stray capacitance does not occur in the MIM capacitor 51 due to the above residue.

Next, a modification of the above embodiment will be described. In the integrated circuit of the above embodiment, the SiN film is used for the dielectric thin film 4 of the MIM capacitor 51. However, instead of the SiN film, the compound semiconductor transistor 50 is formed on the compound semiconductor substrate at a temperature higher than the temperature at which the compound semiconductor transistor 50 is formed. BaSr
The MIM capacitor 51 may be formed using a TiO ₃ film, a SrTiO ₃ film, or a TaO film.

The manufacturing method of such an integrated circuit is the same as the manufacturing method of the above-mentioned embodiment except that the dielectric thin film 4 is formed at about 600 ° C. which is higher than the heat resistant temperature of the compound semiconductor transistor 50.

As described above, in the manufacturing method in which each of the above-mentioned films is used as the dielectric thin film 4, the MI is the same as in the above embodiment.
Since the compound semiconductor transistor 50 is formed after the M capacitor 51 is formed, the compound semiconductor transistor 50 is not affected by the formation of the MIM capacitor 51. As a result, the dielectric thin film 4 is kept above the heat-resistant temperature. Can be formed at the temperature of
There is an effect that an O ₃ film, a SrTiO ₃ film, or a TaO film can be used.

In the integrated circuit of this modification, as described above, the dielectric thin film 4 is formed of BaSrTiO ₃ or SrTiO 3.
Since it is composed of ₃ or TaO, the capacity of the MIM capacitor 51 can be dramatically increased. In addition,
For reference, εr of SiN is about 7.0, while εr of BaSrTiO ₃ is about 100.

As another modification, a thin film resistor or an active element such as a superconducting element may be used instead of the MIM capacitor 51 of the integrated circuit of the above embodiment.
Thus, even when using a thin film resistor or a superconducting element, etc., since it can be manufactured by the same method as the manufacturing method described above, it is possible to increase the capacitance of the thin film resistor and the superconducting element, and to downsize the thin film resistor or the superconducting element effective. Further, there is an effect that the gate electrode 11 having an accurate shape can be formed at an accurate position.

Further, as another modification, the diameter of the contact hole 55c of the integrated circuit of the above-mentioned embodiment is made smaller,
A part of the upper surface of the upper metal 6 may be connected to one end of the wiring metal 5c, and in this case also, the same effect as in the case of the above-described embodiment is obtained.

Example 2. 4 and 6 (f) are cross-sectional views showing the integrated circuit of the second embodiment. This integrated circuit is a monolithic microwave integrated circuit similar to the integrated circuit of the first embodiment, and is a MIM capacitor. A compound semiconductor transistor is integrated and formed on a compound semiconductor substrate.

4 and 6 (f), the same reference numerals as those in the first embodiment and the conventional example are the same as those in the first embodiment. Further, 6A is an upper metal, and this upper metal 6A is obtained by thinning the film thickness of the upper metal 6 of the first embodiment so as not to affect the height of the MIM capacitor 51A. The RF loss of the capacitor 51 cannot be reduced sufficiently. In addition, 7
A is a passivation film (SiO film) provided on a part of the upper surface of the dielectric thin film 4, a part of the side surface and the upper surface of the upper metal 6A, and a side surface of the wiring metal 5e described later near the upper metal 6A. ). 51A is an MIM capacitor having the upper metal 6A as an upper electrode.

Further, 12A is a passivation film (Si
ON film), and the passivation film 12 covers a part of the surface of the compound semiconductor substrate 1b, and the surface of the compound semiconductor transistor 50 and the MIM capacitor 51.
It covers the surface of A. Further, the film thickness of the passivation film 12A is such that its withstand voltage is larger than the withstand voltage of the dielectric thin film 4.

Further, 55e is a contact hole provided in a part of the upper surface of the upper metal 6A, and 5f is provided with one end in the contact hole 55b, is connected to the ohmic electrode 10b, and has the other end in the contact hole. Wiring metal provided in 56b and connected to the lower metal 3. Further, 5e is a wiring metal, one end of which is provided in the contact hole 55e and is connected to the upper metal 6A, and the other end is connected to the power feeding layer metal 16A. The wiring metals 5f and 5e are made of Ti.
The Au layer is provided on the above layer. Further, the film thickness of the wiring metal 5e is a thickness that can sufficiently reduce the RF loss of the MIM capacitor 51A.

Further, 15A is a passivation film 12
A is a passivation film (SiON film) which covers the wiring metals 5a, 5f, 5e and 5d together with A. Furthermore, 16
A is the above-mentioned power supply layer metal (Ti / Au) connected to the wiring metal 5e and the wiring metal 5d, and 17A is an air bridge (Au) provided on the power supply layer metal 16A.
The power supply layer metal 16A and the air bridge 17A are
Similar to the case of the first embodiment, the electric field is prevented from concentrating at the pattern edge of the lower metal 3.

Next, a method for manufacturing the monolithic microwave integrated circuit of the second embodiment will be described. In the method of manufacturing the monolithic microwave integrated circuit of the second embodiment, the MIM capacitor is manufactured first and then the compound semiconductor transistor is manufactured, as in the case of the first embodiment. The details will be described below. 5 (a)-(g) and 6 (a)-(f)
It demonstrates using each sectional drawing shown in and.

First, as shown in FIG. 5A, on the compound semiconductor substrate 1c, a SiO film, a Ti film, a Pt film, and
A SiN film is continuously deposited in this order, and an insulating film (SiO film) 2B, a lower metal film (Ti film, / Pt film) 3B, and a dielectric film (SiN) are formed on the compound semiconductor substrate 1c.
Film) 4b is formed.

After forming the dielectric film 4b, as shown in FIG. 5B, a resist 35A is formed on the dielectric film 4b, and the upper metal 6A is formed in the same manner as the upper metal 6 of the first embodiment. The resist 3 is formed while being formed in a certain area on the dielectric film 4b.
A metal film 60 is formed on 5A. After that, the metal film 60
At the same time, the resist 35A is lifted off, and an insulating film 7B is formed as shown in FIG. 5 (c). After forming the insulating film 7B, a resist 36A is formed as shown in FIG. 5 (d), and the insulating film 7b is formed according to the pattern of the resist 36A.
Etching is performed on the dielectric film 4b, the lower metal film 3B, and the insulating film 2B. As a result, on the compound semiconductor substrate 1B, M
The IM capacitor 51 is formed.

After forming the MIM capacitor 51, FIG.
After removing the resist 36A as shown in FIG.
As shown in (f) and (g) and FIG. 6A, the compound semiconductor transistor 50 is formed together with the compound semiconductor substrate 1b in the same manner as in the first embodiment. That is, the MIM capacitor 51b and the compound semiconductor substrate 1b are covered with a resist, and then a resist pattern of the gate of the resist is formed to form a resist 38A.
After forming the substrate recess 20, the gate electrode 11 is formed.

Then, as shown in FIG. 6B, the passivation film 12C is formed on a part of the surface of the compound semiconductor substrate 1b, the surface of the compound semiconductor transistor 50, and the MI.
It is attached to the surface of the M capacitor 51b.

After formation of the passivation film 12C, FIG.
As shown in (c), the passivation film 12B is formed as the contact hole 13a, and the wiring metal 1 is formed.
3 is formed. After forming the wiring metal 13, as shown in FIG. 6 (d), the contact holes 55a, 55b, 56b, 5 are formed.
5e is formed to form the passivation film 12A and the wiring metals 5a, 5d, 5e, 5f. After that, as shown in FIG. 6 (e), a passivation film 15B is deposited, and further shown in FIG. 4 and FIG. 6 (f).
Contact holes 56c and 55d are formed in the passivation film 15B. As a result, the passivation film 1
5A is formed. After that, the power supply layer metal 16A is connected to the wiring metal 5e and the wiring metal 5d, and the air bridge 17A is further formed on the power supply layer metal 16A. As a result, the monolithic microwave integrated circuit of Example 2 is manufactured.

As described above, the upper metal 6A has such a thinness that it hardly affects the height of the MIM capacitor 51A.
Since the film thickness of the wiring metal 5e is equal to or larger than the film thickness of the upper metal 6A, when the compound semiconductor transistor 50 is formed,
The height of the resist 38A covering the MIM capacitor 51 is
The upper metal 6A can be made thinner by making it thinner, so that the shape of the gate pattern formed on the resist 38A can be made accurate, and as a result, the gate electrode 11 having an accurate shape can be formed at an accurate position. , The wiring metal 5e
Since the thickness is equal to or larger than the film thickness of the upper metal 6A and the RF loss of the MIM capacitor 51A is sufficiently small, the RF loss of the MIM capacitor 51 can be sufficiently reduced in addition to the above effects.

The MIM capacitor 51A of the second embodiment
Then, compared with the MIM capacitor 51 of the first embodiment, only the film thickness of the upper metal is reduced, but naturally, the film thickness of each film other than the upper metal may be reduced. As an example, the thickness of the insulating film 2 is 500 angstroms, the thickness of the lower metal 3 is 2500 angstroms, the thickness of the dielectric thin film 4 is 1000 angstroms, and the thickness of the upper metal 6A is 50 angstroms.
0 angstrom, the thickness of the passivation film 7A is 500 angstrom, the MIM capacitor 51
The thickness of A is 0.5 μm. When using a film-like body having such a film thickness, in order to sufficiently reduce the RF loss of the MIM capacitor 51A, the film thickness of the wiring metal 5e is set to
2500 Angstrom.

Further, in the integrated circuit of the second embodiment, the SiN film is used as the dielectric thin film 4. However, as in the case of the above-mentioned first embodiment, the dielectric thin film 4 is provided with the BaSrTiO ₃ film and the SrT film.
An iO ₃ film or a TaO film may be used, which has the effect of increasing the capacitance of the MIM capacitor 51.

Further, in the integrated circuit of the second embodiment, as in the case of the first embodiment, a thin film resistor or an active element such as a superconducting element is used instead of the MIM capacitor 51A of the integrated circuit of the above embodiment. May be. Thus, even when using a thin film resistor or a superconducting element, etc., since it can be manufactured by the same method as the manufacturing method described above, it is possible to increase the capacitance of the thin film resistor and the superconducting element, and to downsize the thin film resistor or the superconducting element effective. Further, there is an effect that the gate electrode 11 having an accurate shape can be formed at an accurate position.

Also in the integrated circuit of the first embodiment described above, the film thickness of the upper metal 6 is the same as that of the upper metal 6A, and the film thickness of the wiring metal 5c is the same as that of the wiring metal 5e. The size may be the same as the film thickness. The method of manufacturing the integrated circuit in this case is the same as the method described in the first embodiment. Further, such an integrated circuit is the same as that of the first embodiment.
In addition to the effect similar to that of the integrated circuit described above, since the upper metal 6 is thin, there is an effect that the depth of the engraving of the substrate recess 21 can be reduced by the amount of the thinner upper metal 6.

[0087]

According to the method of manufacturing an integrated circuit of the present invention (Claim 1), in a method of manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrally formed on a substrate, A step of forming the substrate having a low-level portion and a low-level portion, a step of forming the passive element or the active element in the low-level portion of the substrate, the passive element or the active element and the substrate. The process of covering with resist,
A step of removing a portion of the resist covering a required area of the high step portion and patterning the resist so as to have an electrode pattern of the transistor; and the patterned resist and the required area. Since the method includes a step of depositing an electrode material on the top and then removing the resist and the electrode member on the resist by lift-off to form the electrode on the required region. The height of the resist from the high stepped portion can be reduced within the length of the step between the high stepped portion and the low stepped portion, and the height becomes low, the electrode of the resist is reduced. The pattern can be formed more accurately, and as a result, the electrode having a more accurate shape can be formed at a more accurate position.

According to the integrated circuit of the present invention (claim 2),
In an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, the substrate has a high step portion and a low step portion, and the passive element or the active element has the low step portion. Since the transistor is provided in the high-level portion, the passive element or the active element is formed in the low-level portion, and this and the substrate are covered with a resist, and then the , Removing a portion of the resist covering a required area on the high step portion,
The resist is patterned by patterning the resist so as to have the electrode pattern of the transistor, and by further depositing an electrode member on the resist and the required region to form an electrode of the transistor in the region. The height from the high stepped portion of the resist can be reduced within the step difference between the high stepped portion and the low stepped portion, and the height of the resist can be reduced, so that the electrode pattern of the resist is reduced. Can be formed more accurately, and as a result, the electrode having a more accurate shape can be formed at a more accurate position. Further, there is an effect that the projection can be made small on the surface of the circuit to make the circuit thin.

According to the integrated circuit of the present invention (claim 3),
In the integrated circuit (claim 2), since the height of the passive element or the active element from the low step portion is equal to or lower than the height of the transistor from the low step portion, the passive element or the active element An element is formed in the low step portion, and this and the substrate are covered with a resist, and then, a portion of the resist covering a required area on the high step portion is removed, The resist is patterned by patterning the resist so as to have the electrode pattern of the transistor, and by further depositing an electrode member on the resist and the required region to form an electrode of the transistor in the region. Of the transistor can be determined according to the height of the transistor, the electrode pattern of the resist can be formed more accurately, and as a result, the electrode having a more accurate shape can be more accurately formed. There is an effect that can be formed in precise positions.

A method for manufacturing an integrated circuit according to the present invention (claim 4).
According to the method, in a method for manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, a step of forming the passive element or the active element on the substrate, the passive element or Since the step of forming the transistor on the substrate after forming the active element is included, the transistor is formed during the formation of the passive element or the active element as in the conventional integrated circuit manufacturing method. There is no need to remove the resist covering the resist, which has the effect of preventing foreign substances or oxides when removing the resist from mixing into the passive element or the active element. Further, there is an effect that the transistor is not affected by heat when forming the passive element or the active element.

Method for manufacturing integrated circuit of the present invention (claim 5)
According to the method of manufacturing an integrated circuit (claim 4), the step of forming the passive element or the active element on the substrate includes the first to n (n) th regions on the same region of the substrate surface. Is an arbitrary integer greater than or equal to 1) are laminated in this order, and then the above-mentioned required regions are removed by removing the portions other than the portions formed on the required regions on the substrate of each of the above-described film substances. The step of forming the passive element or the active element on the substrate, and the step of forming the transistor on the substrate after forming the passive element or the active element is a region on the substrate other than the required region. Since the transistor is formed in, during the formation of the passive element or the active element, as in the method of manufacturing an integrated circuit of the conventional example,
There is no need to remove the resist covering the transistor, and as a result, foreign substances and oxides during resist removal are
There is an effect that the above-mentioned passive elements or active elements can be improved in performance and the area of the above-mentioned passive elements or active elements can be reduced, since they are not mixed between the respective film-shaped bodies. In addition, like the integrated circuit manufacturing method shown in FIG.
Even if the insulating film covering the transistor is not thickened, foreign matter when removing the film body does not remain on the insulating film on the surface of the transistor.

A method for manufacturing an integrated circuit according to the present invention (claim 6).
According to the method of manufacturing an integrated circuit (claim 4), the step of forming the passive element or the active element on the substrate includes the step of forming the passive element or the active element on the substrate at a first temperature. The step of forming the transistor on the substrate after forming the passive element or the active element is the first step of forming the transistor.
Since it is formed on the substrate at a second temperature equal to or lower than the above temperature, the material forming the passive element or the active element may include BaSrTiO ₃ , SrTiO ₃ , or TaO having a temperature equal to or higher than the first temperature. What is formed at a temperature can be used, which has the effect of improving the performance of the passive element or active element and reducing the area of the passive element or active element.

According to the integrated circuit of the present invention (claim 7),
In an integrated circuit in which a passive element or active element and a transistor are integrated and formed on a substrate, the passive element or active element is a capacitor, and the dielectric of the capacitor is higher than the temperature at the time of forming the transistor. BaSrTiO ₃ , SrTiO ₃ , formed on the substrate,
Alternatively, since it is made of TaO, the dielectric substance is SiN.
The capacitance of the capacitor can be increased as compared with the case of using, and thus the area of the capacitor can be reduced.

Method for manufacturing integrated circuit of the present invention (claim 8)
According to the method for manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, the passive element or the active element having a thin film electrode on its upper end is formed on the substrate. A step of forming, a step of covering the passive element or the active element and the substrate with a resist, and a portion of the resist covering a required region of the substrate is removed to remove the resist from the electrode of the transistor. Patterning to have a pattern; depositing an electrode material on the patterned resist and on the required region, and then lifting off from the substrate to the resist and the electrode member on the resist; Removing the electrode of the transistor on the required region, and after the lift-off, the thickness of the thin-film electrode is less than Since the thickness of the metal member is to include a step of forming on the thin film-like electrodes of the the height of the resist can thin partial lower of the thin film-shaped electrode,
Since the height of the resist can be reduced, the electrode pattern of the resist can be formed more accurately, and as a result, the electrode of the transistor having a more accurate shape can be formed at a more accurate position.

Method of manufacturing integrated circuit of the present invention (claim 9)
According to the method of manufacturing the integrated circuit (claim 8), the passive element or the active element is a capacitor having a thin film electrode on an upper end thereof, and the metal member has a thickness of the thin film. Since the thickness is equal to or more than the thickness of the electrode and the RF loss of the capacitor is equal to or less than a predetermined value, the height of the resist can be reduced by the thinness of the thin film electrode, and the resist can be lowered. As a result, the electrode of the transistor can be formed more accurately, and in the formed integrated circuit, the metal member can reduce the RF loss of the formed capacitor to a predetermined value or less.

According to the integrated circuit (Claim 10) of the present invention, in the integrated circuit in which the passive element or active element and the transistor are integrated and formed on the substrate, the passive element or active element is formed on the upper end thereof. Since it has a thin film electrode, and a metal member having a thickness equal to or greater than the thickness of the electrode is provided on the electrode, the passive element or the active element is formed, and this and the substrate are separated from each other. Cover with resist,
After that, a portion of the resist covering a required area is removed, the resist is patterned to have an electrode pattern of the transistor, and an electrode member is formed on the resist and the required area. After putting on,
Lifting off the resist and the electrode member on the resist to form an electrode of the transistor in the region,
After that, by forming the metal member on the thin film electrode, the resist can be made lower by the amount of thinning the thin film electrode, thereby making the electrode pattern of the resist more accurate. Can be formed into a
There is an effect that the electrode having a more accurate shape can be formed at a more accurate position.

According to the integrated circuit (Claim 11) of the present invention, in the integrated circuit (Claim 10), the passive element or the active element is a capacitor having a thin film electrode on the upper end thereof, Since the thickness of the member is equal to or greater than the thickness of the thin film electrode and the thickness of the capacitor is such that the RF loss of the capacitor is equal to or less than a predetermined value, the passive element or the active element is formed and The substrate is covered with a resist, then, a portion of the resist covering a required region is removed, and the resist is patterned so as to have the electrode pattern of the transistor.
After depositing an electrode member on the resist and on the required region, lift off the resist and the electrode member on the resist to form the electrode of the transistor in the region, and then the thin film. By forming the metal member on the electrode in the shape of a thin film, the thickness of the thin film electrode can be reduced, and the resist can be made lower, whereby the electrode pattern of the resist can be formed more accurately,
As a result, there is an effect that the electrode having a more accurate shape can be formed at a more accurate position, and an RF loss of the passive element or the active element can be reduced to a predetermined value or less.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a monolithic microwave integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the monolithic microwave integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the monolithic microwave integrated circuit according to the first embodiment of the present invention, which is subsequent to FIG. 2;

FIG. 4 is a sectional view showing a structure of a monolithic microwave integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of the monolithic microwave integrated circuit according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the monolithic microwave integrated circuit according to the second embodiment of the present invention, which is subsequent to FIG. 5;

FIG. 7 is a sectional view showing a structure of a monolithic microwave integrated circuit in a conventional example.

FIG. 8 is a cross-sectional view showing a manufacturing process of a monolithic microwave integrated circuit in a conventional example.

9 is a cross-sectional view showing the manufacturing process of the conventional monolithic microwave integrated circuit, following FIG. 8;

FIG. 10 is a cross-sectional view showing another example of a conventional manufacturing process.

[Explanation of symbols]

1, 1b Compound semiconductor substrate, 2 Insulating film, 3 Lower metal, 4 Dielectric thin film, 5a, 5b, 5c, 5d, 5e,
5f wiring metal, 6,6A upper metal, 7,7A passivation film, 10a, 10b oscillating electrode, 1
1 gate electrode, 12, 12A passivation film,
13 metal wiring, 15, 15A passivation film, 1
6,16A Power feeding layer metal, 17,17A Air bridge, 50 Compound semiconductor transistor, 51,51A
MIM capacitors, 55a, 55b, 55c, 55d,
55e, 56b, 56c Contact holes.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 21/768 27/04 21/822 29/40 A H01L 27/04 C

Claims (11)

[Claims] 1. A method of manufacturing an integrated circuit in which a passive element or an active element and a transistor are integratedly formed on a substrate, the step of forming the substrate having a high step portion and a low step portion. A step of forming the passive element or the active element on a low step portion of the substrate, a step of covering the passive element or the active element and the substrate with a resist, and the high step portion of the resist Patterning the resist so as to have the electrode pattern of the transistor by removing the portion covering the required region of, and depositing an electrode material on the patterned resist and the required region, After that, the method includes removing the resist and the electrode member on the resist by lift-off to form the electrode on the required region. Method of fabricating an integrated circuit. 2. An integrated circuit in which a passive element or active element and a transistor are integrated and formed on a substrate, wherein the substrate has a high step portion and a low step portion, and the passive element or the active element. Is provided in the low-stage portion, and the transistor is provided in the high-stage portion. 3. The integrated circuit according to claim 2, wherein the height of the passive element or the active element from the low step portion is equal to or lower than the height of the transistor from the low step portion. Characterized integrated circuit. 4. A method of manufacturing an integrated circuit in which a passive element or an active element and a transistor are integrated and formed on a substrate, the step of forming the passive element or the active element on the substrate, and the passive element. Or a step of forming the transistor on the substrate after forming an active element, the method for manufacturing an integrated circuit. 5. The method for manufacturing an integrated circuit according to claim 4, wherein the step of forming the passive element or the active element on the substrate includes the first to n-th layers on the same region of the substrate surface. (n is an arbitrary integer of 1 or more) are laminated in this order, and then the portions other than the portions formed on the required regions on the substrate of the respective film bodies are removed to obtain the above-mentioned required film. The step of forming the passive element or the active element on a region, and the step of forming the transistor on the substrate after forming the passive element or the active element is performed on the substrate other than the required region. A method of manufacturing an integrated circuit, comprising forming the transistor in a region. 6. The method of manufacturing an integrated circuit according to claim 4, wherein the step of forming the passive element or the active element on the substrate includes the step of forming the passive element or the active element on the substrate at a first temperature. In the step of forming the transistor on the substrate after forming the passive element or the active element, the transistor is formed on the substrate at a second temperature equal to or lower than a first temperature. A method of manufacturing an integrated circuit, comprising: 7. An integrated circuit in which a passive element or active element and a transistor are integrated and formed on a substrate, wherein the passive element or active element is a capacitor, and a dielectric of the capacitor is used when the transistor is formed. BaSrTi formed on the substrate at a temperature higher than the temperature
An integrated circuit comprising O ₃ , SrTiO ₃ , or TaO. 8. A method for manufacturing an integrated circuit in which a passive element or active element and a transistor are integrated on a substrate, wherein the passive element or active element having a thin film electrode on the upper end thereof is provided on the substrate. And a step of covering the passive element or the active element and the substrate with a resist, and removing a portion of the resist covering a required region of the substrate to remove the resist from the transistor. Patterning to have an electrode pattern; depositing an electrode material on the patterned resist and on the required area, and then lifting off from the substrate to the resist and the electrode member on the resist And forming the electrode of the transistor on the required region, and after the lift-off, the thin film electrode is formed. Method of manufacturing an integrated circuit, which comprises a step of forming on the above thickness of the metal member of the thin-film electrode. 9. The method for manufacturing an integrated circuit according to claim 8, wherein the passive element or the active element is a capacitor having a thin film electrode on an upper end thereof, and the metal member has a thickness of the thin film shape. A method of manufacturing an integrated circuit, wherein the thickness is equal to or more than the thickness of the electrode and the RF loss of the capacitor is equal to or less than a predetermined value. 10. An integrated circuit in which a passive element or active element and a transistor are integrated and formed on a substrate, wherein the passive element or active element has a thin film electrode on the upper end thereof. An integrated circuit characterized in that a metal member having a thickness equal to or larger than the thickness of the electrode is provided on the integrated circuit. 11. The integrated circuit according to claim 10, wherein the passive element or the active element is a capacitor having a thin film electrode on an upper end thereof, and the metal member has a thickness of the thin film electrode. An integrated circuit having a thickness that is equal to or greater than a predetermined value and has an RF loss of the capacitor that is equal to or less than a predetermined value.