JPH0810853B2 - Information data transmission system - Google Patents

Description

The present invention relates to an information data transmission system for transmitting information data obtained by digitalizing an analog information signal together with synchronous data.

[Conventional technology]

Conventionally, when the additional information, which is the second information data different from the main information data, which is the first information data, is to be transmitted together with the main information data, for example, as shown in FIG. 6, the additional information is included in the data transmission block. A plurality of types of information have been transmitted by providing or expanding a data area for data corresponding to information.

[Problems to be solved by the invention]

However, in the conventional method, by providing a data area for additional information in the transmission block to transmit additional information, the transmission density of the main information is reduced, or the transmission bit rate is increased to require a wideband transmission line. It caused the problem that I said.

The present invention has been made in view of the above problems, and an object thereof is to provide an information data transmission system capable of transmitting a plurality of types of information without increasing the transmission bit rate.

[Means for solving problems]

The information data transmission system of the present invention is a system for transmitting first information data obtained by digitizing an analog information signal together with synchronization data, and generates a plurality of types of synchronization data having different bit patterns. Synchronization data generation means, and synchronization data generation control means for selectively outputting the synchronization data from the synchronization data generation means according to the second information of a type different from the first information data. It is a thing.

[Action]

In the above configuration, the second information is transmitted by selectively generating a plurality of types of synchronization data having different bit patterns according to the second information and transmitting the synchronization data together with the first information data. The second information can be transmitted without providing a special data area.

〔Example〕

 Hereinafter, the present invention will be described with reference to an embodiment of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a transmission unit in an information data transmission system to which the present invention is applied.

A synchronizing signal is added to the first information data by the synchronizing signal adding circuit 1, further modulated by a modulator 2 into a signal suitable for the transmission path (for example, a well-known NRZI modulation rate, etc.), and output as a transmission signal.

A second information signal, which is the second information, is supplied to the synchronization signal adding circuit 1, and the synchronization of the data pattern corresponding to the supplied second information signal among a plurality of preset data patterns is performed. Data is selected and added.

The sync signal adding operation in the sync signal adding circuit 1 will be described in detail with reference to FIGS. 2 and 3.

2 is a schematic block diagram showing an example of the synchronizing signal adding circuit in FIG. 1, and FIG. 3 is an operation timing chart of the synchronizing signal adding circuit shown in FIG.

Further, here, the first information data is, for example, image information data obtained by digitalizing an NTSC system television signal,
The second information signal is a field identification signal indicating whether the image information data is the first field data or the second field data.

In FIG. 2, the first synchronizing signal generating circuit 3 is the first
A circuit for generating a first sync signal having a data pattern corresponding to a field identification signal representing a field and supplying it to the parallel-series conversion circuit 5. The second sync signal generation circuit 4 converts the field identification signal representing the second field into a field identification signal. A circuit that generates a second synchronization signal having a corresponding data pattern and supplies the second synchronization signal to the parallel-serial conversion circuit 6, and each parallel-serial conversion circuit.
5 and 6 are shown in FIG. 3 (c).

A load signal as shown in FIG. 3 (c) is supplied to each of the parallel-serial conversion circuits 5 and 6, and is supplied from each of the synchronization signal generation circuits 3 and 4 when the load signal is at the "L" level. The synchronized signal that has been generated is taken in, converted into serial synchronous data in synchronization with the rising timing of the clock signal as shown in FIG. 3A, and output to the switch 7.

The connection of the switch 7 is controlled in accordance with the field identification signal which is the second information signal. When the field identification signal representing the first field is supplied, the switch 7 is connected to the A side in the figure. When the field identification signal representing the second field is supplied, the switch 7 is connected to the B side in the figure.

When transmitting the first field image information data as the first information data, the switch 7 is connected to the A side in the figure by the field determination signal and is output from the first synchronizing signal generating circuit 3 in parallel-series. The first synchronization data converted into the serial signal by the conversion circuit 5 is the switch 8
Is supplied to.

The switch 8 is connected to the D side in the figure during the period when the sync addition timing signal shown in FIG.
During the period of "L" level, it is connected to the C side in the figure, and the connection of the switch 8 is controlled by the sync addition timing signal so that the first sync data of the switch 8 is at the first field. It is added before the image information data, supplied to the modulator 2 in FIG. 1, and transmitted in the same manner as described above.

Further, when transmitting the second field image information data as the first information data, the switch 7 is connected to the side B in the figure by the field discriminating signal, contrary to the above.
The second synchronization data output from the second synchronization signal generation circuit 4 and converted into a serial signal by the parallel-serial conversion circuit 6 is supplied to the switch 8, and in the same manner as described above, the switch 8 outputs the second synchronization data to the first synchronization data. It is added and transmitted before the 2-field image information data.

As described above, the field identification signal, which is the second information signal, can be transmitted together with the image information data, which is the first information data, without using a special data area or the like.

FIG. 4 is a diagram showing a schematic configuration of the receiving section in the information data transmission system to which the present invention is applied, and FIG. 5 is a schematic configuration diagram showing an example of the synchronization signal detection circuit in FIG. The detection operation of the synchronization signal at the time of receiving the transmission signal will be described below with reference to FIGS. 4 and 5.

In FIG. 4, the input transmission signal is demodulated by the demodulation circuit 9 into the original data form and then supplied to the synchronization detection circuit 10 and the data restoration circuit 11.

The synchronization detection circuit 10 detects the data pattern of each synchronization data from the supplied data string, and when detected, outputs a synchronization detection signal to the timing signal generation circuit 12. Then, in the timing signal generation circuit 12, various timing signals necessary for data restoration in the data restoration circuit 11 to be described later are formed in synchronization with the supplied synchronization detection signal, and are supplied to the data restoration circuit 11.

In the data restoration circuit 11, the data sequence supplied from the demodulator 9 is subjected to processing such as error correction and data interpolation based on various timing signals formed in the pre-tone timing signal generation circuit 12 to restore the first data. Output as information data.

Further, the synchronization detection circuit 10 restores and outputs the second information signal by discriminating a plurality of preset data patterns of the synchronization data.

Now, the operation of restoring the second information signal in the synchronization detection circuit 10 will be described with reference to FIG. The sync detecting circuit shown in FIG. 5 corresponds to the sync signal adding circuit shown in FIG. 2 and is configured to detect the first and second sync data having different data patterns.

In FIG. 5, the output from the demodulator is supplied to the serial-parallel conversion circuit 13 one bit at a time, converted into parallel signals of the number of bits corresponding to the number of bits constituting the synchronous data, and supplied to the comparison circuits 14 and 15. To be done.

Also, the first synchronization signal generation circuit 16 and the second synchronization signal generation circuit 1
In 7, the first sync signal generating circuit 16 generates the first sync signal having the data pattern corresponding to the field identification signal representing the first field, and the second sync signal generating circuit 17 outputs the second field in the same manner as described above. A second sync signal having a data pattern corresponding to the field identification signal representing the first sync signal is supplied to the comparison circuit 14.
The second synchronization signal is supplied to 15.

Then, in each of the comparison circuits 14 and 15, the data pattern of the output signal of the demodulator converted into the parallel signal supplied as described above is compared with the data pattern of each of the first synchronization signal and the second synchronization signal. If they match, the detection signal is output to the OR gate 18, and the output of the OR gate is supplied to the timing signal generation circuit 12 as the synchronization detection signal, and the data restoration operation is performed as described above.

On the other hand, the detection signal of the comparison circuit 14 is supplied to the set terminal S of the set-reset flip-flop (hereinafter referred to as SR-FF) 19, and the detection signal of the comparison circuit 15 is supplied to the reset terminal R of SR-FF19. The SR-FF19 is at the “H” level while the first synchronization image data is followed by the first field image information data, and the second synchronization data is followed by the second field image information data. The field identification signal that is at the “L” level is output during the period in which is supplied.

As described above, the field identification signal which is the second information signal transmitted together with the image information data which is the first information data can be restored.

By the way, in the present embodiment, the first information data is the image information data and the second information signal is the field identification signal, but the present invention is not limited to these and can be applied to other information data and information signals. However, the same effect can be obtained.

Further, in the present embodiment, the field identification signal is transmitted by the synchronous data having two kinds of data patterns, but more kinds of data patterns are prepared and the synchronous signal generating circuit and the comparing circuit corresponding to the kinds are prepared. It is also possible to transmit a plurality of types of second information signals by providing.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide an information data transmission system capable of transmitting a plurality of types of information without increasing the transmission bit rate.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a transmission unit in an information data transmission system to which the present invention is applied. FIG. 2 is a schematic configuration diagram showing an example of the synchronizing signal adding circuit in FIG. FIG. 3 is an operation timing chart of the synchronizing signal adding circuit shown in FIG. FIG. 4 is a diagram showing a schematic configuration of a receiving unit in the information data transmission system to which the present invention is applied. FIG. 5 is a schematic configuration diagram showing an example of the synchronization signal detection circuit in FIG. FIG. 6 is a diagram showing the structure of a data transmission block in a conventional information data transmission system. 3,16 …… First sync signal generation circuit 4,17 …… Second sync signal generation circuit 7,8 …… Switch 14,15 …… Comparison circuit 18 …… OR gate 19 …… Set / reset flip flip

Claims (1)

[Claims] 1. A system for transmitting first information data obtained by digitizing an analog information signal together with synchronization data, and a synchronization data generating means for generating a plurality of types of synchronization data having different bit patterns. And a synchronization data generation control means for selectively outputting the synchronization data from the synchronization data generation means according to the second information of a type different from the first information data. Data transmission system.