JPH08107545A - Video signal converter - Google Patents

Abstract

PURPOSE: To record and reproduce the various standards of digital video signals by using the digital recording and reproducing device of a prescribed format. CONSTITUTION: A data structure is changed so as to house input digital video signals provided at least with luminance signals and chrominance signals whose bit rate is larger and two-dimensional space area is smaller compared with the digital television video signals of the prescribed format within the capacity of the prescribed format. The input digital video signals are written in a memory 204 in synchronism with the input digital video signals by a timing generation part 221, a memory control counter part 222 and an address memory 223 and the data of the memory 204 are read by the memory control counter part 222 and the address memory 224. In this case, the data of upper bits are set in the first area of the format and the data of lower bits are set in the second area of the format.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is capable of storing a plurality of digital video signals having different bit rates and sampling rates in a storage means having a common predetermined format, and can be stored in the original state from the core means. The present invention relates to a video signal conversion device that can be taken out as a digital video signal.

[0002]

2. Description of the Related Art At present, various formats are standardized as formats of digital video signals. For example, the sampling rate ratio of luminance signal Y: color difference signal Cb: color difference signal Cr is 8: 4: 4, and the sampling rate ratio of luminance signal Y: color difference signal Cb: color difference signal Cr: alpha signal is 4: 4 :.
There is a 4: 4 signal. The alpha signal is additional information such as chroma key. The bit rate of these signals is 10 bits.

On the other hand, the format in the high-definition system has been standardized. This format is 1
Field has a bit rate of 8 bits, horizontal sampling rate 1920, vertical sampling rate 5
Seventeen. This format is different from the standards for the various digital video signals described above. The high-definition digital recording / reproducing apparatus is capable of recording / reproducing 1125/60, that is, a high-definition video signal of 1125 scanning lines at a field frequency of 60 Hz, and digital lines 1 to 563 are digital first fields and digital lines. 564 to 1125 are used as the digital second field.

[0004]

Meanwhile, a digital recording / reproducing apparatus has been developed corresponding to the above-mentioned high-definition system (HDTV system). However, this digital recording / reproducing apparatus cannot record / reproduce digital video signals of different standards, and is insufficient in terms of application. Therefore, an object of the present invention is to provide a video signal conversion device capable of recording and reproducing digital video signals of various standards with the above-mentioned digital recording / reproducing device.

[0005]

SUMMARY OF THE INVENTION According to the present invention, an input digital video signal of at least a predetermined format that includes at least a luminance signal and a chrominance signal and has a bit rate and a sampling rate different from that of a digital television video signal of a predetermined format is used. As means for converting the data structure so as to fit within the capacity, a memory for converting the data structure, a writing means for writing the input digital video signal in the memory in synchronization with the input digital video signal, and the input from the memory When reading a digital video signal, the upper bit data of the input digital video signal is read and set in the first area of the format, and the lower bit data is read and set in the second area of the format, and a data structure And a reading means for converting and reading.

[0006]

By the above means, a digital video signal having a high bit rate can be accommodated within the format of a digital video signal having a low bit rate but a large two-dimensional space capacity.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows an embodiment of the present invention, and 10
0 is an 8: 4: 4 digital video system, and the digital video signal (luminance signal and color difference signal) from here is
It is divided into a main signal and a sub signal and input to the conversion device 200 of the present invention. In this conversion device 200, an input digital video signal is converted into a high definition standard digital video signal, which is input to a digital video system (digital video tape recorder) 300 and recorded.

Here, the conversion device 200 is, for example, as shown in FIG.
The configuration is as shown in FIG. That is, the input unit 201,
The main signal and the sub signal are respectively supplied to 202,
It is introduced into the input processing unit 203. The main signal and the sub signal are obtained by distributing the 525 sequential scanning signal for each line as shown in FIGS. 2A and 2B. The luminance signal pixels of the main signal are shown as Y ′, the color difference signal pixels are shown as Cb ′, Cr ′, the luminance signal pixels of the sub signal are shown as Y ″, and the color difference signal pixels are shown as Cb ″, Cr ″. The luminance signal pixel in the main signal is 72 in the horizontal direction.
0 pixels, vertical 254 (first field) or 2
53 (second field), and the color difference signal pixel Cb ′
, Cr ′ are 360 pixels in the horizontal direction and 254 (first field) or 253 (second field) in the vertical direction, respectively. The luminance signal pixels in the sub signal are 720 pixels in the horizontal direction and 253 (first field) or 254 (second field) in the vertical direction, and the color difference signal pixels Cb ′ and Cr ′ are 360 in the horizontal direction, respectively.
Pixels, vertical 253 (first field) or 25
4 (second field). One pixel is composed of 10 bits.

The input processor 203 separates the sync signal, and the sync signal is input to the timing generator 221. The timing generation unit 221 generates a clock that is sampling-synchronized with the input digital video signal and various timings, and supplies this to the memory control counter unit 222. The memory control counter unit 222 uses the address memory 2
A timing signal and a clock are given to 23. Then, the address memory 223 outputs the write address according to the sequence of the predetermined pattern and supplies it to the address input section of the conversion memory section 204. As a result, the input video signal from the input processing unit 203 is written in the conversion memory unit 204.

As the conversion memory section 204, for example,
A data storage device having a capacity capable of writing one frame of video data in the format shown in FIG. 2 is used. Memory control counter unit 22
2 also supplies a timing signal and a clock to the address memory 224. This address memory 2
24 outputs a read address according to a sequence of a predetermined pattern and supplies the read address to the address input section of the conversion memory section 204. As a result, it is derived from the conversion memory unit 204 in the form of being mapped to a predetermined pattern, that is, a format of a digital video signal of the high-definition standard, and supplied to the output processing unit 205.

3A to 3D show the mapping state. In FIG. 3A, first, 20
Is a digital first field area in the high definition standard, and has 1920 pixels in the horizontal direction and 517 pixels in the vertical direction.
Each pixel is 8 bits. The above-mentioned video data is stored in this field. That is, the luminance signal of the main signal of the first field and the luminance signal of the sub signal are combined to produce Y ′ +
Y ″, and is further divided into an upper 8-bit pixel group 21 and a lower 2-bit pixel group 22. And this luminance signal is
It is mapped to the digital first field area 20 of the HDTV signal. In the digital second field area 23, the color difference signals in the main signal and the sub signal of the first field are combined to be C ′ + C ″, and this signal is also supplied to the upper 8-bit pixel group 24 and the lower 2-bit pixel group 25. Be divided. Then, this color difference signal is mapped to the digital second field area 23 of the HDTV signal (FIG. 3).
(B)). Similarly, for the main signal and the sub-signal of the second field, the upper 8-bit pixel group 2 of the luminance signal is stored in the digital third field area 26 shown in FIG.
7, the lower 2 bit pixel group 28 is mapped, and FIG.
An upper 8-bit pixel group 30 and a lower 2-bit pixel group 31 of the color difference signal are mapped in the digital fourth field area 29 shown in (D). The same processing is repeated for the subsequent fields. The high-definition digital recording / reproducing apparatus is capable of recording / reproducing a high-definition video signal of 1125/60, that is, 1125 scanning lines at a field frequency of 60 Hz, and digital lines 1 to 563 are the digital first field and the digital line. 564 to 1125 are used as the digital second field.

The signal read in the above mapping state is input to the output processing unit 205, converted into serial data, and supplied to the recording system of the VTR. By mapping as described above, 8: 4: 4 (4:
2: 2, 4: 2: 2) data can be easily recorded by the HDTV standard processing system. This is because the digital field of the output digital video video signal (HDTV standard signal) after conversion is smaller in bit rate than the input digital video signal having a high bit rate, but has a two-dimensional spatial capacity larger than that of the input digital video signal. Because there is a big relationship. At the time of playback, if you reverse the above process,
The original digital video signal can be reproduced.

In the above description, the luminance signal Y: the color difference signal C
b: The sampling rate ratio of the color difference signal Cr is 8: 4: 4
Signal is converted so that it can be easily processed by the processing system of HDTV standard (BTA S-002), but not limited to this, luminance signal Y: color difference signal Cb: color difference signal Cr: alpha
Conversion of signals having a sampling rate ratio of 4: 4: 4: 4, or luminance signal Y: color difference signal Cb: color difference signal C
The sampling rate ratio of the r: alpha signal is 4: 2: 2:
Conversion of the 4 signal is also conceivable. The alpha signal is additional information such as chroma key.

FIG. 4A shows another embodiment of the present invention. In this embodiment, the LinkA signal and the LinkB signal from the 4: 4: 4: 4 video system 400 are input to the conversion apparatus 200 of the present invention and converted into a high-definition standard digital video signal, and a digital video system (digital It is recorded by a video tape recorder) 300. 4B and 4C, the sampling rate ratio of the luminance signal Y: the color difference signal Cb: the color difference signal Cr: alpha signal is 4: 4: 4: 4 (LinkA signal 4: 2: 2,
LinkB signals 4: 2: 2) are shown. Here, the LinkA signal and the LinkB signal are ITU-R B
T. It is a 4: 2: 2 digital video signal defined by 656, and Y of the LinkB signal is alpha for chroma key.
Signals, etc.

The LinkA signal is composed of a luminance signal Y and two color difference signals Cb and Cr, and the color difference signals Cb and Cr are
It is an even-numbered pixel in the field. The LinkB signal is composed of an alpha signal and two color difference signals Cb and Cr, and the color difference signals Cb and Cr are odd-numbered pixels in the field. These signals are 254 lines / field in the first field, 253 lines / field in the second field, 720 pixels / line for luminance signals Y and alpha signals, 360 pixels / line for color difference signals Cb and Cr, and 10 pixels for 1 pixel. It consists of bits.

In order to map the signal as described above into a predetermined format, the mapping as shown in FIGS. 5A to 5D is performed. That is, 50, 55,
Reference numerals 60 and 65 are digital first, second, third and fourth field areas in the high definition standard, respectively.
Horizontal 1920 pixels, Vertical 517 pixels, 1 pixel 8
Is a bit. For the digital first field area 50, the luminance signal Y of the first field is al in the left area.
The pha signal is mapped to the right region. In this case, since there is a difference in the bit rate of the setting signal with respect to the field area 50, the luminance signal Y and the alpha signal are divided into upper 8-bit pixel groups 51 and 52 and lower 2-bit pixel groups 53 and 54. Thus, for example, the upper 8-bit pixel groups 51 and 53 are arranged in the vertical upper area, and the lower 2-bit pixel groups 52 and 54 are arranged in the lower area.

Next, for the digital second field area 55, the color difference signal Cb + Cr is divided into an 8-bit pixel group 56 and a 2-bit pixel group 57, which are respectively arranged in an upper area and a lower area in the vertical direction. .

Hereinafter, the signals of the second field of the LinkA signal and the LinkB signal are also mapped to the digital third and fourth fields, as in the case of the first field (FIG. 5 (C), ( See D)). Also in the case of this embodiment, the configuration of the conversion device 200 is as shown in FIG. 1B, and the address generation sequence of the address memories 223 and 224 is different from that of the previous embodiment.

FIG. 6 shows an apparatus for restoring the original digital video signal from the signal whose data structure has been converted by the first and second embodiments. The input processing unit 601 has a structure shown in FIG.
Alternatively, a digital video signal having the structure shown in FIG. 5 is input. The synchronization information extracted by the input processing unit 601 is input to the timing generation unit 611. Here, the clock synchronized with the input digital video signal is reproduced and input to the memory control counter unit 612. The clock and counter data generated by the memory control counter unit 612 are supplied to the write address memory 613. The address memory 613 generates an address for loading the input digital video signal into the memory unit 602. As a result, the digital video signal having the structure shown in FIG. 3 or 5 is written in the memory unit 602. The timing signal of the memory control counter unit 612 is also given to the read address memory 614. Address memory 6
14, when reading data from the memory unit 602,
An address for which a read sequence is set in advance is written so that the digital video signal having the original structure can be obtained, and the data in the memory unit 602 is read based on this address. The read data is output as the main signal and the sub signal or the LinkA signal and the LinkB signal through the output processing unit 603. As the memory unit, a high-speed read / write FIF
O memory is used.

The present invention is not limited to the above embodiment. In the above embodiment, as shown in FIG. 3 or 5, the input digital video signal is decomposed and arranged. However, there is more room in the two-dimensional spatial domain of HD video systems. Therefore, character information such as a title may be further stored as auxiliary data in this spare space. This auxiliary data can be freely separated and derived in the output processing unit 603. Further, when inputting, the input processing unit 203 may capture it.

Furthermore, in the first embodiment, a signal having a sampling rate ratio of luminance signal Y: color difference signal Cb: color difference signal Cr of 8: 4: 4 is converted to HDTV standard (BTA).
S-002) was converted so that it could be processed easily, but the input digital video signal was originally a conventional 2: 2: 2 interlaced scanning type video signal, and this type of video signal The channel images or the left and right channel images of the stereo image may be distributed to the main signal side and the sub signal side for conversion.

Furthermore, although the above description has not described the method and type determination of the input digital video signal, type determining means for automatically determining is provided, and based on the determination result, a plurality of address memories are stored. The address memory having an appropriate address sequence may be automatically selected from

[0023]

As described above, according to the present invention, digital video signals of various standards can be recorded / reproduced by using the digital recording / reproducing apparatus of a predetermined format.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an input digital video signal of FIG.

FIG. 3 is an explanatory diagram of a data structure of an output digital video signal of the conversion device of FIG.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention and its input digital video signal.

5 is an explanatory diagram of a data structure of an output digital video signal of the conversion apparatus of FIG.

FIG. 6 is a diagram showing a third embodiment of the present invention.

[Explanation of symbols]

100, 400 ... Digital video system, 200 ... Conversion device, 300 ... HD digital video system, 203
Input processing unit, 204 ... Memory unit, 205 ... Output processing unit, 221 ... Timing generating unit, 222 ... Memory control counter unit, 223, 224 ... Address memory.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshinobu Miyazaki, 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Abu E., Ltd.

Claims (6)

[Claims] 1. An input digital video signal including at least a luminance signal and a chrominance signal, which has a bit rate higher and a two-dimensional spatial region smaller than a digital television video signal of a predetermined format, is stored in a capacity of the predetermined format. As a means for converting the data structure so that it fits, a memory for converting the data structure, a writing means for writing the input digital video signal in the memory in synchronization with the input digital video signal, and the input digital held in the memory. When reading the video signal, the upper bit data of the input digital video signal is read and set in the first area of the format, the lower bit data is read and set in the second area of the format, and the data structure is changed. A reading means for reading the converted second digital video signal. Video signal converting apparatus characterized by a. 2. The reading means arranges a digital luminance signal in the first and second areas in the digital first field of the second digital video signal, and the digital luminance signal in the first field in the digital second field. The new video signal conversion device according to claim 1, wherein a digital color difference signal is arranged in the second area. 3. The video signal conversion device according to claim 1, wherein the first and second areas are the left and right sides in the horizontal direction of the two-dimensional spatial area of the second digital video signal. . 4. The input digital video signal is a signal in which a sampling rate ratio of a luminance signal Y: color difference signal Cb: color difference signal Cr is 8: 4: 4, and a main signal of 4: 2: 2 and 4: 2. 4. The video signal conversion according to claim 3, wherein the read means arranges the composite signal of the main signal and the sub signal in the first and second areas, respectively. apparatus. 5. The first and second regions are vertically above and below the two-dimensional space region of the second digital video signal, and the first and second regions are two-dimensional space. 2. The video signal conversion device according to claim 1, wherein third and fourth regions are further set on the left and right sides of the region in the horizontal direction, and above and below the right side. 6. The video signal conversion apparatus according to claim 5, wherein digital luminance signals are arranged in the first and second areas, and additional signals are arranged in the third and fourth areas.