JPH08107527A - Image processor - Google Patents

Abstract

PURPOSE: To improve the degree of freedom of arithmetic to an electric charge read from a photoelectric converting element by performing the vertical scanning of an object while using plural rows of image sensors. CONSTITUTION: One terminals of multigate MOS transistors 21 to 24 are connected to the output terminals of photoelectric converting elements D1i to D4i in the same column of the image sensors provided with four rows of photoelectric converting elements, thier other terminals are commonly connected to one terminals of multigate MOS transistors 31 to 34 and their other terminals are commonly connected. The multi-gate MOS transistors 21 to 24 are functioned as analog buffer registers and time division charge distributors, the multigate MOS transistors 31 to 34 are functioned as analog integrators for controlling an input/output gate and corresponding to control signals to these instruments, various kinds of arithmetic can be performed to the electric charges read from the photoelectric converting elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing image data obtained by optically or mechanically sub-scanning an object using a plurality of rows of image sensors.

[0002]

2. Description of the Related Art In a fax machine, a scanner, an infrared imaging device, etc., a one-dimensional sensor is used to optically or mechanically sub-scan an object to obtain two-dimensional image data. In high-speed reading and low-illuminance imaging, in order to improve the S / N ratio, a time-delay integration (integrating outputs of photoelectric conversion elements in the same column of an image sensor having photoelectric conversion elements in a plurality of rows in synchronization with sub-scanning ( TDI) system is adopted.

FIG. 12 shows a photoelectric conversion element D11 of 4 rows and n columns.
~ D1n, D21 to D2n, D31 to D3n and D41
7 shows a conventional TDI image processing circuit for D4n. In FIG. 12, the rows of the photoelectric conversion elements are described separately, but in reality, the rows are arranged close to each other. The electrons photoelectrically converted by the photoelectric conversion elements D11 to D1n in the first row are sequentially transferred in the horizontal transfer CCD 1 in synchronization with the four-phase clock through the multi-gate MOS transistors 211 to 21n for realizing the TDI method. After that, the charges are sequentially transferred by the vertical transfer CCD 5 in synchronism with the four-phase clock, amplified by the charge / voltage conversion circuit 6, and output. The same applies to the first to second rows.

[0004]

In the conventional TDI method, the charges are transferred only in one direction by the CCDs 1 to 5, so only the time division transfer in the multi-gate MOS transistor and the addition when entering the CCD can be calculated. Since this is not possible and the degree of freedom in calculation is low, it is not possible to perform optical reciprocating sub-scanning for high-speed reading, for example.

In view of the above problems, an object of the present invention is to provide an image processing apparatus which has a high degree of freedom in calculation of charges read from a photoelectric conversion element.

[0006]

According to the present invention, there is provided an image processing device for arithmetically controlling outputs of first to m photoelectric conversion elements in the same column of an image sensor having a plurality of rows of photoelectric conversion elements. The 1i input terminal is connected to one end of the i-th photoelectric conversion element, and charges from the photoelectric conversion element are connected to the 1i-th photoelectric conversion element.
Held in a region, the charge held in the first i region is transferred to the second i region in response to the first control signal, and the held charge in the second i region is output from the first i output end in response to the second i control signal. And a charge supplied to the 2j-th input terminal in response to the 3j-th control signal is added to the current held charge and held in the 3j-th region, and in response to the 4j-th control signal. A second j charge storage / transfer section that outputs the charges held in the third j area from the second j output terminal, i = 1 to m, j = 1 to
u, the first to 1m output terminals and the second to 2u input terminals are commonly coupled to each other, and
2u output terminals are commonly connected to each other, and
A control unit that generates 21st to 2mth and 31st to 3uth control signals.

According to the present invention, the 1i-th charge storage / transfer section functions as an analog buffer register and a time division charge distributor, and the 2j-th charge storage / transfer section functions as an analog integrator whose input / output gates can be controlled. A first control signal and a second i control signal for the first i-th charge storage / transfer section, and a second
Various calculations can be performed on the charges read from the photoelectric conversion element by the 3jth control signal and the 4jth control signal to the j charge accumulation transfer unit, so that the degree of freedom in calculation is high.

In the first aspect of the present invention, the first i-th charge storage / transfer section is a multi-gate MOS transistor in which first to fifth gates are arranged in parallel, and the first-i region is the first.
an i-potential well, the first i-potential well having a first constant potential at one end thereof supplied to the first gate and a second bottom having a bottom portion supplied to the second gate.
The second end is formed to have a constant potential, and the other end is formed to be variable in height by the first control signal supplied to the third gate.
The i region is a second i potential well, the bottom of the second i potential well is formed at a third constant potential supplied to the fourth gate, and one end thereof is at the other end of the first i potential well. Yes, the other end is formed to be variable in height by the 2i control signal supplied to the fifth gate.

In a second aspect of the present invention, the 2jth charge storage / transfer section is a multi-gate MOS transistor in which sixth to ninth gates are arranged in parallel, and the 3jth region is a third gate.
the third j-th potential well, one end of which is supplied to the sixth gate.
The control signal is formed to be variable in height, the bottom portion of which is formed of fourth and fifth constant potentials which are supplied to the seventh and eighth gates, and the other end portion of which is supplied to the ninth gate. Four
It is formed to be variable in height by the j control signal.

In a third aspect of the present invention, the 2j-th charge storage / transfer section is a multi-gate MOS transistor in which sixth to ninth gates are arranged in parallel, and one end of the 3j-th region is the first gate. It is formed by the fourth constant potential supplied to the 6th gate, and the middle part thereof is formed by the 3jth control signal and the 4th jth signal.
The height is variable according to a control signal, and the other end is formed with a fifth constant potential supplied to the ninth gate.

In the conventional image processing apparatus using CCD, C is used.
Although it was difficult to reduce the price because a special production line was required for producing the CD, according to the above first to third aspects, the image processing apparatus can be configured using MOS transistors, so the cost can be reduced. . Further, according to the third aspect, since the 2j-th charge storage / transfer section also functions as a charge pump,
It is possible to simplify the configuration of the amplifier circuit for the output.

In a fourth aspect of the present invention, the above u is an integer multiple of the above m, and the control section uses the above first control signal to simultaneously hold the charges held in the above 11 to 1m regions respectively. 2m region, and the 21st to 2m control signals cause the stored charges of the 21st to 2m regions to be sequentially output from the 11th to 1m output ends in a time division manner.
The 3j-th control signal causes the charge supplied to the 2j-th input terminal to be added to the charge currently held in the 3j-th region, and the 4k-control signal causes the charge to be held in the 3k-th region. Charge is output from the 2k output terminal,
~ M The charges corresponding to the same pixel read from the photoelectric conversion element are integrated in the 3j-th region, and the charges of the 3k-region where the integration is completed are output from the 2k output terminal, k is determined, and the above processing is repeatedly executed.

According to the fourth aspect, the time delay integration (TDI) system can be realized as an example of the above calculation.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] As shown in FIG. 6B, the image sensor 10 includes a photoelectric conversion element Dji of 4 rows and n columns, j = 1 to 4,
It has i = 1 to n. Image data of the area 12 of the read object 11 shown in FIG. 6A is obtained at the same time by the image sensor 10, and an optical or mechanical scanning device (not shown) indicates the direction of the arrow in the column direction of the image sensor 10. Subscan to Y.

At time t00, the pixels d, c,
b and a are read by the photoelectric conversion elements D1i, D2i, D3i, and D4i on the i-th column of the image sensor 10, respectively. The pixel data read at this time is set to d1, c
Represented as 2, b3, a4. At time t10 when one pixel is sub-scanned in the direction Y, the data of the pixels e, d, c, and b read by the photoelectric conversion elements D1i to D4i are changed to e1, d2, c3.
And b4. The same applies hereinafter. For example, at time t00,
By integrating the data d1 to d4 of the pixel d read at t10, t20, and t30, random noise is reduced and the SN ratio is theoretically improved by 4 = 2 times.

FIG. 1 shows a schematic configuration of an image processing circuit for the image sensor 10. The image processing circuits for the respective columns of the image sensor 10 have the same configuration, and FIG. 2 shows a configuration example of the image processing circuits for the photoelectric conversion elements D1i to D4i in the i-th column. For simplification of the component identification code, the symbols 21i to 24i of the components in the i-th column in FIG. 1,
In FIG. 2, 31i to 34i, 40i, and 50i are simply denoted as 21 to 24, 31 to 34, 40, and 50 by omitting i.

The circuit shown in FIG. 2 has photoelectric conversion elements D1i to D1.
4i are formed on the same semiconductor substrate. FIG.
Shows a more detailed configuration and operation of the multi-gate MOS transistor 21 in FIG. This multi-gate MOS
The transistor 21 has the same structure as the conventional multi-gate MOS transistor 211 shown in FIG. In the photoelectric conversion elements D1i to D4i, the p-type region is connected to the ground line, and the n-type regions are connected to the source regions N1 (input ends) of the multi-gate MOS transistors 21 to 24, respectively. Multi-gate MOS transistors 21-24
Functions as an analog buffer register and a time division charge distributor capable of controlling the intermediate gate G22 and the output gate G25. Multi-gate MOS transistors 21-2
4 have the same configuration as each other, and as shown in FIG.
Gates G21, G22, G23, G24 and G25 are arranged in a line above the n-type diffusion regions N1 and N2 in the mold substrate with the insulating film Z interposed therebetween. These gates are
For example, the surface (thick line portion) of polycrystalline silicon is thermally oxidized to form an insulating film, and the gates are insulated from each other. The gates G21 to G24 are commonly connected to the multi-gate MOS transistors 21 to 24, and the gates G21 to G24 are supplied with the constant potentials V1 and V2, the control signal φ1, and the constant potential V3 from the control circuit 60, respectively. . Control signals φ21 to φ24 independent of each other are supplied from the control circuit 60 to the gates G25 of the multi-gate MOS transistors 21 to 24.

The photoelectric conversion elements D1i to D4i are, for example, infrared photodiodes and have a relatively large background noise. Therefore, in order to improve the SN ratio, the gate G22 is used.
An nMOS transistor T1 for resetting charges is formed in the potential well portion below the central portion of the. That is, the n-type diffusion region N2 is formed below the central portion of the gate G22, and the gate G2 is formed above the periphery thereof with the insulating film Z interposed therebetween.
0 is formed, and the N2 between the n-type diffusion regions is the power supply line VDD.
And a reset signal RST1 is supplied to the gate G20.

As shown in FIG. 2, the gates and drains of the charge reset nMOS transistors T1 to T4 of the multi-gate MOS transistors 21 to 24 are connected in common. 2 and 2 show the gate potential for electrons, and the control signal φ1,
φ21 to φ24 are low level VL1 or high level VH1
Is a binary potential of For example, the constant potentials V1, V2 and V3 are 0V, 3V and 3V, respectively, and the low level VL1 and the high level VH1 are 0V and 3.5V, respectively.

When the control signal φ1 is at the low level VL1, one of the charges (electrons in this embodiment) generated by the pair of photoelectric conversion elements D1i to D4i is formed below the gate G22 of each of the multi-gate MOS transistors 21 to 24. Are accumulated in the region A which is a potential well. The control signal φ1 is once set to the high level VH1 and then set to the low level VL.
Returning to 1, the charges accumulated in the region A are transferred to the region B which is a potential well formed below the gate G24 of each of the multi-gate MOS transistors 21 to 24. Then, the reset signal RST1 turns on the MOS transistors T1 to T4 to extract the free electrons in the n-type region of the region A, and the reverse voltage is applied to the depletion layer.

When the control signals φ21 to φ24 are once set to the high level VH1 and then returned to the low level VL1, the charges accumulated in the region B are transferred to the multi-gate MOS transistors 21 to 21.
24 is taken out to the other n-type diffusion region N3 (output end). The n-type diffusion regions N3 of the multi-gate MOS transistors 21 to 24 are connected to each other, and further, the multi-gate MOS transistor 31 of the second charge storage / transfer section 30.
One of the n-type diffusion regions (input end) is also connected to the other n-type diffusion regions. This n-type diffusion region functions as an analog time division bus.

Multi-gate MOS transistors 31 to 3
Reference numeral 4 functions as an analog integrator whose input / output gate can be controlled. Multi-gate MOS transistors 31-34
Have the same configuration as each other, and have gates G31, G32, and G3 above the p-type region between the n-type diffusion regions via an insulating film.
3 and G34 are arranged in one row. The gates G32 and G33 are commonly connected to the multi-gate MOS transistors 31 to 34, respectively.
2 and G33 are supplied with constant potentials V4 and V5 from the control circuit 60, respectively. Control signals φ31 to φ34 and φ41 to φ44, which are independent of each other, are supplied from the control circuit 60 to the gates G31 and G34 of the multi-gate MOS transistors 31 to 34.

For example, the constant potentials V4 and V5 are 4 respectively.
V, 7V, and high level V of control signals φ31 to φ34
H2 is 5V, high level VH3 of control signals φ41 to φ44
Is 8V. Control signals φ31 to φ34 and φ41 to φ
When φ3j is once set to the high level VH2 and then returned to the low level VL1 with 44 set to the low level VL1, the charges from the first charge storage transfer unit 20 are generated in the potential well below the gate G33 of the multi-gate MOS transistor 3j. It is taken into a certain area C and added to the electric charge held in the area C until then. In this state, if the control signal φ4j is once set to the high level VH3 and then returned to the low level VL1,
The charges held in the region C are taken out to the other n-type diffusion region of the multi-gate MOS transistor 3j.

Multi-gate MOS transistors 31 to 3
The other n-type diffusion regions 4 are connected to each other, and are further connected to one n-type diffusion region of the multi-gate MOS transistor 40. The multi-gate MOS transistor 40 functions as a charge pump for pushing up the electrons to the low potential side. The multi-gate MOS transistor 40 includes gates G41, G42, G43, G44, and G above the p-type region between the n-type diffusion regions via an insulating film.
45 are arranged in one row. Gates G41 and G45
The control circuit 60 supplies constant potentials V6 and V7, respectively. Control signals φ5 to φ7 independent of each other are supplied from the control circuit 60 to the gates G42 to G44.

For example, the constant potentials V6 and V7 are each 9
V3V, and high level VH4 of control signals φ5 to φ7
Is 12V, and the low level VL2 of the control signal φ5 is 5V. Control signals φ5, φ6 and φ7 are set to low level V
When the control signal φ5 is set to the high level VH4 from the state of L2, VL1, and VL1, the charges below the gate G41 are transferred to the region D which is the potential well below the gate G42. Next, the control signal φ6 is set to the high level VH4,
Next, when the control signal φ5 is returned to the low level VL2, the charges in the region D are transferred to the region E which is the potential well below the gate G43. Next, the control signal φ7 is set to the high level VH4.
Then, when the control signal φ6 is returned to the low level VL1, the charge in the region E is transferred to the region F which is the potential well below the gate G44. Next, when the control signal φ7 is returned to the low level VL1, the charges in the region F are transferred to the other n-type diffusion region of the multi-gate MOS transistor 40.

The other n-type diffusion region of the multi-gate MOS transistor 40 is connected to the charge / voltage converter 50. In the charge / voltage conversion unit 50, a switching MOS transistor 51 is connected between the power supply wiring Vdd and the output end of the multi-gate MOS transistor 40, and an amplification MOS transistor 52 is provided between the power supply wiring Vdd and the output line 54. The switching MOS transistor 53 is connected in series, and the gate of the MOS transistor 52 is connected to the output terminal of the multi-gate MOS transistor 40. The output line 54 is common to each column of the image sensor 10, and is connected to the ground line via the load nMOS transistor 55. MOS transistors 51, 5
For example, both 2 and 53 are n-channel type. M
The gates of the OS transistors 51 and 53 are supplied with the reset signal RST2 and the main scanning clock φ8i from the control circuit 60, respectively.

When the MOS transistor 53 is turned on by the main scanning clock φ8i, a current corresponding to the potential of the output terminal of the multi-gate MOS transistor 40 is supplied to the power supply wiring Vd.
d to the output line 54 through the MOS transistors 52 and 53, and the potential Vout of the output line 54 changes to the multi-gate M.
It has a value corresponding to the potential of the output terminal of the OS transistor 40. MOS transistor 5 by reset signal RST2
When 1 is turned on, multi-gate MOS transistor 4
The electrons accumulated at the 0 output end (n-type diffusion region) are MOS
It is pulled out to the power supply wiring Vdd side through the transistor 51.

Control signals other than the main scanning clock φ8i are
The image processing circuit for each column of the image sensor 10 is common. The main scanning clock φ8i is a control signal φ6.
Alternatively, φ7 becomes a positive pulse at the i-th position obtained by dividing the low level VL1 into n. As a result, a signal obtained by integrating four pixel data for each pixel of one row of the reading object 11 is
It is taken out to the output line 54 in the order of i = 1 to n.

The operation of the circuit shown in FIG. 2 will be described in detail with reference to FIG. In FIG. 4, the various binary levels in FIG. 2 are shown as the same for simplification. The sub-scanning direction of the area 12 is the direction Y in FIG. FIG. 5 schematically shows the charge integration process of the circuit of FIG. (T00) The control signals φ1, φ41, and φ5 transition to the high level, and the control signals φ24 and φ31 transition to the low level.

As a result, the charge transfer from the regions A to B of the multi-gate MOS transistors 21 to 24 is started, and the charge transfer from the region B of the multi-gate MOS transistor 24 to the region C of the multi-gate MOS transistor 31 is stopped. , Multi-gate MOS transistor 31
The charge transfer from the area C to the area D of the multi-gate MOS transistor 40 is started. The signal output to the output line 54 is being continued, and is sequentially continued until the time point t02 below.

Referring to FIG. 5A, the multi-gate M
Charge z1 + z2 + z held in the OS transistor 31
The output of 3 + z4 is started. Charges c1, b1 + b2 are applied to the multi-gate MOS transistors 32-34, respectively.
And a1 + a2 + a3 are held. (T01) The control signals φ1 and φ41 transition to the low level, and the reset signal RST1 and the control signals φ21, φ31, and φ6 transition to the high level (RST1 is the potential Vdd).

As a result, the charge transfer from the regions A to B of the multi-gate MOS transistors 21 to 24 is stopped, and the charges in the region A are extracted to the power supply line Vdd through the MOS transistors T1 to T4. Further, the charge transfer from the region B of the multi-gate MOS transistor 21 to the region C of the multi-gate MOS transistor 31 is started, and the charge transfer from the region C of the multi-gate MOS transistor 31 to the region D of the multi-gate MOS transistor 40 is stopped. It

Referring to FIG. 5A, the multi-gate M
Charge z1 + z2 + z held in the OS transistor 31
The output of 3 + z4 is stopped, and the transfer of the charge d1 from the multi-gate MOS transistors 21 to 31 is started. (T02) Reset signal RST1, control signals φ21, φ
31 and φ5 transit to low level, and control signals φ22 and φ
32, φ7 and the reset signal RST2 transition to high level.

As a result, the photoelectric conversion elements D1i to D4i
Of the free electrons in the n-type region of the multi-gate MOS transistor 21 is stopped, the charge transfer from the region B of the multi-gate MOS transistor 21 to the region C of the multi-gate MOS transistor 31 is stopped, and the region E of the multi-gate MOS transistor 40 is stopped.
A part of the charges are transferred from F to F, the transfer of the charges c2 from the region B of the multi-gate MOS transistor 22 to the region C of the multi-gate MOS transistor 32 is started, and the output end of the multi-gate MOS transistor 40 is connected to the power supply wiring Vdd. Of electric charges is started.

(T03) Control signals φ22, φ32, φ6
And the reset signal RST2 transits to the low level, and the control signals φ23 and φ33 transit to the high level. As a result, the charge transfer from the region B of the multi-gate MOS transistor 22 to the region C of the multi-gate MOS transistor 32 is stopped, and the multi-gate MOS transistor 23
Transfer of the charge b3 from the area B of the multi-gate MOS transistor 33 to the area C of the multi-gate MOS transistor 33 is started,
The remaining charges are transferred from the regions E to F of the S transistor 40, and the extraction of charges from the output end of the multi-gate MOS transistor 40 to the power supply wiring Vdd is stopped.

(T04) Control signals φ23, φ33 and φ
7 goes low, and the control signals φ24 and φ34 go high. As a result, the charge transfer from the region B of the multi-gate MOS transistor 23 to the region C of the multi-gate MOS transistor 33 is stopped, and the charge a4 from the region B of the multi-gate MOS transistor 24 to the region C of the multi-gate MOS transistor 34 is stopped. Transfer is started, and charges z1 + z are transferred from the region F of the multi-gate MOS transistor 40 to the gate of the MOS transistor 52.
2 + z3 + z4 are transferred. Further, signal output to the output line 54 in sequence from i = 1 is started.

Similarly, at time t10, the multi-gate MOS transistor 34 moves from the region C to the multi-gate M.
Charge a1 + a2 + a3 to the region D of the OS transistor 40
+ A4 transfer is started, and at time t14, the multi-gate M
Charges a1 + a2 + a3 + a4 are transferred from the region F of the OS transistor 40 to the gate of the MOS transistor 52, and the multi-gate MOS transistor 33 is transferred at time t20.
Transfer of the charges b1 + b2 + b3 + b4 from the region C of the above to the region D of the multi-gate MOS transistor 40,
At time t24, charge b1 + is applied from the region F of the multi-gate MOS transistor 40 to the gate of the MOS transistor 52.
b2 + b3 + b4 is transferred, and at the time t30, the multi-gate M is transferred from the region C of the multi-gate MOS transistor 32.
Charge c1 + c2 + c3 to the region D of the OS transistor 40
+ C4 transfer is started, and at time t34, the multi-gate M
The charges c1 + c2 + c3 + c4 are transferred from the region F of the OS transistor 40 to the gate of the MOS transistor 52.

As is clear from the above configuration and operation,
In the first embodiment, the control signals .phi.1 and .phi.21 to .phi.24 for the first charge storage and transfer unit 20, and the control signals .phi.31 to .phi.34 and .phi.41 for the second charge storage and transfer unit 30.
Various operations can be performed on the image data by ˜φ44. For example, when the sub-scanning direction of the area 12 in FIG. 6A is set to the −Y direction, simply control signals φ21 to φ are used.
The time-division reading order from the first charge storage / transfer section 20 by means of 24 is reversed from the case of FIG. 4, or the control signals φ31 to φ
34 and φ 41 to φ 44
The time division input / output order may be reversed from that in FIG. This makes it possible to reverse the sub-scanning direction each time,
That is, reciprocal sub-scanning can be performed, and the reading speed can be improved.

Also, for example, only three columns of the four columns of photoelectric conversion elements Dji of the image sensor 10 are used, and the first charge accumulation transfer unit 20 and the second charge accumulation transfer unit 3 corresponding thereto are used.
By using only the column of 0, the yield of the image sensor 10 can be improved, and the photoelectric conversion element D can be used for a long period of time.
When a defect occurs in ji, it can be relieved.

Further, when it is desired to perform averaging (blurring) processing, for example, the control signals φ21 to φ24 are made equal to each other and the control signals φ31 to φ34 and φ41 to φ44 are set to a constant potential, so that the second charge storage / transfer unit 30 is formed. By setting the through state, the moving averaging process can be performed at high speed by hardware in the previous stage of the output line 54. Also, FIG.
In the conventional image processing apparatus using a CCD shown in FIG. 2, charges must be transferred by the CCDs 1 to 4 even in the number of stages equal to the number n of photoelectric conversion elements for one row, for example, 500 stages. C
In manufacturing a CD, a buried channel formation (ion implantation and drive-in) step is required, and if the number of steps is large, the yield is reduced. Therefore, crystal point defects are caused by intrinsic gettering or ring gettering. It must be removed or otherwise complicated. Therefore, a special manufacturing line is required and it is difficult to reduce the price. However, in the image processing apparatus of the first embodiment,
Since the number of transfer stages is small, the price can be reduced.

[Second Embodiment] In the second embodiment, as shown in FIG. 7, multi-gate MOS transistors 401 to 40 are provided.
The output of n is supplied to the CCD 1 and sequentially transferred in one direction as in FIG. 12, and the electric charge extracted from the output end of the CCD 1 is converted into a voltage by the charge / voltage conversion circuit 6. Thus, even if the CCD 1 transfers in one direction, there is no problem because the calculation with a high degree of freedom has already been performed.

[Third Embodiment] In the third embodiment, FIG.
As shown in (B), the image sensor 10A includes photoelectric conversion elements Dji, j = 1, 2, and i = 1 to n in 2 rows and n columns. In the image sensor 10A, there is a one-pixel interval between the photoelectric conversion elements in the first and second columns. The image sensor 10A simultaneously obtains the image data of the regions 121 and 122 of the read object 11 shown in FIG. 11A, and the image data is in the column direction of the image sensor 10A by an optical or mechanical scanning device (not shown). Sub scanning is performed in the arrow direction Y.

At time t00, the pixel c in the area 121 and the pixel a in the area 122 are respectively in the image sensor 10A.
Are read by the photoelectric conversion elements D1i and D2i in the i-th column of. The read pixel data are represented as c1 and a2. At time t10 when one pixel is sub-scanned in the direction Y, the data of the pixels d and b read by the photoelectric conversion elements D1i and D2i are represented as d1 and b2. The same applies hereinafter. For example, the data c1 of the pixel c read at the times t00 and t20
And c2 are added, the random noise is reduced and the SN ratio is theoretically improved by a factor of 2.

The image processing circuits for the respective columns of the image sensor 10A have the same configuration, and FIG. 8 shows the image processing circuits for the photoelectric conversion elements D1i and D2i in the i-th column. The first charge storage / transfer unit 20A includes the photoelectric conversion element D1i.
And a multi-gate MOS transistor 22 corresponding to the photoelectric conversion element D2i.

In the second charge storage / transfer section 30A, the gates G31 of the multi-gate MOS transistors 31 to 34 are commonly connected to each other, and the constant potential V4 is supplied to the gates G31 of the multi-gate MOS transistors 31 to 34.
Are respectively supplied with control signals φ31 to φ34, control signals φ41 to φ44 are respectively supplied to gates G33 of the multi-gate MOS transistors 31 to 34, and gates G34 of the multi-gate MOS transistors 31 to 34 are commonly connected to each other. A constant potential V5 is supplied to.

The control signal output from the control circuit 60A is represented by the potential waveform of the gate for electrons in FIG. 8 and the timing chart shown in FIG.
By forming the region G that temporarily holds electric charges immediately before the region C of the multi-gate MOS transistors 31 to 34, the multi-gate MOS transistors 31 to 34 also serve as a charge pump. The potential increase required at 40 is less than in the case of FIG.
The S transistor 40 becomes unnecessary.

Other points are the same as in the case of the first embodiment. Also in the third embodiment, various calculations can be performed on the image data as in the first embodiment. For example,
The read density can be halved by not using the multi-gate MOS transistors 33 and 34 and performing the same processing as in the case where the 4-row configuration of the first embodiment is changed to the 2-row configuration.

The present invention includes various modifications other than the above. For example, in FIG. 2 or 8, the multi-gate MOS transistor 40 can be omitted by increasing the drain potential of the MOS transistor 52. In addition, a hole is taken out from the photoelectric conversion element Dji,
The image processing device may be composed of pMOS transistors. As the photoelectric conversion element Dji, various types that can convert light into electric charges can be used.

[0049]

As described above, according to the image processing apparatus of the present invention, the first ii charge storage / transfer section functions as an analog buffer register and a time division charge distributor, and
The j charge accumulation transfer unit functions as an analog integrator capable of controlling the input / output gate, and the first control signal and the second i control signal for the 1i charge accumulation transfer unit and the 3j control signal and the third control signal for the 2j charge accumulation transfer unit Various operations can be performed on the charges read from the photoelectric conversion element by the 4j control signal, so that there is an advantage that the degree of freedom in calculation is high with a simple configuration.

According to the first to third aspects of the present invention, since the image processing apparatus can be constructed by using the MOS transistor which does not require a special manufacturing line, there is an effect that the cost can be reduced. . According to a third aspect of the present invention, a second
Since the j charge storage / transfer section also functions as a charge pump, it is possible to simplify the configuration of the amplifier circuit for the output thereof.

According to the fourth aspect of the present invention, one of the above operations is performed.
As an example, it is possible to realize the time delay integration method.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing circuit for an image sensor including photoelectric conversion elements of 4 rows and n columns according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an image processing circuit and a gate potential for one row of photoelectric conversion elements in FIG.

FIG. 3 is a diagram showing a more detailed structure and operation of the multi-gate MOS transistor in FIG.

FIG. 4 is a timing chart showing the operation of the circuit of FIG.

5 is an explanatory diagram of charge integration processing of the circuit in FIG.

FIG. 6 is a diagram showing a relationship between a photoelectric conversion element of an image sensor and a reading pixel.

FIG. 7 is a block diagram of an image processing circuit for an image sensor including photoelectric conversion elements of 4 rows and n columns according to a second embodiment of the present invention.

FIG. 8 is a diagram showing an image processing circuit and a gate potential for one row of photoelectric conversion elements according to a third embodiment of the present invention.

9 is a timing chart showing the operation of the circuit of FIG.

10 is an explanatory diagram of charge integration processing of the circuit of FIG.

FIG. 11 is a diagram showing a relationship between photoelectric conversion elements of an image sensor and read pixels.

FIG. 12 is a block diagram of a conventional image processing circuit for an image sensor including photoelectric conversion elements arranged in 4 rows and n columns.

[Explanation of symbols]

10, 10A Image sensor 11 Object to be read D11 to D4n Photoelectric conversion element 20, 20A First charge storage transfer unit 30, 30A Second charge storage transfer unit 21-24, 31-34, 40 Multi-gate MOS transistor 50 Charge / voltage Converter 51, 52, 53, T1 to T4 MOS transistor 54 Output line 60, 60A Control circuit

Claims (5)

[Claims] 1. An image processing apparatus for arithmetically controlling outputs of first to m-th photoelectric conversion elements in the same column of an image sensor having a plurality of rows of photoelectric conversion elements, wherein a first i-th input terminal is the i-th photoelectric conversion element. Connected to one end,
The charge from the photoelectric conversion element is held in the first i region (A), and the held charge in the first i region is transferred to the second i region (B) in response to the first control signal (φ1) to perform the second i control. In response to the signal (φ2i), the charge held in the second i region is changed to the first i
The 1i-th charge storage / transfer section (2i) output from the output end and the charge supplied to the 2j-th input end in response to the 3j-th control signal (φ3j) are added to the current held charge to add to the 3j-th region (C). ), And outputs the electric charge held in the 3j-th region from the 2j-th output end in response to the 4j-th control signal (φ4j), and i = 1 to m, j = 1 to u, the first to 1m output terminals and the second to 2u input terminals are commonly coupled to each other, and the second to 2u output terminals are commonly coupled to each other, and An image processing apparatus, comprising: a control unit that generates the first, 21st to 2mth, and 31st to 3uth control signals. 2. The first i charge storage / transfer portion is a multi-gate MOS transistor in which first to fifth gates are arranged in parallel, the first i region is a first i potential well, and the first i potential well is , One end of which is formed with a first constant potential supplied to the first gate, the bottom of which is formed with a second constant potential supplied to the second gate, and the other end of which is supplied to the third gate The second i region is a second i potential well, and the second i potential well is formed at a third constant potential whose bottom is supplied to the fourth gate. ,
The one end thereof is the other end of the first i potential well, and the other end is formed to be variable in height by the second i control signal supplied to the fifth gate. Image processing device. 3. The second j charge storage / transfer section is a multi-gate MOS transistor in which sixth to ninth gates are arranged in parallel, the third j region is a third j potential well, and the third j potential well is , One end of which is formed to be variable in height by the third j control signal supplied to the sixth gate, and the bottom of which is formed of fourth and fifth constant potentials supplied to the seventh and eighth gates. The image processing apparatus according to claim 1 or 2, wherein the other end is formed to be variable in height by the 4j control signal supplied to the ninth gate. 4. The second j-th charge storage / transfer section is a multi-gate MOS transistor in which sixth to ninth gates are arranged in parallel, and one end of the third-j region is supplied to the sixth gate. A fifth constant voltage is formed with a fourth constant potential, an intermediate part of which is formed to be variable in height by the third jj control signal and the fourth jj control signal, and the other end of which is supplied to the ninth gate.
The image processing apparatus according to claim 1, wherein the image processing apparatus is formed at a constant potential. 5. The u is an integer multiple of the m, and the controller causes the first control signal to simultaneously transfer the charges held in the first to 1 m regions to the 21 to 2 m regions, respectively. The 21st and 2m control signals correspond to the 21st and 2nd control signals, respectively.
The retained charges in the m region are sequentially output from the first to 1m output ends in a time division manner, and at this time, the charges supplied to the second j input end are currently retained in the third j region by the 3j control signal. Stored charge, and the charge held in the 3k region is added to the 2k region by the 4k control signal.
The charges corresponding to the same pixel read from the 1st to m-th photoelectric conversion elements are integrated in the 3j-th region, and the charges in the 3k-th region where the integration is completed are output from the 2k-output end. 5. The image processing apparatus according to claim 1, wherein the j and k are determined as described above, and the above processing is repeatedly executed.