JPH08107342A - Output buffer circuit - Google Patents

Abstract

PURPOSE: To obtain an output buffer circuit in which the operating speed is not reduced even when a power supply voltage drops. CONSTITUTION: The circuit is provided with transistors(TRs) PM5, NM6 having 1st and 2nd power supply lines whose potential differs from each other, a couple of current terminals and a control terminal receiving an input signal, a circuit 1 connected between the 1st power supply wire and one current terminal of the TRs MP5, NM6 and including at least either of a load and a switching element, and a voltage application means 4 connected between the other current terminals of the TRs PM5, NM6 and the 2nd power supply line, in which the 2nd power supply line is connected to the other current terminals usually, and applying a bias voltage transiently to the TRs PM5, NM6 and the other current terminals so that a voltage between the current terminals of the TRs MP5, NM6 is higher than the voltage between the 2nd power supply terminal and the one current terminal of the TRs PM5, NM6 in the case of the switching state of the TRs PM5, NM6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit for supplying an output signal of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art The structure and operation of a conventional output buffer circuit will be described with reference to FIG. FIG. 5A shows a conventional NMOS type output buffer circuit. Power supply voltage V _CC
And the ground potential V _SS between the nMOS transistor NM1
And NM2 are connected in series. Transistor NM
The input signals φ _A ,
φ _B is given. The interconnection point between the transistors NM1 and NM2 forms and outputs the output signal φ _OUT .

When the input signal φ _A rises and the input signal φ _B falls at the same time, the transistor NM1 is turned on and the transistor NM2 is turned off. A current flows through the transistor NM1 and the transistor NM
By charging a load capacitance (not shown) connected to the interconnection point between 1 and NM2, the output signal φ _OUT rises.

On the contrary, when the input signal φ _A falls and the input signal φ _B rises at the same time, the electric charge accumulated in the load capacitance is discharged through the transistor NM2. Therefore, the output signal φ _OUT falls.

In the above description, the input signals φ _A and φ _B
, But the tri-state buffer as shown in FIG. 5A does not always make a simultaneous transition.

FIG. 5B shows a conventional CMOS type output buffer circuit. The pMOS transistor PM3 and the nMOS transistor NM4 are connected in series between the power supply voltage V _CC and the ground potential V _SS . Transistor PM
3, the gate electrode of NM4, input signal φ _C ,
φ _D is given. The interconnection point between the transistors PM3 and NM4 forms and outputs the output signal φ _OUT .

When the input signals φ _C and φ _D fall, the transistor PM3 is turned on and the transistor NM4 is turned on.
Turns off. A current flows through the transistor PM3, and a load capacitance (not shown) connected to the interconnection point between the transistors PM3 and NM4 is charged, so that the output signal φ _OUT rises.

On the contrary, when the input signals φ _C and φ _D rise, the electric charge accumulated in the load capacitance is discharged through the transistor NM4. Therefore, the output signal φ _OUT falls. In this way, when the output signal changes, a large drive current flows in order to charge and discharge the load connected to the output terminal. The power supply voltage wiring and the ground wiring are formed of wiring having a resistance as low as possible in order to suppress a decrease in the power supply voltage due to the drive current and noise generated in the ground wiring.

[0009]

In recent years, there has been an increasing demand for lower voltage and higher speed of semiconductor integrated circuits. However, when the driving voltage is lowered, the operation speed becomes slow. Therefore, it is difficult to satisfy both low voltage and high speed at the same time. Hereinafter, with reference to FIG. 6, the factors that reduce the operation speed when the voltage is lowered will be described.

FIG. 6 shows the drain current characteristics of a normal nMOS transistor. The horizontal axis represents the drain-source voltage V _ds , and the vertical axis represents the drain current I _ds . The curves in the figure show the drain currents when the gate-source voltage is constant. The gate voltage V _gs is 3V, 4V,
When it is increased to 5 V, the drain current I _ds increases as shown in the figure.

When the drain voltage V _ds is reduced while keeping the gate voltage V _gs constant, the drain current decreases along the drain current curve as shown by the arrow a1. Further, if the gate voltage V _gs is lowered while keeping the drain voltage V _ds constant, the drain current is reduced as shown by the arrow a2.

That is, when the MOS transistor is driven at a low voltage, the drain current decreases. Therefore, the time for charging or discharging the load capacity becomes long and the operation speed decreases.

An object of the present invention is to provide an output buffer circuit whose operating speed does not decrease even if the power supply voltage is decreased.

[0014]

The output buffer circuit of the present invention includes first and second power supply wirings having different potentials from each other.
A load and a switching element, which are connected between a transistor having a pair of current terminals and one control terminal, and an input signal is input to the control terminal, and one current terminal of the transistor and the first power supply wiring. Connected between the second power supply wiring and the other current terminal of the transistor and a circuit including at least one of the transistors, the second power supply wiring is normally connected to the other current terminal, and the transistor is switched when the transistor is switched. Voltage supply means for transiently supplying a bias voltage to the other current terminal of the transistor so that the voltage between the current terminals of the transistor and the second power supply wiring becomes larger than the voltage between the one current terminal of the transistor. .

The voltage supply means may supply the bias voltage in a pulsed manner in synchronization with a change in the state of the input signal.

[0016]

When the voltage between the pair of current terminals of the transistor is increased, a larger current flows. When a large current flows, the load capacitance of the transistor can be charged and discharged faster, and thus the switching speed becomes faster.

When this circuit is applied to the output buffer circuit of the semiconductor memory, the speed of the memory can be increased. In order to increase the switching speed, the voltage between the current terminals may be increased only during the period from when the input signal of the transistor starts to change to when the output signal becomes the steady state.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of an output buffer circuit according to an embodiment of the present invention will be described with reference to FIG.

FIG. 1A shows an output buffer circuit according to the embodiment. The drain electrodes of the pMOS transistor PM5 and the nMOS transistor NM6 are connected to each other and form and output the output signal φ _OUT . The high-voltage generation circuit 1 is connected between the source electrode of the transistor PM5 and the power supply wiring that supplies the power supply voltage V _CC, and
Negative voltage generating circuit 4 is connected between M6 and a ground wire supplying ground potential V _SS . Input signals φ _P and φ _N are applied to the gate electrode of the transistor PM5 and the gate electrode of the transistor NM6, respectively.

The high voltage generating circuit 1 has a high voltage generating unit 2 and a high voltage generating unit 2.
The negative voltage generating circuit 4 is composed of the voltage applying section 3,
The pressure generating unit 5 and the negative voltage applying unit 6 are included. High voltage
The pressure generation circuit 1 supplies a voltage to the source electrode of the transistor PM5.
Source voltage V_CCOr power supply voltage V _CCSelect higher voltage than
Can be supplied to. The negative voltage generation circuit 4 is
Ground potential V is applied to the source electrode of the transistor NM6._SSOr ground
Rank V_SSIt is possible to selectively supply a negative voltage lower than
Wear.

When the input signals φ _P and φ _N fall, the transistor PM5 is turned on and the transistor NM6 is turned off. A current flows through the transistor PM5 that is turned on to charge a load capacitance (not shown) connected to the drain electrodes of the transistors PM5 and NM6.

When the input signals φ _P and φ _N rise, the transistor PM5 is turned off and the transistor NM6 is turned on. A current flows through the transistor NM6 that is turned on, and the charge accumulated in the load capacitance is discharged.

Next, referring to FIG. 1B, the input signal is
Taking the rise time as an example, the operation of the output buffer circuit
explain about. FIG. 1B shows the input signal φ._INStands
Input signal φ when rising_INAnd output signal φ _OUTWaveform of
Show. Input signal φ_PAnd φ_NHave the same waveform
Input signal φ_INExpressed by

The output signal φ _OUT2 shows the case where the negative voltage -V _BB is applied to the source electrode of the transistor NM6 by the negative voltage generation circuit 4, and the output signal φ _OUT1 is directly grounded to the source electrode of the transistor NM6. The case where the potential V _SS is applied is shown.

When the input signal φ _IN rises from the time T ₀ and exceeds the threshold of the transistor NM6, the transistor NM6 is turned on. When the transistor NM6 is turned on, the charge accumulated in the load capacitance is discharged through the transistor NM6 as described above, and the output signal φ _OUT drops.

When the negative voltage -V _BB is applied to the source electrode of the transistor NM6, the voltage between the source and the drain becomes higher than when the ground potential V _SS is applied. If the drain voltage with respect to the source is high, a larger drain current flows, so that the fall of the output signal φ _OUT2 becomes steeper than the fall of the output signal φ _OUT1 .

The threshold voltage for determining low level is V _L
Then, when the input signal φ _IN rises, the output signal φ
The delay time until _OUT becomes low level is t _{1 in} the figure when the negative voltage generating circuit 4 applies a negative voltage, and t ₂ in the figure when a ground potential is applied. Thus, by inserting the negative voltage generating circuit 4 and applying the negative voltage to the source electrode of the transistor NM6, the switching time can be shortened.

Also, when the input signal φ _IN falls, the high voltage generating circuit 1 is similarly inserted and the transistor P
Switching time can be shortened by applying a voltage higher than the power supply voltage V _CC to the source electrode of M5.

When the negative voltage -V _BB is constantly applied to the source electrode of the transistor NM6, a large noise is secondarily generated in the wiring supplying the negative voltage -V _BB . This noise adversely affects other circuits in the board using the negative voltage -V _BB . For example, in a DRAM, the negative voltage applied to the back gate of the cell transistor is
When shared with V _BB , it affects the operation of the DRAM cell. Also, the capacity of the negative voltage power supply must be increased.

Next, a configuration example of the negative voltage generating circuit 4 will be described with reference to FIGS. It will be apparent to those skilled in the art that the high voltage generation circuit 1 can be realized with the same configuration. FIG. 2A shows the configuration of the negative voltage generator 5 of FIG. The output terminal 11 that supplies the negative voltage -V _BB has nM
It is connected to the oscillation circuit 10 via the OS transistor NM8 and the capacitor C1. The oscillator circuit 10 outputs a rectangular wave. The gate electrode of the transistor NM8 is connected to the output terminal 11. The interconnection point 12 between the capacitor C1 and the transistor NM8 is an nMOS transistor N
It is connected to the ground wiring V _SS via M7. The output signal of the oscillation circuit 10 is applied to the gate electrode of the transistor NM7.

The potential of the output signal of the oscillation circuit 10 is φ ₂ , the potential of the interconnection point 12 is φ ₃ , and the potential of the output terminal 11 is φ _4.
And When the potential φ ₃ is higher than the potential φ ₄ , the transistor NM8 is turned off, and when the potential φ ₄ is higher than the potential φ ₃ and the difference is larger than the threshold voltage of the transistor NM8, the transistor NM8 is turned on. Turns on. That is, the transistor NM8 functions as a diode.

FIG. 2B shows a signal waveform of the circuit of FIG. The oscillator circuit 10 outputs a rectangular wave as indicated by the polygonal line φ ₂ . When the potential φ _{2 of the} output signal is at high level, the capacitor C1 is charged and the potential φ ₃ at the interconnection point 12 rises. At this time, since the transistor NM7 is in the ON state, the potential φ ₃ never exceeds the ground potential V _SS .

The potential φ of the output signal of the oscillation circuit 10₂Stands
When it goes down, the potential φ of the interconnection point 12 ₃Also falls. This
, The potential φ of the output terminal 11_FourIs the power of interconnection point 12
Position φ ₃Transistor NM8 is on
It becomes a state. When the transistor NM8 is turned on,
The charge accumulated in the capacitor C1 is transferred to the transistor
Discharged through NM8 and potential φ at interconnection point 12₃But
As it rises, the potential φ of the output terminal 11_FourIs reduced
You.

When the output signal of the oscillation circuit 10 rises again and the potential φ ₂ becomes high level, the transistor NM is turned on.
7 is turned on, the capacitor C1 is a transistor N
Charged through M7. As the capacitor NM7 is charged, the potential φ _{3 at the} interconnection point 12 changes to the ground potential V _SS.
Rise towards. When the potential φ _{3 at the} interconnection point 12 becomes higher than the potential φ _{4 at the} output terminal 11, the transistor N
M8 is turned off, and the potential φ ₄ of the output terminal 11 maintains a constant value.

By repeating charging and discharging of the capacitor C1, the potential φ ₄ of the output terminal 11 gradually decreases. When the potential φ ₄ of the output terminal 11 reaches the potential −V _BB which is higher than the minimum potential of the potential φ ₃ of the interconnection point 12 by the threshold value of the transistor NM8, the transistor NM8 is not turned on. Therefore, the potential φ ₄ of the output terminal 11 becomes a constant negative potential −V _BB .

FIG. 3A shows a configuration example of the negative voltage applying section 6 of FIG. The source electrode of the transistor NM6 is connected to the ground wiring V _SS via the nMOS transistor NM8 and is connected to the wiring supplying the negative voltage −V _BB via the nMOS transistor NM9. The gate electrode of the transistor NM9, the signal phi ₁ is applied to the gate electrode of the transistor NM8 the signal phi ₁ via the NOT gate NOT1 are given.

FIG. 3B is a signal wave of the circuit of FIG.
Show the shape. Time T₀Input signal from φ _NIs up
You. Signal φ₁Is the input signal φ_NWith a pulse waveform synchronized with
is there. For example, input signal φ_NObtained by differentiating
Can be Signal φ₁Becomes a high level state
If the gate voltage of the transistor NM9 exceeds the threshold,
The transistor NM9 is turned on. At this time,
The transistor NM8 is turned off. Because of this, Transis
Potential φ of the source electrode of the NM6_SIs a negative voltage −V_BBTona
You. The source drain of the transistor NM9 is actually
Curve φ due to resistance between_SAs shown in
It becomes a waveform.

The rising of the input signal φ _N turns on the transistor NM6. At this time, since the potential φ _{S of the} source electrode is negative, the drain-source voltage and the gate-source voltage increase, and a large drain current flows. For this reason, the electric charge charged in the load capacitance is discharged, and the output signal φ _OUT decreases toward the potential φ _S.

As described above, since a larger drain current flows as compared with the conventional example shown in FIG. 5, the fall time of the output signal φ _OUT can be shortened. FIG. 4A shows another configuration example of the negative voltage applying section 6 of FIG. The source electrode of the transistor NM6 is connected to the ground wiring V _SS via the resistor R1.
It is connected to the. The nMOS transistor NM10 and the capacitor C2 are connected in series, a negative voltage −V _BB is applied to the transistor NM10 side contact of this series circuit, and the ground potential V _SS is applied to the capacitor C2 side contact.

The interconnection point between the transistor NM10 and the capacitor C2 is connected to the source electrode of the transistor NM6 via the nMOS transistor NM11.
An input signal φ _N is given to the gate electrode of the transistor NM11, and _N is given to the gate electrode of the transistor NM10.
The input signal φ _N is supplied via the OT gate NOT2.

FIG. 4B shows a signal waveform of the circuit of FIG. The threshold value is set so that the transistor NM10 is turned on and the transistor NM11 is turned off when the input signal φ _N is at a low level.

When the input signal φ _N is low level, the capacitor C2 is charged through the transistor NM10.
The potential of the interconnection point between the capacitor C2 and the transistor NM10 becomes -V _BB.

When the input signal φ _N rises at time T ₀ , the transistor NM10 is turned off and the transistor NM11 is turned on. At this time, the transistor N
The potential φ _S of the source electrode of M6 drops to the negative potential −V _BB . In addition, actually, the source of the transistor NM11-
Due to the resistance between the drains, the potential φ _S has a blunt waveform as shown in the figure.

The negative charge accumulated in the capacitor C2 discharges the positive charge at the output terminal and is discharged through the resistor R1. As it is discharged, the potential φ _S rises and converges to the ground potential V _SS . Note that the potential φ _S may fluctuate positively due to the relationship with the load capacitance.

Thus, the input signal φ_NAt the start of
In addition, the capacitor C2 allows the transistor NM6
Potential φ_SIs negative, the output signal is the same as in the case of FIG.
No. φ _OUTThe fall time of can be shortened.

In the configuration of FIG. 4A, the negative voltage -V
_{Since the} wiring supplying _BB is not directly connected to the source electrode of the transistor NM6, the negative voltage −V _BB is not affected even if the output signal φ _OUT changes. Therefore, the negative voltage −
V _BB can be stabilized. The resistor R1 is shown in FIG.
It is also possible to replace it with a combination of a NOT gate and a transistor as in the above embodiment.

Such an output buffer circuit is, for example,
It can be used as an output buffer circuit that outputs data stored in a semiconductor memory. This is effective in lowering the driving voltage of the semiconductor memory and maintaining high speed.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0049]

As described above, according to the present invention,
It is possible to suppress a decrease in switching speed when the drive voltage of the output buffer circuit is decreased. When this output buffer circuit is applied to a semiconductor memory, the operation speed of the memory can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention and a graph showing a signal waveform of the output buffer circuit.

FIG. 2 is a circuit diagram of the negative voltage generator of FIG. 1 and a graph showing a signal waveform of this circuit.

3 is a circuit diagram of a configuration example of the negative voltage applying section of FIG.
3 is a graph showing a signal waveform of this circuit.

4A and 4B are a circuit diagram of another configuration example of the negative voltage applying section of FIG. 1 and a graph showing a signal waveform of this circuit.

FIG. 5 is a circuit diagram of an output buffer circuit according to a conventional example.

FIG. 6 is a graph showing drain current characteristics of a MOS transistor.

[Explanation of symbols]

 1 High Voltage Generation Circuit 2 High Voltage Generation Section 3 High Voltage Application Section 4 Negative Voltage Generation Circuit 5 Negative Voltage Generation Section 6 Negative Voltage Application Section 10 Oscillation Circuit 11 Output Terminal 12 Mutual Connection Point PM pMOS Transistor NM nMOS Transistor R Resistance C Capacitor NOT NOT gate

Claims (3)

[Claims] 1. A transistor having first and second power supply wirings having different potentials, a pair of current terminals and a control terminal, and an input signal being input to the control terminal, A circuit that is connected between one current terminal and the first power supply line and that includes at least one of a load and a switching element, and is connected between the other current terminal of the transistor and the second power supply line. The second power supply line is normally connected to the other current terminal, and when the transistor is switched, the voltage between the current terminals of the transistor is
An output buffer circuit having voltage supply means for transiently supplying a bias voltage to the other current terminal of the transistor so as to be higher than the voltage between the one current terminal of the transistor and the second power supply wiring. . 2. The output buffer circuit according to claim 1, wherein the voltage supply means supplies the bias voltage in a pulsed manner in synchronization with a change in the state of the input signal. 3. The voltage supply means selects a bias voltage generation circuit for generating the bias voltage, and selects one of the voltage of the second power supply wiring and the bias voltage for the other current terminal of the transistor. 3. The output buffer circuit according to claim 1, further comprising switching means for selectively applying the voltage.