JPH08107209A - Transistor circuit - Google Patents

Abstract

PURPOSE: To make possible reducing chip area and chip cost, and improving yield. CONSTITUTION: A transistor circuit is constituted as follows; a first transistor T1 which has a first drain region 8, a first channel region 4, a first offset gate region 6, and a first gate electrode 12, and a second transistor T2 which has at least a second drain region 9, a second channel region 5, a second offset gate region 7, and a second gate electrode 13 are formed on the same chip, and the first transistor T1 and the second transistor T2 are connected in common with a source region 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor circuit, and particularly to an SOI for a switching power supply synchronous rectification circuit.
Horizontal power MO using (Silicon on Insulator) substrate
The present invention relates to an S field effect transistor circuit.

[0002]

2. Description of the Related Art FIG. 4 is a document (for example, N. Murakami, J. Aso).
h, K.Sakakibara, and T.Yachi, "A Highly Efficient, 30
-W Board Mounted Power Supply Module, "in Proc.IEE
FIG. 2 is a circuit diagram illustrating a configuration of a synchronous rectification circuit of a switching power supply disclosed in E INTELEC, Kyoto, pp.122-127, 1991.). 4, in the synchronous rectification circuit, a rectification element having resistance characteristics, for example, power MOS field effect transistors 20 and 21 is used in place of the conventional rectification diode to perform a rectification action, and a forward voltage drop is suppressed to perform switching. The conversion loss of the power supply can be reduced. In addition,
22 is a transformer and 23 is a diode.

As the power MOS field-effect transistor, a vertical structure element such as a VDMOS field-effect transistor has been used in the past, but the parasitic capacitance is increased as the switching frequency is increased in response to the demand for miniaturization of the switching power supply. The use of lateral power MOS field effect transistors using SOI substrates of small size has also been studied (eg T.Sakai, S.Matsumoto, IJKim, T.Yachi,
and T. Fukumitsu, "Potential of SOI Power MOSFETs as
a Switching Device for Megahertz DC / DC Converter
s, "in Proc. IEEE PESC, Taipei, pp. 450-456, 1994.).

FIGS. 5A and 5B show a conventional lateral power MO formed on an SOI substrate used in a synchronous rectification circuit.
FIG. 3 is a cross-sectional structure and a plane pattern diagram for explaining the configuration of an S field effect transistor circuit, respectively. In FIG. 5, 1 is a substrate, 2 is a buried insulating layer, 3 is a source region, 14 is a channel region, 15 is an offset gate region, 16 is a drain region, 17 is a gate insulating film, and 18 is a gate electrode (first conductive layer). Layers) and 19 are semiconductor active layers.

In such a structure, the substrate 1 is formed of single crystal silicon, polycrystalline silicon, aluminum nitride, silicon carbide crystal or diamond crystal, and has a thickness of 200 to 700 μm. Also,
The buried insulating layer 2 is made of silicon oxide, silicon nitride, S
It is formed of iON or tantalum oxide and has a thickness of 0.05 to 4 μm.

The gate insulating film 17 is made of silicon oxide, SiON, silicon nitride, tantalum oxide, or the like, and has a thickness of 10 to 200 nm. The gate electrode 18 is made of polycrystalline silicon, molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide, molybdenum, tungsten,
It is formed of tantalum or titanium and has a thickness of about 0.5 μm. The semiconductor active layer 19 is made of single crystal silicon and has a thickness of 0.1 to 1 μm.
Is.

When the lateral power MOS field effect transistor circuit configured as described above is applied to a synchronous rectification circuit of a switching power supply as shown in FIG. 4, specifically,
As shown in FIG. 6, the power MOS field effect transistor is composed of two chips (chip C1 and chip C2), and the lead terminal 24 of each source electrode is connected by the conductor pattern 25 and used. Further, in order to take out the terminals from the respective electrodes of the power MOS field effect transistor, it is necessary to provide the pad portions 26 such as the source pad 26S, the drain pad 26D and the gate pad 26G on the chips C1 and C2. In the power device, the area of the pad portion 26 is so large that it cannot be ignored as compared with the area of the active portion of the device, and the areas of the chips C1 and C2 are generally large.
In addition, 27 is a circuit board and 28 is a resin mold.

For connecting the pad portion 26 to each terminal 29, an aluminum wire 30 having a diameter of about several hundred μm is usually used. The wire 30 and the lead terminal 24 are used.
The resistance, parasitic inductance, and parasitic capacitance due to the increase in switching frequency become a problem in device operation. Further, in the synchronous rectification circuit shown in FIG. 4, it is necessary to externally add a resistance of about several Ω to the gate electrode terminal in order to avoid the simultaneous ON state of the rectification elements, which results in a large circuit volume. There is also.

[0009]

As described above, the conventional horizontal power MO used in the switching power supply synchronous rectification circuit is used.
Since the S field effect transistor is composed of two chips and the pads of each electrode are formed independently, there is a problem that the chip area becomes large, the yield of the device decreases and the chip cost increases.

Further, since the aluminum wire is used for the connection from the pad to the terminal, there is a problem that the resistance and the parasitic inductance and the parasitic capacitance of the wire and the lead terminal increase, which deteriorates the performance of the element. Further, in order to avoid the simultaneous ON state, it is necessary to add an individual resistance to the gate electrode, which causes a problem that the circuit volume of the switching power supply becomes large.

Therefore, the present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to reduce the chip area of a rectifying element and to improve the yield and the chip cost of a transistor. To provide a circuit.

[0012]

In order to achieve such an object, a first invention is to provide at least a first drain region, a first channel region, a first offset gate region and a first gate electrode. A first transistor having, and a second transistor
A second transistor having at least a drain region, a second channel region, a second offset gate region, and a second gate electrode are provided on the same chip, and the source is formed by the first transistor and the second transistor. Areas are commonly connected.

The transistor circuit according to the second aspect of the present invention is configured such that the first drain region and the second gate electrode are connected, and the second drain region and the first gate electrode are connected. . In the transistor circuit according to the third aspect of the invention, the first drain region and the second gate electrode are connected through the first resistor, and the second drain region and the first gate electrode are the second drain region and the second gate electrode. It is configured to be connected via a resistor.

[0014]

In the first aspect of the present invention, the source region is made common, so that the chip area can be reduced.
In the second aspect, the pads of the drain electrode and the gate electrode in the drain region can be shared, the chip area can be further reduced, and the resistance in the chip and the parasitic capacitance are not increased by the wiring in the chip. In the third invention, it is possible to eliminate the need for an external resistor added if necessary.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 shows a lateral power MO formed on an SOI substrate according to an embodiment of a transistor circuit of the present invention.
It is a figure explaining composition of an S field effect transistor circuit, Drawing 1 (a) shows a section structure, and Drawing 1 (b) is a figure showing the plane pattern. In FIG. 1, 1 is a substrate,
Reference numeral 2 is a buried insulating layer, 3 is a source region, and 19 is a semiconductor active layer.

Further, this lateral power MOS field effect transistor circuit comprises a first lateral power MO on the same substrate 1.
S field effect transistor T1 and second lateral power MO
An S field effect transistor T2 is formed. In this first lateral power MOS field effect transistor T1, 4 is a first channel region, 6 is a first offset gate region, 8 is a first drain region, 10
Is a first gate insulating film, 12 is a first gate electrode (first
Conductive layer).

In the second lateral power MOS field effect transistor T2, 5 is the second channel region, and 7 is
Is a second offset gate region, 9 is a second drain region, 11 is a second gate insulating film, and 13 is a second gate electrode (second conductive layer).

In such a structure, the substrate 1 is formed of single crystal silicon, polycrystalline silicon, aluminum nitride, silicon carbide crystal or diamond crystal, and has a thickness of 200 to 700 μm. Also,
The buried insulating layer 2 is made of silicon oxide, silicon nitride, S
It is formed of iON or tantalum oxide and has a thickness of 0.05 to 4 μm.

The gate insulating films 10 and 11 are made of silicon oxide, SiON, silicon nitride, tantalum oxide, or the like, and have a thickness of 10 to 200 nm.
The gate electrodes 12 and 13 are made of polycrystalline silicon, molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide, molybdenum, tungsten, tantalum, titanium or the like, and have a thickness of about 0.5 μm. In addition, the semiconductor active layer 19
Is formed of single crystal silicon and has a thickness of 0.1 to
It is 1 μm.

In such a structure, the source regions 3 are commonly connected to each other and connected to the source line S, and the first gate electrode 12 and the second gate electrode 13 are different from each other in the gate line G1 and the gate line G2. And the first drain region 8 and the second drain region 9 are connected to different drain wirings D1 and D2, respectively.

Further, the horizontal power M having the above-mentioned structure
The OS field effect transistor circuit has a structure in which a first lateral power MOS field effect transistor T1 and a second lateral power MOS field effect transistor T2 are formed in one chip C as shown in FIG. There is.

That is, in this case, although not shown, the source wiring S of the source region 3 shown in FIG.
Gate wiring G1 of the gate electrode 12, gate wiring G2 of the second gate electrode 13, drain wiring D1 of the first drain region 8, drain wiring D2 of the second drain region 9
It has a structure in which five pad portions corresponding to are formed. Note that in FIG. 2, the first gate electrode G1 and the second gate electrode G1
The pad portion corresponding to the gate electrode G2 of is omitted.

According to this structure, the first lateral power MOS field effect transistor T1 and the second lateral power MOS field effect transistor T2 are formed in the source region 3 thereof.
Therefore, the area of the source region 3 and the area of the source pad for extracting the electrode thereof can be reduced to about half of the conventional one, and the area of the chip C can be reduced.

(Embodiment 2) FIG. 3 is a diagram for explaining the configuration of a lateral power MOS field effect transistor circuit according to another embodiment of the transistor circuit of the present invention.
FIG. 3A shows a sectional structure, and FIG. 3B shows a plane pattern thereof. In FIG. 3, 1 is a substrate, 2 is a buried insulating layer, 3 is a source region, and 19 is a semiconductor active layer.

Further, this lateral power MOS field effect transistor circuit is provided with a first lateral power MO on the same substrate 1.
S field effect transistor T1 and second lateral power MOS
A field effect transistor T2 is formed. In this first lateral power MOS field effect transistor T1, 4 is a first channel region, 6 is a first offset gate region, 8 is a first drain region, 10 is a first gate insulating film, and 12 is a first gate insulating film. 1 gate electrode (first conductive layer).

In the second lateral power MOS field effect transistor T2, 5 is the second channel region, and 7 is the second channel region.
Is a second offset gate region, 9 is a second drain region, 11 is a second gate insulating film, and 13 is a second gate electrode (second conductive layer).

In such a structure, the substrate 1 is made of single crystal silicon, polycrystalline silicon, aluminum nitride, silicon carbide crystal or diamond crystal, and has a thickness of 200 to 700 μm. Also,
The buried insulating layer 2 is made of silicon oxide, silicon nitride, S
It is formed of iON or tantalum oxide and has a thickness of 0.05 to 4 μm.

The gate insulating films 10 and 11 are made of silicon oxide, SiON, silicon nitride, tantalum oxide, or the like and have a thickness of 10 to 200 nm.
The gate electrodes 12 and 13 are made of polycrystalline silicon, molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide, molybdenum, tungsten, tantalum, titanium or the like, and have a thickness of about 0.5 μm. In addition, the semiconductor active layer 19
Is formed of single crystal silicon and has a thickness of 0.1 to
It is 1 μm.

In such a structure, the source regions 3 are commonly connected to each other and connected to the source line S, and the second gate electrode 13 and the first drain region 8 are connected to the first drain line D1. First gate electrode 12 and second
And the drain region 9 thereof are respectively connected to the second drain wiring D2.

Further, the horizontal power M constructed as described above is used.
In the OS field effect transistor circuit, specifically, as shown in FIG. 2, a first lateral power MOS field effect transistor T1 and a second lateral power MOS field effect transistor T2 are formed in one chip C. A structure in which three pads 26S, 26D1, and 26D2 corresponding to the source wiring S, the first drain wiring D1, and the second drain wiring D2 of the source region 3 shown in FIG. 3 are formed on the chip C, respectively. Has become.

With such a configuration, the source region 3 of the first lateral power MOS field effect transistor T1 and the second lateral power MOS field effect transistor T2 can be made common, so that the source region 3 of the source region 3 can be made common. Since the area and the area of the source pad for taking out the electrodes can be reduced to about half of the conventional case, the chip area can be reduced.

Further, the first drain region 8 and the second gate electrode 13 are connected to a metal wiring such as aluminum, gold and copper in the chip, and the second drain region 9 and the first gate electrode 12 are further connected. In the chip are aluminum, gold,
Since it is connected to a metal wiring such as copper, the pads for taking out the terminals can be shared, and the chip area can be greatly reduced.

(Embodiment 3) In a further embodiment of the present invention, in the configuration of the above-described embodiment 2, the pattern shape of the conductive layer is changed between the first gate electrode 12 and the second gate electrode 13. As a result, the first gate electrode 12
It is possible to change the resistance value added to each of the gate electrode 13 and the second gate electrode 13.

For example, when the conductive layers of the first gate electrode 12 and the second gate electrode 13 are made of polycrystalline silicon having a sheet resistance of 10 Ω / □, the wiring length is set to several times the wiring width. Therefore, a resistance of several tens of Ω can be added.

According to such a structure, an externally added resistor is not required for the gate electrode terminal, the circuit volume can be reduced, and the simultaneous rectifying elements in the synchronous rectifying circuit can be prevented from being turned on at the same time.

In the embodiment described above, the case of using the surface channel type power MOS field effect transistor has been described, but the same effect as described above can be obtained by using the embedded type power MOS field effect transistor.

[0037]

As described above, according to the first invention, the chip area can be reduced, so that the yield and the chip cost can be improved. Further, according to the second aspect of the present invention, it is possible to suppress an increase in resistance due to, for example, the bonding wire and the lead terminal, and suppress parasitic inductance and parasitic capacitance. Therefore, it is possible to reduce deterioration of element performance due to a higher switching frequency. Further, according to the third aspect of the invention, it is possible to eliminate the need for an external resistor that is added if necessary, and thus it is possible to suppress an increase in circuit volume.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a lateral power MOS field effect transistor circuit for explaining an embodiment of a transistor circuit according to the present invention.

FIG. 2 is a perspective view showing a specific configuration of the transistor circuit of FIG.

FIG. 3 is a diagram showing a configuration of a lateral power MOS field effect transistor circuit for explaining another embodiment of the transistor circuit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of a switching power supply synchronous rectification circuit.

FIG. 5 is a diagram showing a configuration of a conventional lateral power MOS field effect transistor circuit.

6 is a perspective view showing a specific configuration of the transistor circuit of FIG.

[Explanation of symbols]

1 ... Substrate, 2 ... Buried insulating layer, 3 ... Source region, 4 ...
First channel region, 5 ... Second channel region, 6 ... First offset gate region, 7 ... Second offset gate region, 8 ... First drain region, 9 ... Second drain region, 10 ... 1st gate insulating film, 11 ... 2nd gate insulating film, 12 ... 1st gate electrode (1st conductive layer), 1
3 ... Second gate electrode (second conductive layer), 14 ... Channel region, 15 ... Offset gate region, 16 ... Drain region, 17 ... Gate insulating film, 18 ... Gate electrode (first conductive layer), 19 ... Semiconductor active layer, 20, 21 ... Power M
OS field effect transistor, 24 ... Lead terminal, 25 ...
Conductor pattern, 26S ... Source pad, 26D1 ... First drain pad, 26D2 ... Second drain pad, 29
… Terminals, 30… Aluminum wires, C… Chips, T1
... First lateral power MOS field effect transistor, T2
... A second lateral power MOS field effect transistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/12 Z 21/336 9056-4M H01L 29/78 617 A

Claims (3)

[Claims] 1. A first channel region and a second channel region are formed sandwiching a first source region, and a first gate electrode is formed on the first channel region via an insulating film. A second gate electrode is formed on the second channel region via an insulating film, a first offset gate region is formed adjacent to the first channel region, and a second offset gate region is formed on the second channel region. A second offset gate region is formed adjacently, a first drain region is formed adjacent to the first offset gate region, and a second drain region is formed adjacent to the second offset gate region. In the formed transistor circuit, the first gate electrode and the second gate electrode are connected to different gate wirings, and the first drain region and the second drain region are different from each other. Transistor circuit, characterized in that connected to the rain wiring. 2. A first channel region and a second channel region are formed with a first source region sandwiched therebetween, and a first gate electrode is formed on the first channel region with an insulating film interposed therebetween. A second gate electrode is formed on the second channel region via an insulating film, a first offset gate region is formed adjacent to the first channel region, and a second offset gate region is formed on the second channel region. A second offset gate region is formed adjacently, a first drain region is formed adjacent to the first offset gate region, and a second drain region is formed adjacent to the second offset gate region. In the formed transistor circuit, the first drain region and the second gate electrode are connected to the first wiring, and the second drain region and the first gate electrode are the first drain region and the first gate electrode. Distribution Transistor circuit, characterized in that it is connected to a different second wiring and. 3. A first channel region and a second channel region are formed with a first source region sandwiched therebetween, and a first gate electrode is formed on the first channel region with an insulating film interposed therebetween. A second gate electrode is formed on the second channel region via an insulating film, a first offset gate region is formed adjacent to the first channel region, and a second offset gate region is formed on the second channel region. A second offset gate region is formed adjacently, a first drain region is formed adjacent to the first offset gate region, and a second drain region is formed adjacent to the second offset gate region. In the formed transistor circuit, the first drain region and the second gate electrode are connected via a first resistance, and the second drain region and the first gate electrode are the first drain region and the second gate electrode. Transistor circuit, characterized in that it is connected via a different second resistor and the resistor.