JPH08107185A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To decrease testing cost by testing memory devices in parallel and simultaneously with the same pin configuration as of a conventional testing device at wafer testing in a semiconductor memory device that is loaded with a test mode of a data bit compression function. CONSTITUTION: A testing integrated circuit 13 that comprises buffer circuits 4, common input terminals 3 and common input and output terminals 14, and virtual large capacity memory IC's that comprises memory IC's 12 are formed on a wafer, and the input terminals of the memory IC's 2 are connected with the common input terminals 3 through the buffer circuits 4 inside the testing integrated circuit 13 and the data terminals are connected with the common input and output terminals of the testing integrated circuits 13 in the virtual large capacity memory IC's 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device that improves the test efficiency of a wafer test.

[0002]

2. Description of the Related Art A conventional semiconductor memory device ("memory IC")
A plurality of memory ICs 2 are formed on the wafer 1 as shown in FIG. 3. Each memory IC 2 exists completely independently as shown in FIG. A terminal (address and control clock) 5 and a data input / output terminal 6 were formed respectively.

In the electrical characteristic test (wafer test) of the memory IC 2, the input terminal 5 and the data input / output terminal 6 are used.
4, the probe needle 8 mounted on the probe card substrate 7 shown in FIG. 4 is brought into contact, and a signal from a test device (not shown) (abbreviated as “IC tester”) is input as an electric signal through the probe needle 8. And are conducting a test.

In this case, only the memory ICs that are in contact with the probe needles 8 can be tested, and in order to test all the memory ICs 2 formed on the wafer 1, the wafer 1 can be tested by a probing device (not shown). By moving a plurality of times (referred to as “probing”), the sequential memory I
The same test is repeatedly executed by bringing the probe needle 8 into contact with the input terminal 5 and the data input / output terminal 6 of C2.

The number of times of probing is determined by the number and arrangement of the memory ICs 2 formed on the wafer 1 and the performance of the IC tester.

Here, the performance of the IC tester is the simultaneous measurement capability of the memory IC under test in one probing, which is almost the same as the pin configuration of the IC tester (driver pin for input signal and data input / output signal). (For example, the comparator pin for).

[0007]

Generally, a memory IC
Test time increases with increasing memory capacity,
Test costs increase. Further, recently, as the memory capacity increases, the number of data bits is expanded, and the number of IC testers that can be simultaneously measured is remarkably reduced. This causes an increase in test cost. That is, in the test of the memory IC, the increase of the test cost is a big problem.

[0008] For such a problem, for example, Japanese Patent Laid-Open No.
Japanese Patent Laid-Open No. 2-179755 provides an IC device with a built-in test circuit capable of performing a burn-in test in a wafer state to judge pass / fail of the IC device, reducing the number of contact between the wafer and the prober, and shortening the time for parallel test. For the purpose of, a test circuit having a structure in which at least a power-supply energizing terminal wiring and other input terminal wiring are commonly connected to each of the independent chips which are formed on a semiconductor integrated circuit wafer and are regularly arranged. Embedded semiconductor integrated circuits have been proposed.

In the semiconductor integrated circuit (referred to as a "conventional example") proposed in Japanese Patent Laid-Open No. 62-179755, as shown in FIG. 6, a common wiring 10 is provided outside the semiconductor device 9 between the semiconductor devices 9. Common input / output terminal 11
By providing the above, a plurality of semiconductor devices 9 are simultaneously tested in parallel and the test time per wafer is shortened.

However, in the above-mentioned conventional example, since the data output terminals of the respective semiconductor devices 9 are commonly connected by the common wiring 10 between the semiconductor devices, all the output data of the respective semiconductor devices 9 are ORed (OR). Connected) and output to the common input / output terminal 11.

Therefore, if defective products are mixed in the commonly connected semiconductor device group, the defective semiconductor device 9 cannot be identified by one test, and each semiconductor device 9 is individually identified. By repeating the test of 1, the defective product is specified.

In this case, on the contrary, the test time becomes long.

In Japanese Patent Laid-Open No. 62-179755, a method is proposed in which output terminals such as data output terminals are not wired between chips.

However, when the data output terminals are not connected to each other, the number of the data output terminals of one semiconductor device 9 is multiplied by the number of the semiconductor devices 9 mutually connected by the common wiring 10. There is a problem that an IC tester equipped with the comparator pin is required, and the IC tester becomes more expensive.

In the above-mentioned conventional example, the input terminals of the plurality of semiconductor devices 9 are directly connected to each other, so that defective products having varying input levels are mixed in the interconnected semiconductor devices 9. At times, it is difficult to identify a defective semiconductor device 9.

Therefore, the present invention solves the above-mentioned problems and enables a plurality of semiconductor memory devices to be simultaneously tested in parallel while maintaining the pin configuration of the conventional test device, thereby reducing the test cost. The purpose is to provide.

[0017]

To achieve the above object, the present invention comprises, on a wafer, at least one test integrated circuit including an input / output terminal and a buffer circuit, and a plurality of semiconductor memory devices. I / O terminals of the plurality of semiconductor memory devices are electrically connected to the I / O terminals of the test integrated circuit so that the plurality of semiconductor memory devices form an apparently one semiconductor memory device. Provided is a semiconductor memory device characterized by being configured.

Further, according to the present invention, in a semiconductor memory device having a data bit compression function in a test mode, a test integrated circuit is provided for a predetermined number of semiconductor memory devices on a wafer, and the test integrated circuit is provided. Includes a plurality of common input terminals and a plurality of common input / output terminals, and at the time of a wafer test, signals are simultaneously distributed from the common input terminals to the same input terminals of the plurality of semiconductor memory devices. A semiconductor memory device is provided, in which compressed data bit signals output from the plurality of semiconductor memory devices are respectively supplied to the common input / output terminals. That is, the semiconductor memory device according to the present invention outputs the output value when all the plurality of data bit outputs from the predetermined data output terminal have the same value in the test mode, and outputs at least the plurality of data bit outputs. When one is different, the high impedance state is established.

In the semiconductor memory device of the present invention, preferably, the test integrated circuit includes a plurality of buffer circuits, and a signal input to one of the common input terminals is passed through the plurality of buffer circuits. A plurality of semiconductor memory devices are supplied to the same input terminal.

[0020]

According to the present invention, a plurality of interconnected semiconductor memory devices are virtually one large-capacity memory IC,
The test efficiency of the wafer test by the wafer prober and IC tester is improved.

The present invention has a plurality of data bits as a memory IC to be measured, and performs logical coincidence detection of each data bit among the plurality of data bits to detect among the plurality of data terminals of the memory IC to be measured. To the predetermined one terminal of the match detection result signal, for example, "1" level if all the data bits of the memory IC match with a logical "1", and if all the data bits match with a logical "0". A memory IC equipped with a test mode function that outputs a "0" level and sets to a high impedance state if there is a mismatch in even one bit of a plurality of data bit outputs. is there.

Therefore, according to the present invention, the measured memory ICs corresponding to the total number of the comparator pins included in the IC tester can be simultaneously used with the pin configuration of the IC tester when testing one measured memory IC. That can be tested,
A semiconductor memory device for reducing the test time of a wafer test is provided.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a wafer 1 on which a memory IC according to an embodiment of the present invention is formed.

Referring to FIG. 1, a plurality of virtual large capacity memory ICs 12 are formed on the wafer 1. As shown in the figure, the virtual large capacity memory IC 12 includes a plurality of memory ICs 2 and a test integrated circuit (“test IC”).
It is composed of 13).

FIG. 2 is a diagram showing a circuit configuration in the virtual large capacity memory IC 12 according to the present invention.

Referring to FIG. 2, a virtual large capacity memory I
The C12 is composed of a buffer IC 4, a common input terminal 3, and a test IC 13 formed of a common input / output terminal 14, and a plurality of memory ICs 2.

Then, the input terminals 5 of the plurality of memory ICs 2
Are electrically connected to the common input terminal 3 via the buffer circuit 4 of the test IC 13, and the data input / output terminal 6 of the memory IC 2 is connected to the common input / output terminal 14 of the test IC 13.

The memory IC2 has a data bit compression function for compressing data bits during a test. That is, the memory IC2 has a plurality of data bits, and in the test mode, performs a logical match detection of each output signal between the plurality of data bits, and determines a predetermined one of the plurality of data input / output terminals 6 of the memory IC2. If the match detection result signal, for example, all the data bits of the memory IC2 match with a logic "1", the one terminal (referred to as "test data terminal") is set to "1" level, and all the data bits are set to a logic "1". A test circuit (not shown) is provided which outputs a "0" level when there is a match with "0" and a high impedance level when even one bit among the plurality of data bits does not match.

The test circuit incorporated in the memory IC2 basically uses the exclusive OR circuit that receives a plurality of data output bits as inputs and the output of the exclusive OR circuit as the output control signal of the tri-state buffer. , The tri-state buffer outputs the output value (“H”, “L”) of the data bit in response to the matching or non-matching of the plurality of output data bits, or the output of the tri-state buffer becomes the high impedance state. That is, it is configured by a known method. Then, the memory IC2 preferably includes a test mode signal input terminal for inputting a control signal for activating the test circuit.

At the time of testing the wafer 1, an address and a control clock signal from an IC tester (not shown) are applied to the common input terminal 3 of the test IC 13 via the probe needle 8. Then, the signal applied to the one common input terminal 3 is
It branches to the input terminals 5 of the plurality of memory ICs 2 to be measured via the plurality of buffer circuits 4 that perform impedance conversion, and is simultaneously applied to these input terminals 5.

A write data signal from an IC tester (not shown) is input to the common input / output terminal 14 of the test IC 13 via the probe needle 8 and independently input to the data input / output terminals 6 of the plurality of measured memory ICs 2. Is applied.

When the memory under test IC2 is read out, the test data terminal of the memory under test IC2 outputs a logical coincidence detection signal of a plurality of data bits, and the signal is not output via the common input / output terminal 14 of the test IC13. I shown
Captured by C tester.

That is, the electrical characteristic test signal supplied from the IC tester is transmitted to the plurality of measured memories IC2 on the wafer 1 via the probe needle 8 and the test IC 13, and the plurality of measured memory ICs 2 are measured. The read data from the data is output as a logical match detection signal output from any one of the data input / output terminals 6 of FIG. 2 via the common input / output terminal 14 of the test IC 13 and the probe needle 8. It is transmitted to the comparator pin of the IC tester, and in this way, a plurality of virtual mass memory ICs
The plurality of memory ICs 2 in the group 12 are simultaneously tested in parallel.

In this embodiment, for example, a 4M-bit memory IC having 16-bit data bits is used.
(Actually 256K words x 16 bits)
When testing 2 with an IC tester having eight comparator pins, the comparator pin of the IC tester is connected to the common input / output terminal 14 of the test IC 13 and is used as a virtual large capacity memory IC12 of 256K. Eight memory ICs of word × 16 bits can be measured simultaneously.

In this case, 256K from the IC tester side
Since it is considered that one memory IC having a word × 8 bit configuration is being tested, it is possible to achieve eight times the processing capacity in an apparently equivalent test time.

Note that referring to FIG. 2, a plurality of memory ICs
The wiring between 2 and the test IC 13 is cut during dicing.

According to the present embodiment, by providing the test IC 13 for sharing the input / output with the tester pin for each predetermined number of memory ICs 2 on the wafer 1, the virtual large capacity memory IC group 12 is once formed. Therefore, the test time per memory IC can be substantially shortened. Further, the number of probing times is reduced, and the life of the probe needle is lengthened (for example, the life of the probe needle is several tens of times or more as compared with the conventional one). Further, since the number of movements of the probe needle is significantly reduced, contact failure due to needle misalignment or the like is avoided, and the reliability of test data is improved.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments and includes various embodiments according to the principle of the present invention. For example, the present invention is similarly applied to a simultaneous test of a random logic integrated circuit including a data input / output terminal and having a data bit compression function in the test mode.

[0039]

As described above, according to the present invention (Claim 1), the test IC for sharing the input / output with the tester pin is provided on the wafer for each predetermined number of memory ICs. Since a group of virtual large capacity memory ICs can be tested simultaneously at the same time, the test time per memory IC can be substantially shortened, the test efficiency can be improved, and the test cost can be reduced.

Further, according to the present invention (Claim 1), the number of probing times is reduced, the life of the probe needle is extended,
The running cost of the probe card can be reduced. Further, according to the present invention (Claim 1), there is an effect that contact failure due to needle misalignment or the like is avoided, and the reliability of test data is improved.

Furthermore, in a preferred aspect (claim 2) of the present invention, a test integrated circuit is provided for a plurality of semiconductor memory devices on a wafer, and a common input terminal and a common input / output terminal are provided in the test integrated circuit. Signals are exchanged between the probe needle and a plurality of semiconductor memory devices via the probe needle, so that a plurality of semiconductor memory devices can be simultaneously tested in parallel while maintaining the pin configuration of the conventional IC tester during a wafer test, which improves test efficiency. It has the effect of improving and simultaneously reducing the test cost.

In the present invention (claim 3),
The signal applied to the common input terminal of the test integrated circuit is simultaneously supplied to the corresponding input terminals (same pin number) of the plurality of memory ICs to be measured through the plurality of buffer circuits. A signal can be applied to a plurality of memory ICs to be measured by one driver pin and one probe needle. Further, since the memory IC to be measured has the data bit compression function in the test mode, the read data (for example, 8-bit data) is compressed into the 1-bit output from the predetermined test data terminal, and therefore the given data is given. The number of memory ICs that can be simultaneously tested is increased with respect to the total number of comparator pins of the IC tester, the number of probing operations is significantly reduced, the test time of the wafer test is shortened, and the test efficiency is remarkably improved.

[Brief description of drawings]

FIG. 1 is a plan view of a wafer according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a memory IC according to an embodiment of the present invention.

FIG. 3 is a plan view illustrating a wafer.

FIG. 4 is a diagram showing a configuration of a conventional memory IC.

FIG. 5 is a cross-sectional view of a probe card.

FIG. 6 is a diagram showing a configuration of a conventional semiconductor device.

[Explanation of symbols]

 1 Wafer 2 Memory IC 3 Common Input Terminal 4 Buffer Circuit 5 Input Terminal 6 Data Input / Output Terminal 7 Probe Card Board 8 Probe Needle 9 Semiconductor Device 10 Common Wiring 11 Common Input / Output Terminal 12 Virtual Large Capacity Memory IC Group 13 Test integrated circuit (test IC) 14 Common input / output terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/66 F 7735-4M

Claims (3)

[Claims] 1. At least one test integrated circuit having an input / output terminal and a buffer circuit on a wafer,
A plurality of semiconductor memory devices, and the input / output terminals of the plurality of semiconductor memory devices are electrically connected to the input / output terminals of the test integrated circuit so that the plurality of semiconductor memory devices are A semiconductor memory device configured to form a semiconductor memory device. 2. A semiconductor memory device having a data bit compression function in a test mode, wherein one test integrated circuit is provided for a predetermined number of semiconductor memory devices on a wafer, and the test integrated circuit comprises a plurality of test integrated circuits. A common input terminal and a plurality of common input / output terminals are provided, and at the time of a wafer test, signals are simultaneously distributed from the common input terminal to the same input terminals of the plurality of semiconductor memory devices. A semiconductor memory device, wherein each of the compressed data bit signals output from the semiconductor memory device is supplied to the common input / output terminal. 3. The test integrated circuit includes a plurality of buffer circuits, and signals input to one of the common input terminals are input to the plurality of semiconductor memory devices via the plurality of buffer circuits with the same input. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is supplied to a terminal.