JPH08102947A - Image signal coding method and image signal coding device - Google Patents

Abstract

PURPOSE: To attain smooth connection of a signal in response to arrangement by detecting a boundary between a non-coding block and a coding block and applying weighting to a signal in a boundary block to be detected. CONSTITUTION: An input image signal K11 is given to a block conversion circuit 11, in which signals are rearranged and a block signal K12 is outputted. The signal K12 is multiplied by a proper coefficient in the weighting circuit 12 in accordance with a kind of weighting and a position of a signal in a block to be a weighting block signal K13. The signal K13 is given to a DCT transformation circuit 13, in which the signal is DCT-transformed and quantized by a quantization circuit 14 to be a quantization conversion weight block signal K15. The signal K15 is given to the variable length coding circuit 15, in which variable length coding is implemented, the information quantity is smoothed in a buffer memory 16 and the result is given to a multiplexer circuit 20. The circuit 20 uses the memory 16 to multiplex a signal K17 with a prescribed information amount and a quantization step size signal K21, and the result is outputted.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 14 to 16) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 7) Actions (FIGS. 1 and 7) Example (1) Example 1 (FIGS. 1 to 6) (2) Second example (FIGS. 7 to 13) (3) Other examples Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal encoding method and an image signal encoding apparatus, and more particularly, to a remote location of an image by a transmission medium having a limited transmission capacity when transmitting or recording and reproducing the image signal. An image transmission device or a tape recorder / disc that uses a high-efficiency encoding method for efficiently compressing an image signal with a smaller amount of information, which is a device for transmission and recording / reproduction on a storage medium having a limited storage capacity. It is suitable to be applied to a recorder or the like.

[0003]

2. Description of the Related Art Conventionally, for coding an image signal, a coding method such as predictive coding for handling an image in pixel units, orthogonal transform coding such as discrete cosine transform (DCT), subband coding, There are band-division coding represented by the wavelet transform and block-coding methods in which the band-divided data is divided into blocks and handled. Predictive coding is easy to implement, but deterioration is easily perceived at high compression rates. Further, in a block coding method such as a subband code by DCT or block division or a wavelet transform, a relatively high image quality can be obtained even at a high compression rate by performing appropriate quantization for each block.

FIG. 14 shows an image signal coding device by block division. In this image signal encoding device, D
The image signal is coded by a coding method such as CT or the like orthogonal transform coding. Actually, the input image signal A11 is input to the block conversion circuit 101, rearranged, and then the block signal A11 is input.
It is output as 12. An example of this block conversion is shown in FIG.
Shown in The block signal A12 is a DCT conversion circuit (DC
T) 102, DCT-converted, and output as a conversion block signal A13. Conversion block signal A13
Is quantized by the quantization circuit (Q) 103 in accordance with the quantization step size A20 and becomes a quantization conversion block signal A14. The quantization step size A20 will be described later.

The quantized transform block signal A14 is input to a variable length coding circuit (VLC) 104, and is subjected to variable length coding in which, for example, a Huffman code and a run length code of zero coefficient are combined to perform variable length coding. Block signal A1
It becomes 5. The variable length coded block signal A15 is smoothed in the amount of information in the buffer memory 105, and the multiplexed circuit (M
UX) 106. The multiplexing circuit 106 multiplexes the smoothed variable length coded block signal A16, which has been converted into a constant amount of information by the buffer memory 105, and the quantized step size A20, and becomes the output A17 of the image signal coding apparatus.

On the other hand, the block attribute / activity calculation circuit 107 calculates and outputs a block attribute value or activity value A18 from the block signal A12. Here, both the block attribute value and the activity value are numerical values of the feature of the block, and for example, the sum of squares of the signals in the block, or the value mapped by an appropriate relational expression is used. The block attribute value or the activity value has a larger attribute value or a smaller activity value for a block having a higher importance, and has a smaller attribute value or a larger activity value for a block having a lower importance. The quantization control circuit 108 calculates the quantization step size A20 by referring to the block attribute value or activity value A18 of the block concerned and the accumulated information amount A19 of the buffer memory 105 arranged in the subsequent stage, and the quantization circuit 103 input.

There is also a case where there is no significant information in the block and it is not necessary to encode the block. At this time, the quantization circuit 103 is notified that the block is not encoded. In particular, when encoding not the original image signal but the inter-frame difference signal, for example, many blocks such as a block having almost no motion may not be encoded. In other cases, the quantization step size is generally larger when the amount of information stored in the buffer memory 105 is large and the block attribute value A18 is small and the importance is low or the activity value A18 is high. To roughen.

In the image signal decoding apparatus shown in FIG. 15, the input data B11 is input to the shunt circuit (DMUX) 121, and the variable length coded block signal B12 and the quantization step size B18 are separated. The variable-length coded block signal B12 is immediately input to the buffer memory 122, and then input to the variable-length decoding circuit (IVLC) 123 to be variable-length decoded and reconstructed quantization conversion block signal B12.
It becomes 14. The restored quantization conversion block signal B14 is input to the inverse quantization circuit (IQ) 124, and the quantization information B18 is input.
Is inversely quantized to become a reconstructed conversion block signal B15. The restoration conversion block signal B15 is subjected to inverse DCT conversion by the inverse DCT conversion circuit (IDCT) 125 and becomes a restoration block signal B16. Restoration block signal B16
Is converted by the block inverse conversion circuit 126 into the restored image signal B1.
7, which is the output of the image signal decoding device.

[0009]

By the way, in the image signal coding method in which the image is block-divided and coded in this way, as described above, it is possible to use other control signals such as attribute values and activity values for each block. When the coding block is controlled and the coding block and the non-coding block coexist, there is a problem that visually apparent block distortion occurs at the boundary between the coding / non-coding block and the image quality is greatly deteriorated. Further, as described above, when the encoding is controlled by the attribute value for each block, the activity value, and other control signals, if the control signal changes greatly locally, encoding with different properties compared to the surrounding part is performed. As a result, the amount of generated information may fluctuate greatly, and there is a problem that visually apparent block distortion occurs and the image quality is greatly impaired.

The present invention has been made in consideration of the above points, and an image signal encoding method and an image signal encoding apparatus capable of effectively suppressing block distortion when an image is divided into blocks and converted and encoded. Is to propose.

[0011]

In order to solve such a problem, in the present invention, the input image signal (K11) is divided into a plurality of blocks (K12), and the block (K1) is divided.
2) It is determined whether the coded or non-coded for each block, and the block (K1
2) In the image signal coding method in which conversion coding is performed in units, a boundary block detection step for detecting a boundary between a non-coded block and a coded block, and a signal in the detected boundary block are weighted. A weighting step to be performed is provided.

In the present invention, the input image signal (M
11) is divided into a plurality of blocks (M12), the attribute (M18) of each block (M12) is evaluated, and the image signal to be converted and encoded in block (M12) units according to the attribute (M18) In the encoding method, the block (M
12) An area dividing step for dividing the screen into a plurality of areas and an area shape adjusting step for adjusting the shape of the divided area are provided according to the attribute (M18) of each.

In the present invention, the input image signal (K
11) is divided into a plurality of blocks (K12), the coding or non-coding is judged for each block (K12), and the non-coding is performed in the image signal coding apparatus for transform coding in the unit of block (K12). A boundary block detecting means (18) for detecting the boundary between the encoded block and the encoding block and a weighting means (12) for weighting the signal in the detected boundary block are provided.

In the present invention, the input image signal (M
11) is divided into a plurality of blocks (M12), the attribute (M18) of each block (M12) is evaluated, and the image signal to be converted and encoded in block (M12) units according to the attribute (M18) In the encoding device, the block (M
Area dividing means (48) for dividing the screen into a plurality of areas according to the attribute (M18) for each 12) and area shape adjusting means (48) for adjusting the shape of the divided areas are provided.

[0015]

In the mixed state of the coded block and the non-coded block, the part where the block distortion occurs is grasped, and the signal in the coded block existing at the boundary with the non-coded block is adjacent to the block. By weighting according to the arrangement state, the signals can be smoothly connected according to the arrangement state, and visual block distortion is reduced. Further, by performing this weighting before the transform coding, the level of the signal to be coded becomes small, and the amount of coded information decreases.

Further, by detecting an area where the attribute changes greatly locally and adjusting the attribute of the block having the local change to the adjacent block, the fluctuation of the coding characteristic for each block is reduced, and the characteristic of the surrounding area is reduced. It becomes possible to control the encoding so that different encodings are not performed.

[0017]

An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment FIG. 1 shows a first embodiment of an image signal coding apparatus by block division according to the present invention. This image signal encoding device corresponds to the image signal encoding device described above with reference to FIG. In this image signal encoding device, the input image signal K11 is input to the block conversion circuit 11, rearranged and output as a block signal K12. This block conversion is the same as in FIG. 16 described above for the conventional technique. The block signal K12 is multiplied by an appropriate coefficient in the weighting circuit 12 according to the weighting type and the position of the signal in the block by a weighting instruction signal K19, which will be described in detail later, and becomes a weighted block signal K13.

The weighting block signal K13 is input to the DCT conversion circuit (DCT) 13, DCT-converted, and output as a conversion weighting block signal K14. The transform weighting block signal K14 is quantized by the quantizing circuit (Q) 14 according to the quantizing step size K21 to become a quantized transform weighting block signal K15. The quantization step size K21 is the same as that of the conventional image signal coding apparatus described above with reference to FIG.

Quantization transform weighted block signal K15
Is input to the variable length coding circuit (VLC) 15 and is subjected to variable length coding in which, for example, a Huffman code and a run length code of zero coefficient are combined to form a variable length coded block signal K16. The variable length coded block signal K16 has its information amount smoothed by the buffer memory 16 and is input to the multiplexing circuit (MUX) 20. The multiplexing circuit 20 multiplexes the smoothed variable-length coded block signal K17, which has been converted into a constant amount of information by the buffer memory 16, and the quantized step size K21, and outputs the output K of the image signal coding apparatus.
22.

On the other hand, the block activity calculation circuit 17
Calculates and outputs a block activity value K18 from the block signal K12. The definition of block activity is the same as the conventional one. The quantization control circuit 19 calculates the quantization step size K21 by referring to the block activity K18 of the block concerned and the accumulated information amount K20 of the buffer memory 16 arranged in the subsequent stage to calculate the quantization step size K21.
Enter in 4. The block activity K18 is input to the coding pattern detection circuit 18. The coded pattern detection circuit 18 identifies a block that is not coded from the activity, detects a coded / non-coded pattern of an adjacent block of each block, and weights the block in accordance with the pattern. For outputting the weighting instruction signal K19.

The positional relationship between each block and the adjacent block is shown in FIG. The block X in the center is the block of interest, and the weighting is determined by checking the arrangement of the coded / non-coded blocks of the eight blocks A to H around it. Here, the coding pattern detection circuit 18 including the weighting circuit 12 is shown in FIG. Input activity signal L1
1 corresponds to the block activity K18 of FIG. 1 and is input to the encoding flag calculation circuit 31. The coding flag calculation circuit 31 determines whether or not to code the block, sets the coding flag signal L12 to "1" for the coding block, and codes for the non-coding block. The flag signal L12 is set to "0".

To determine the coding block from this activity, an evaluation standard as shown in FIG. 4, for example, is used. The encoded flag signal L12 is 16 lines by the 2-block line delay circuit 32, 8 lines by the 1-block line delay circuit 35, and the block delay circuits 33, 3.
Nine signals L1 delayed by one block by 4, 36, 37, 38, 39 and having a positional relationship as shown in FIG.
2, L13, L14, L15, L16, L17, L1
8, L19, L20. Flag signals L12, L1
3, L14, L15, L16, L17, L18, L1
9 and L20 are blocks H, C, B, A, E, and
Encoding flags corresponding to the positions of X, D, G, and F.

Since there are eight blocks adjacent to one block, there are 2 ⁸ combinations to describe the coding / non-coding pattern, and it takes time to classify and is not realistic. Therefore, if one block is divided into appropriate sub-blocks and the number of external blocks adjacent to each sub-block is, for example, 3 or less, 2 ³ = 8
All patterns can be described in street combinations. In the case of a rectangular block, if it is divided into four sub-blocks as shown in FIG. 2, the pattern of the outer block adjacent to each sub-block becomes three combinations of top or bottom, left or right, and diagonal. At this time, in each sub-block, one of the four weighting patterns 1 to 4 shown in FIG.
By combining the two, it is possible to correspond to the patterns of all adjacent blocks.

Although only the sub-block S among the four sub-blocks S is shown in FIG. 5, the weighting patterns of the other sub-blocks P to R may be aligned with each other. FIG. 6 shows the selection of the weighting pattern for each subblock in the coding block according to the combination of the coding flags of the adjacent blocks A to H. For example, when A, B, D, and F are uncoded blocks among the adjacent blocks A to H, the sub-block P is pattern 4, the sub-block Q is pattern 2, the sub-block R is pattern 1, and the sub-block S is No weighting (all original values remain unchanged).

Returning to FIG. 3 again, the delay coding flag signals L12, L13, L14, L15, L16, L17,
L18, L19, and L20 are input to the state comparison circuit 40 composed of a ROM or the like and become the weighting pattern selection signal L21 for each subblock. The weighting pattern selection signal L21 corresponds to the weighting instruction signal K19 shown in FIG. 1 and is input to the weighting coefficient generation circuit 42 composed of a ROM or the like. The weighting coefficient generation circuit 42 outputs a weighting coefficient L23 corresponding to each pixel signal in the block from the weighting pattern selection signal L21 and the counter value L22 of the block counter 41.

On the other hand, the input block signal L24 corresponds to the block signal K12 in FIG. 1, is delayed by 2 block lines and 1 block by the delay circuit 43, and is delayed by the timing corresponding to the weighting coefficient L23.
25. The delayed block signal L25 has a weighting factor L
It is multiplied by 23 to obtain the weighted block signal L26. This weighted block signal L26 corresponds to the weighted block signal K13 in FIG.

According to the above configuration, the portion where the block distortion is generated is grasped from the mixed state of the coded block and the non-coded block, and the arrangement state of the adjacent block with respect to the signal in the coded block. By combining the weights of the two, the coded block signal is smoothly connected to the non-coded block at the boundary between the coded block and the non-coded block that causes block distortion, and visual block distortion is reduced. Thus, the quality of the restored image can be improved.

Further, by performing the weighting before the transform coding, the level of the signal to be coded is reduced, so that the coded information amount is reduced and the information amount to be transmitted or stored can be saved, thus improving the coding efficiency. This can be remarkably improved, and since the processing block is further divided into a plurality of sub-blocks for processing, the entire circuit configuration and the ROM used for selection can be simplified.

(2) Second Embodiment FIG. 7 shows a second embodiment of the image signal coding apparatus by block division according to the present invention. This image signal encoding device corresponds to the image signal encoding device described above with reference to FIG. In this image signal encoding device, the input image signal M11 is input to the block conversion circuit 41, rearranged and output as the block signal M12. This block conversion is the same as in FIG. 16 described above for the conventional technique. The block signal M12 is delayed by the delay circuit 42 in accordance with the calculation time of the encoding parameter, and becomes the delayed block signal M13. Delayed block signal M13 is D
It is input to the CT conversion circuit (DCT) 43, DCT-converted, and output as a conversion block signal M14.

The transform block signal M14 is quantized by the quantizing circuit (Q) 44 according to the quantizing step size M21 to become a quantized transform block signal M15. The quantization step size M15 is the same as the conventional one. The quantized transform block signal M15 is input to a variable length coding circuit (VLC) 45 and subjected to variable length coding in which, for example, a Huffman code and a zero coefficient run length code are combined to perform a variable length coded block signal. It becomes M16. The variable length coded block signal M16 has its information amount smoothed by the buffer memory 46, and the multiplexed circuit (MUX) 5
Input to 0. The multiplexing circuit 50 multiplexes the smoothed variable-length coded block signal M17 whose constant information amount has been converted by the buffer memory 46 and the quantized step size M21 into an output M22 of the image signal coding apparatus.

On the other hand, the block attribute value calculation circuit 47 calculates a block attribute value M18 from the block signal M12 and outputs it. The definition of the block attribute value is the same as the conventional one. The block attribute value correction circuit 48 inputs the block attribute value M18 of the block, divides the region from the distribution of the block attribute value, corrects the local variation of the region shape and the attribute value,
The modified block attribute value M19 is output. The quantization control circuit 49 uses the modified block attribute value M19 of the block and the accumulated information amount M20 of the buffer memory 46 arranged in the subsequent stage.
, The quantization step size M21 is calculated and input to the quantization circuit 44.

Next, FIG. 8 shows a first configuration of the block attribute value correction circuit. The input attribute value N11 corresponds to the block attribute value M18 in FIG. 7, and is input to the attribute value pattern memory 51. The attribute value pattern memory 51 is a memory for sequentially storing the attribute value of each block. The temporarily stored attribute value signal N12 is supplied to the adjacent attribute value detection circuit 52.
Is input to the isolated area detection circuit 53. The adjacent attribute value detection circuit 52 determines the mode value of the attribute values of 4 to 8 adjacent blocks from the attribute values of adjacent blocks in the 4 to 8 directions around the block as the adjacent attribute value N13. The positional relationship between each block and the adjacent block is shown in FIG.

The block X in the center is the block of interest,
The area is determined by comparing the attribute values of eight surrounding blocks A to H. Blocks in all eight directions are adjacent to each other, and block A touching at only one point,
Blocks in four directions excluding C, F, and H may be considered to be adjacent to each other. The isolated area detection circuit 53 checks from the attribute values of the eight blocks A to H whether or not the block is isolated on the attribute value, and if it is isolated, sets the isolated flag N14 to "1". If not isolated, "0" is set.

The input attribute value N11 becomes the delay original attribute value N15 by appropriately adjusting the timing in the delay circuit 54. The isolated block comparison circuit 55 selects the delay original attribute value N15 and the adjacent attribute value N13 according to the value of the isolated flag N14. If the isolated flag N14 is "0", it is not an isolated block and the delay original attribute value N15 is output. If the isolated flag N1 is "1", it is an isolated block and therefore the adjacent attribute value N13 is output, and the modified attribute value N16 is output. This modified attribute value N16
Corresponds to the modified block attribute value M19 in FIG.
The isolation of a certain area here means a state such as A or B shown in FIG. 11, for example. In addition to the area of only one block, the area of multiple blocks
It may be considered to be isolated from the surrounding state.
The maximum number of isolated regions is a balance between the application purpose and the circuit scale.

Here, the configuration of this isolated area detection circuit is shown in FIG.
Shown in The input attribute value P11 is the input attribute value N12 of FIG.
16 blocks by the 2 block line delay circuit 61, 8 lines by the 1 block line delay circuit 64, and block delay circuits 62, 63, 65, 6
Each of the six signals 67, 68 is delayed by one block, and the nine signals P11, P having the positional relationship shown in FIG.
12, P13, P14, P15, P16, P17, P1
8, P19. Attribute value signals P11, P12, P1
3, P14, P15, P16, P17, P18, P19
Are attribute values of blocks corresponding to positions H, C, B, A, E, X, D, G, and F, respectively.

These signals are input to the state comparison circuit 69 composed of a ROM or the like, and it is checked whether or not the block X is isolated, and the isolated flag P20 is output. The isolated flag P20 corresponds to the isolated flag N14 in FIG. As the configuration of the state comparison circuit 69, for example, P1
If all eight attribute values of P11 to P19 other than 6 are different from the attribute value P16 of the block, it is considered to be isolated and the isolated flag P20 is set to "1". If only the blocks touching with a line are targeted, P
If all four attribute values of 13, P15, P17 and P18 are different from the attribute value P16 of the block, it is considered to be isolated and the isolation flag P20 is set to "1".

Next, FIG. 12 shows a second configuration of the block attribute value correction circuit. The input attribute value Q11 corresponds to the block attribute value M18 of FIG. 7, and is stored in the first memory (RAM1) 71 by the address Q12 according to the order of blocks generated by the address counter 72. First
The attribute value matrix stored in the memory 71 is read by the arithmetic circuit (CPU) 73 through the bus Q13, and the area division, area area calculation, and adjacency are performed in accordance with the block attribute value correction processing procedure shown in FIG. Each processing of area comparison and attribute value correction is performed and stored in the second memory (RAM2) 75 through the bus Q13. This procedure is stored in the program memory (ROM) 74 and is executed by the arithmetic circuit 73.

The modified attribute value matrix stored in the second memory 75 is sequentially output as the modified attribute value Q15 by the address Q14 according to the order of the blocks generated by the address counter 76. This modified attribute value Q15
Corresponds to the modified block attribute value M19 in FIG.
In the first configuration of the block attribute value correction circuit described above with reference to FIG. 8, only a region consisting of only one block can be recognized as an isolated region, but in the second configuration, the area of each region is calculated. For example, it is also possible to detect a small area composed of an appropriate arbitrary number of blocks or less.

According to the above configuration, the area where the attribute largely changes locally is detected, and the local change is smoothed,
By controlling the encoding so that encoding with different characteristics from the surrounding parts is not performed, it is possible to suppress local changes in the block attributes that cause block distortion, and to reduce visual block distortion. It is possible to obtain a restored image of higher quality by reducing the number of images.

By merging small regions having locally different attributes into adjacent larger regions, the total number of divided regions having the same attribute is reduced, and each region must be coded. Attribute data is also reduced, and the amount of information to be transmitted or stored can be saved. Further, since the variation of the coding characteristic for each block is reduced, the difference in image quality deterioration within or between images becomes inconspicuous. In addition, the control of the amount of generated information is simplified, and the load on the transmission or storage medium can be reduced.

(3) Other Embodiments In the above embodiment, the case where the input image is divided into 8 × 8 square blocks and encoded is described.
This size may be, for example, a block having an appropriate arbitrary size, or may be an arbitrary shape in consideration of image characteristics and the like. Even in that case, if each block is divided into a plurality of sub-blocks, the circuit configuration and the contents of the ROM can be simplified.

In the above embodiment, the coding flag is determined based on the activity calculated from the input image signal, but instead of this, for example, the amount of accumulated information that is fed back is used, and edge detection and edge detection are performed. It is also possible to consider the result of different pre-processing such as pattern recognition. Although an example in which the weighting coefficient is set according to a linear change is shown, an application such as a setting according to a sine function change or a setting according to a logarithmic function change can be considered.

In the above embodiment, the processing for the coding block at the non-coding boundary has been described, but conversely, the same processing is performed for the non-coding block at the boundary with the coding block. It is also possible to do it. In that case, conversely, a weighting shape is considered such that it is lifted closer to the boundary.

In the above embodiment, the case where the DCT in block units is used as the image signal encoding method has been described, but a method using orthogonal transform such as Haar transform or vector encoding in block units may also be used. Conceivable.

Also, in this first embodiment, only 1
Although only the area consisting of only one block is the isolated area, by increasing the scale of the delay circuit and the comparison circuit,
It is also possible to detect areas consisting of two or more blocks. Further, in these embodiments, the example in which the attribute value of the adjacent area is used as the correction value of the attribute value has been described, but a value such as an average of the attribute value of the area and the attribute value of the adjacent area may be used.

[0047]

As described above, according to the present invention, the portion where the block distortion occurs is grasped from the mixed state of the coded block and the non-coded block and exists at the boundary with the non-coded block. By weighting the signals in the coding block according to the arrangement of adjacent blocks, signals can be connected smoothly according to the arrangement, and visual block distortion can be reduced. Also, by performing the weighting in the preceding stage of the transform coding, the level of the signal to be coded becomes small, and the image signal coding method and the image signal coding apparatus that reduce the amount of coded information can be realized.

Further, according to the present invention, a region having a small area having an attribute different from that of an adjacent region is detected by dividing the region into a plurality of regions which are in contact with each other and have the same attribute. By merging the area area with the adjacent area, it is possible to detect the area where the attribute greatly changes locally, and by matching the attribute of the block with the local change to the adjacent block, the coding characteristics of each block can be changed. It is possible to realize an image signal coding method and an image signal coding apparatus capable of performing coding control so that fluctuations are reduced and coding having characteristics different from those of the peripheral portion is not performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an image signal encoding device to which an image signal encoding method and device according to the present invention are applied.

FIG. 2 is a schematic diagram for explaining the positional relationship between adjacent blocks in the detection process of the arrangement pattern of encoded / non-encoded blocks in the image signal encoding apparatus of FIG.

3 is a block diagram showing a configuration of a coding pattern detection circuit in the image signal coding apparatus of FIG.

FIG. 4 is a characteristic curve diagram showing a configuration of an evaluation standard for determining an encoding block from a block activity in the encoding pattern detection circuit of FIG.

5 is a schematic diagram showing the shape of block weighting in the coding pattern detection circuit of FIG. 3;

6 is a chart showing the configuration of a sub-block weighting pattern determination method in the coding pattern detection circuit of FIG.

FIG. 7 is a block diagram showing a configuration of a second embodiment of an image signal encoding device to which an image signal encoding method and device according to the present invention are applied.

FIG. 8 is a block diagram showing a first configuration of a block attribute value correction circuit of the image signal encoding device of FIG.

9 is a block diagram showing a configuration of an isolated area detection circuit of the block attribute value correction circuit of FIG.

FIG. 10 is a schematic diagram for explaining the positional relationship between adjacent blocks.

FIG. 11 is a schematic diagram for explaining an isolated area determined in isolated area detection.

12 is a block diagram showing a second configuration of the block attribute value correction circuit of the image signal encoding device in FIG. 7. FIG.

13 is a flow chart showing a block attribute value correction processing procedure in the block attribute value correction circuit of FIG.

FIG. 14 is a block diagram showing a configuration of a conventional example of an image signal encoding device by block division.

FIG. 15 is a block diagram showing a configuration of a conventional example of an image signal decoding device by block division.

FIG. 16 is a schematic diagram showing a configuration of a processing block in image signal coding by block division.

[Explanation of symbols]

11, 41 ... Block transform circuit, 12 ... Weighting circuit, 13, 43 ... DCT transform circuit (DCT), 14,
44 ... Quantization circuit (Q), 15, 45 ... Variable length coding circuit (VLC), 16, 46 ... Buffer memory, 1
7 ... Block activity calculation circuit, 18 ... Encoding pattern detection circuit, 19, 49 ... Quantization control circuit,
20, 50 ... Multiplexing circuit (MUX), 47 ... Block attribute value calculation circuit, 48 ... Block attribute value correction circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04N 1/41 B G06F 15/66 330 J

Claims (20)

[Claims] 1. An image signal coding method in which an input image signal is divided into a plurality of blocks, coding or non-coding is determined for each block, and conversion coding is performed in block units. An image signal coding method characterized by comprising a boundary block detection step for detecting a boundary between the block and the coding block, and a weighting step for weighting a signal in the detected boundary block. . 2. The boundary block detection step includes a sub-block division processing step for dividing the block into a plurality of sub-blocks, and for each of the sub-blocks, the determination of the coding pattern or the non-coding layout pattern of adjacent blocks is independently performed. The image signal encoding method according to claim 1, further comprising an encoding determination step to be performed. 3. The sub-block division processing step divides the sub-blocks adjacent to all the sub-blocks so that the number of adjacent blocks is three or less. Image signal encoding method. 4. The image signal coding method according to claim 2, wherein the weighting step independently weights each of the plurality of subblocks. 5. The image signal coding method according to claim 1, wherein the weighting step is performed as a pre-process for coding the block. 6. An image signal encoding method for dividing an input image signal into a plurality of blocks, evaluating the attribute of each block, and transform-encoding in block units according to the attribute, in each block. An image signal encoding method, comprising: an area dividing step for dividing a screen into a plurality of areas according to the attribute of 1. and an area shape adjusting step for adjusting the shape of the divided area. 7. The area division step comprises a block connection step for sequentially connecting the blocks having the same attribute that are in contact with each other to form the area, and an attribute of each block belonging to the area as an attribute of the area. 7. The image signal coding method according to claim 6, further comprising a region attribute determining step. 8. The area shape adjusting step comprises an area merging determination step for merging the area into an adjacent area and an area merging processing step for merging with the adjacent area. The image signal encoding method according to claim 6. 9. The area merge determination step detects an arrangement pattern of adjacent blocks surrounded by areas having different attributes and having the same attribute, and compares the attribute of the area with the attribute of the adjacent area. The image signal encoding method according to claim 8. 10. The image signal encoding method according to claim 7, wherein the block connection step is for a block which is in contact with the target block at a line or a point. 11. An image signal coding apparatus for dividing an input image signal into a plurality of blocks, determining coding or non-coding for each block, and transform-coding in block units. An image signal coding apparatus comprising: a boundary block detecting means for detecting a boundary between the block and the coding block; and a weighting means for weighting a signal in the detected boundary block. . 12. The boundary block detecting means independently divides the block into a plurality of subblocks, and determines the coding pattern or non-coding layout pattern of adjacent blocks independently for each subblock. The image signal coding apparatus according to claim 11, further comprising: a coding determination unit that performs the coding. 13. The sub-block division processing means divides the blocks adjacent to the block so that the number of adjacent blocks to all sub-blocks is 3 or less. Image signal encoding device. 14. The image signal coding apparatus according to claim 12, wherein the weighting means independently weights each of the plurality of subblocks. 15. The image signal coding apparatus according to claim 11, wherein the weighting means performs preprocessing for coding the block. 16. An image signal coding apparatus for dividing an input image signal into a plurality of blocks, evaluating the attribute of each block, and transform-coding in block units according to the attribute, in each block. An image signal coding apparatus, comprising: an area dividing unit that divides a screen into a plurality of areas according to the attribute of 1. and an area shape adjusting unit that adjusts the shape of the divided areas. 17. The area dividing means comprises a block connecting means for sequentially connecting the blocks having the same attribute in contact with each other to form the area, and an attribute of each block belonging to the area as an attribute of the area. 17. The image signal encoding device according to claim 16, further comprising area attribute determining means. 18. The area shape adjusting means comprises area merging judging means for judging merging the area into an adjacent area, and area merging processing means merging with the adjacent area. The image signal encoding device according to claim 16. 19. The area merge determination means detects the arrangement pattern of adjacent blocks surrounded by areas having different attributes and having the same attribute, and compares the attribute of the area with the attribute of the adjacent area. The image signal encoding device according to claim 18. 20. The image signal coding apparatus according to claim 17, wherein the block connecting means targets a block which is in contact with the target block at a line or a point.