JPH08102746A - Exchange device, exchange method and semiconductor device - Google Patents

Abstract

PURPOSE: To parallelly switch plural data whose storage positions of the identification information of a transmission destinations are different from each other and to improve the exchange efficiency of lines by selecting the line of an identification number retrieved based on the position data of the frame and a required identifier and transmitting reception data. CONSTITUTION: When the data frame of a LAN line 152 is received, an NT 301 transfers a TYPE to an AP 102, selects a channel and sends out communication destination identification information through a DMAC 103. The AP 102 fetches it and generates interruption to a CPU 12h when it is registered and the CPU 121 reads a segment address from the address register of the AP 102, adds '1', writes it in the address register and specifies the port address of the data. Then, connection to an output port read from a memory register is set in an SEU 111, data transfer from the AP 102 to the SEU 111 is set in the DMAC 103 and the write of the data is performed to the SEU 111.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching apparatus, a switching method, and a semiconductor device which receive a data frame, search an output line associated with the data frame, and transfer the data frame to the searched output line. Regarding

[0002]

2. Description of the Related Art A switching device is, for example, an A in an ATM network.
DA in VPI and VCI of TM header, Ethernet type or IEEE802.3 data frame
(Destination address), DEST (destination address) included in the IP header of TCP / IP, the ISDN number of the other party in the ISDN line, etc. are used to determine the destination of the received data frame based on the data for identifying the destination, Transfer the received data frame.

In recent years, internetworking for connecting a plurality of networks to each other has been promoted. Therefore, it is considered that in the future, there will be an increasing demand for mixing data frames based on various protocols in a one-dimensional network such as a LAN, a telephone network, and a public data communication network.

However, since the position of the data for identifying the destination in the data frame based on each protocol is different, the data frame of each protocol cannot be mixed as it is on a single network. Therefore, conventionally, when transferring data frames of various protocols, the data frame is included in a cell of a single protocol such as an ATM cell, and the data frame is included in the data for identifying the destination of the cell. The data frame was transferred by storing the transmission destination of.

[0005]

However, when a data frame is included in a cell of another protocol such as an ATM cell, surplus data such as a header increases. Further, since the data for identifying the transmission destination of the cell needs to be stored with the transmission destination of the data frame, the load on the switching device increases.

On the other hand, since it is necessary to select the line to which the received frame is to be sent out at high speed, conventionally, it was not possible to mix data frames based on a plurality of protocols as they are and perform switching.

Therefore, an object of the present invention is to provide a switching device and a switching method capable of switching in parallel data frames based on a plurality of protocols in which the storage location of the identification information of the transmission destination is different.

[0008]

In order to achieve such an object, the invention described in claim 1 receives a data frame and sends the data frame to an output line associated with the data frame. In the switching device to transfer,
Storage means for storing the search data and the identification number of the line associated with the search data, position storage means for storing the position of the data to be captured inside the data frame, and data for the position in the data frame inside The fetching means for fetching, the search data position storing means for storing the position of the data used for searching the identification number in the fetched data, and the identification from the storing means based on the data of the position stored in the position storing means. It is characterized by comprising a semiconductor device having a searching means for searching a number and a transmitting means for transmitting the data frame from the line of the identification number searched by the semiconductor device.

A second aspect of the present invention is the exchange apparatus according to the first aspect, wherein the semiconductor device has a plurality of the position storage means and the search data position storage means, and each search data position. A storage means is associated with each position storage means, and the data used to select which position storage means and search data position storage means is used,
A location storage means for storing a location in the data frame, and a selection means for selecting which location storage means and search data location storage means to use based on the data of the location in the data frame. It is characterized by having.

The invention according to claim 3 is the exchange apparatus according to claim 2, wherein at least one of the position storage means and the search data position storage means associated with the position storage means are: It is characterized in that the position of the data including the DEST of the IP is stored, and the search data position storage means stores the position of the TYPE of the Ethernet or SNAP.

According to a fourth aspect of the present invention, in the exchange method of receiving a data frame and transferring the data frame to the output line associated with the data frame, the retrieval data and the retrieval data are associated with each other. A location in the data frame of the data that stores the line identification number in advance, stores a plurality of data positions of data used for searching the identification number in the data frame, and selects which data position to use Stored in the storage means, select which data position to use based on the data of the location, retrieve the identification number from the storage means based on the data of the selected data location, and then use the line of the identification number. The data frame is transmitted.

[0012] The invention according to claim 5 is the exchange method according to claim 4, wherein at least one of the data positions is a data position including IP DEST, and the position is Ethernet or SNAP. It is a type place.

According to a sixth aspect of the present invention, storage means for storing the search data and output data associated with the search data, and position storage means for storing the position of the data to be captured inside the input data string are stored. A retrieval means for retrieving the retrieval data from the storage means based on the retrieval means for retrieving the data at the position in the input data string and the data at the predetermined position in the retrieved data. Means and an output means for outputting the output data associated with the retrieved search data. The invention according to claim 7 is the semiconductor device according to claim 6, which has a plurality of the position storing means, the fetching means, and the searching means, each fetching means and each searching means It is associated with the position storage means,
It is characterized by further comprising a selecting means for selecting which of the position storing means, the fetching means and the searching means to use. The invention according to claim 8 is the semiconductor device according to claim 7, wherein the selecting means stores the data associated with each position storing means, each fetching means, and each searching means. It is characterized in that when the selection data is inputted, the data storage means and the position storage means, the fetching means, and the search means associated with the inputted selection data are selected.

[0014]

According to the present invention, the switching device has the search data and the line identification number associated with the search data, the data position of the data used to retrieve the identification number of the destination line in the received data frame, and Pre-store the location in the data frame of the data used to select which data position to use, when receiving the data frame, based on the data at that location, select which data position to use, The identification number is searched based on the data of the selected data position, and the data frame received from the line of the searched identification number is transmitted.

As an example, at least one data location is the location of the data containing the IP DEST and the location is the Ethernet or SNAP TYPE location.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[Embodiment 1] (1) Configuration of network system In FIG. 1, 10 is an ATM network, and 11 to 17 are ATM exchanges. Reference numeral 21 is a terminal for transmitting and receiving ATM cells. Reference numerals 31 and 32 are IWUs as an example of the exchange apparatus of the present invention.
(Inter Working Unit), a data frame received from a LAN using TCP / IP is converted into an ATM cell and transmitted to the ATM network 10, and an ATM cell received from the ATM network is converted into a TCP / IP data frame. And send it to the LAN. 22, 23, and 44 to 49 are L
It is an AN terminal.

(2) Hardware Configuration of Switching Device FIG. 2 is a hardware block diagram of the IWU 32.
The IWU 31 has a similar configuration. In FIG. 2, 30
1 is a network terminator (NT), ATM
Isolation between the line 150 or the LAN line 152 and the device, serial / parallel conversion, and data buffering are performed. The NT 301 has a CPU bus and a data transfer bus. The CPU bus is connected to the CPU 121.

Reference numerals 101 and 102 denote address processors (AP) as an example of the semiconductor device of the present invention, which searches for input data and outputs a search result in accordance with a preset sequence. AP 101 is connected to NT on the ATM line side, and AP 102 is connected to NT on the LAN line side. In this embodiment, NT301
To Switching element unit (SEU) 111
Address processor (A
P) 101 and 102 are used. The data output from the SEU 111 can be transferred to the DMA without passing through the APs 101 and 102.
It is directly transferred to NT301 by C103.

Reference numeral 103 denotes a direct memory access controller (DMAC), which is NT301, AP10.
Data is transferred between the first and second switching elements unit (SEU) 111. DMAC
103 has a CPU bus and a data transfer bus, and the CPU bus is connected to the CPU 121. The data transfer bus is connected to the data transfer bus of NT301, the input and output ports of AP102, and the port of SEU111.

The SEU 111 has a plurality of data ports (single
Control port) and one control port
Connect the ports according to the data input from the ports.
You. Reference numeral 121 denotes a CPU that controls the entire exchange apparatus, and 122
Is an RO that stores programs executed by the CPU 121.
M and 123 are RAMs. 124 is a timer (TIM
ER), and to the CPU 121 at every set time.
To interrupt. 125 is various equipment for the exchange device.
It is an input device that inputs constants, etc., typically a keyboard
And mouse. 126 is a replacement device
It is a display device that displays an operating state and the like. 160 is the net
Lines 150 and 152 by the work terminator 301
Data bus isolated from. 170 is a CPU bus
Is. (3) Configuration of address processor (AP) As an example of the semiconductor device of the present invention, FIG.
The hardware configuration of P102 will be described. This device
As with many programs,
Can be easily produced and used by those skilled in the art.
It can be done. So, the port configuration of this device,
Specifications such as CAM array configuration and register configuration
Details are given below. The configuration of AP 101 is AP 102.
The configuration is the same as that of.

(3-1) Port Configuration As shown in FIG. 3, the AP 102 has an input port (INPUT PO
It has an RT) 210, an output port (OUTPUT PORT) 220, and a CPU port 230.

(3-1-1) Input Port The input port 210 is a port for inputting search key data. The port width is 32 bits but can be set so that only 16 or 8 bits are valid. The data (ID: 0 to 31) needs to be input in synchronization with the WR pulse. The extreme positive of WR can be set to positive logic or negative logic.

In FIG. 3, the IPB of the input port 210
The USY terminal is a terminal that outputs a signal indicating whether data can be input to the input port, and outputs LOW when another port (output port or CPU port) is operating and does not accept data input to the input port. To be done.

The input data input to the input port 210 is combined (compounded) by the data formatter 211 in accordance with a pre-defined input port sequence to become 32-bit data (comparand data). Processing such as search is performed according to the comparand data.

(3-1-2) Output Port The output port (OUTPUT PORT) 220 is a port for outputting data such as search results. The data width is 32 bits, but it can also be set so that only 16 or 8 bits are valid. Output data (OD) is output by inputting a LOW pulse (RD pulse) to the RD terminal of the output port 220 while LOW is input to the OE terminal of the output port 220.

The OPBUSY terminal of the output port 220 is
It is a terminal that outputs a signal that indicates whether or not data can be output from the output port, and the other port (input port or CPU
Port) is operating and data cannot be output from the output port, LOW is output.

(3-1-3) CPU Port The CPU port is a 16-bit input / output data bus for interfacing with the host processor. Data width is 1
It has 6 bits and an address width of 8 bits. The address is
It is used to specify the addresses of various registers in the AP. The following operations can be performed from the CPU port.

(3-1-3-1) Reading / Writing Registers Data can be written in and read from various registers inside the chip.

(3-1-3-2) Writing to and reading from the CAM table
This is done via access to the R, Memory_HHA, and Memory_HEA registers.

(3-1-3-3) Execution of various commands Execution of commands is performed by writing execution commands in the command register. For example, when a search execution instruction is written, the AP 102 does not require CPU intervention,
Input data from the input port and output the result from the output port according to the defined sequence. The definition of the search condition performed before writing the search execution instruction is also the CPU bus 2
Start from 30.

(3-1-3-4) Search A search can also be performed via the CPU port. The command is executed by writing an operation code in the IP command register.

(3-2) Structure of CAM Array The CAM array 250 has 2048 basic CAM words shown in FIG. In FIG. 4, empty bit 2
51 indicates whether or not valid table data is written in the word. Set to 0 when valid data is being written. The hit / miss hit flag 255 indicates whether or not the search result is a hit.
The access bit 256 indicates whether or not there is a hit or a miss hit in the past search.

The logical configuration of the CAM array 250 will be described with reference to FIG. As shown in FIG. 5, the CAM array 25
0 has a logical configuration of row (horizontal row in FIG. 5) × column (vertical column in FIG. 5). The row and column sizes are shown in Figure 5.
Is defined by the segment number bit 253 and the boundary bit 252 of the. These bits are AP10
2 is pre-written before starting execution.

The segment bits shown in FIG. 4 are 3 bits, and the value of 000 to 111 indicates the segment number. The segment number represents the position in the column direction. If the segment bit value is from 000 words to 111 words, the table column size is 8, and if the segment bit 253 value is only 000 words, the table column size is 1. . Thus, the column size of the table is defined by the value written in the segment bit.

A word with a segment bit of 000 indicates that a new row in the CAM table begins.
1 is written in the boundary bit (see FIG. 4) of this word. The column size n and the row size m of the CAM table must satisfy n × m ≦ 2048. The remaining words defined by 2048-nxm cannot be used. Search is
Do this for each column of the table. One segment 254 in the same column is used by using one comparand data.
Refer to times.

When the definition of the table is completed, the segment 254 of each basic word is transferred to the segment 254 of each basic word via the CPU port 230.
You can write data. The CPU port 2 determines whether the data written in each segment is used as search data (key data) and whether it is used as target data to be output when the search hits.
It is defined by the CPU 121 via 30. The data written in each segment can be used as both key data and target data. Also, a different number of segments for each column can be used as search data or target data. C after power on
Since the values in the AM table are indefinite, the CAM table is set by writing the boundary bits in all the segments (2048 segments) of the CAM.

(3-3) Register Configuration AP 102 is a control register, CUT register, SEARCH register, HHA register, 16 comparand registers, 16 CS registers, 16 mask registers, 32 AOC registers. , 32 AOSC registers, A channel selection register, B channel selection register, and address register. C
The S register and the mask register are divided into 8 channels each for A channel and B channel. The AOC register and the AOSC register are divided into 16 A channels and 16 B channels.

The data width of the input data is set by the control register. Input data used for search is set by the CUT register. The SEARCH register sets the condition for executing the search. The HHA register has
The address of the hit CAM data is stored. 16
Up to 16 comparand data are stored in each comparand register. Arbitrary comparand data stored in the comparand register can be stored in any word in the CAM array by an append instruction from the CPU port. 16 CS registers,
Set the number of bytes to shift comparand data when performing each search. The masked bits of each comparand data are set in the 16 mask registers.

The 16 AOC registers of each channel set the sequence of output data. That is, the output data set in the 1st to 16th AOC registers are sequentially output from the output port. When it is defined that the CAM table data is output by the AOC register, the segment number of the CAM table to be output is set by the AOSC register corresponding to the AOC register. The A channel selection register and the B channel selection register store data used for selecting the A channel and the B channel, respectively. The address register sets the address of the CAM accessed from the CPU port. The setting contents of these registers are
"(3-4) How to set the input sequence" and "(3-5
) Output sequence setting method ".

(3-4) Input Sequence Setting Method Two types (A channel and B channel) of data input sequences (capture of data on input port, masking of comparand data, etc.) should be set in the AP 102. Can be done.

The maximum input sequence of each channel is 64.
It can be set for each input data. Up to 6
Which of the four pieces of input data is taken into the AP is set by the 64-bit CUT register. That is, each bit of the CUT register is made to correspond to each input data, 1 is set to the bit corresponding to the fetched data, and 0 is set to the bit corresponding to the non-fetched input data.

The 16-bit and 8-bit input data are combined (compounded) in the AP and treated as a maximum of 16 32-bit width data (called comparand data). 32-bit input data is 32 as is
Handled as bit-width comparand data. The comparand data is stored in 16 comparand registers.

The maximum amount of data that can be used for a search by the input sequence of one channel among the data taken in the comparand register is the maximum column size of the CAM table, that is, eight. Therefore, when the effective input data width is 32 bits, 16 bits, and 8 bits, 8, 16, and 32 pieces of input data can be used for the search, respectively.

The input data set when taken into the AP by the CUT register is sequentially A-synchronized with the WR pulse.
It is stored in the accumulation buffer of P102.
64-bit SEAR which input data should be searched when stored in the accumulation buffer
Set in CH register. That is, each bit of the SEARCH register corresponds to each of 64 input data, and the bit of the SEARCH register corresponding to the input data to be searched is set to 1. The search can be executed even when the 4-byte data is not stored in the comparand register. In this case, the value of the comparand data of the field in which no data is input is set to 0.

When executing the search, 1 to 3 bytes of the input data stored in the previous comparand register can be shifted to the comparand register to be searched. The number of bytes to be shifted when performing each search is set in the 2-bit shift amount field in the CS register. Further, the 3-bit segment designation field in the CS register is used to set the number of the segment in the CAM array to search for the input data. Eight CS registers are provided for each channel, and the shift amount and the segment to be searched can be set for each of the eight searches.
When the shift is not performed, the shift amount field is set to 0 as the default.

When a part of the comparand data is masked when executing the search, the bit corresponding to the bit to be masked in the mask register corresponding to the search is set to 0. Set 1 to the bits that are not masked. In the AP, the value of the masked bit is masked to 0 by calculating the logical product (AND) of the mask register value and the comparand data when executing the search.

The input sequence advances one by one by inputting a WR pulse. Also, LOW for the SQRST pin
The input sequence returns to the beginning by inputting a pulse or an SQRST command from the CPU port.

(3-5) Output Sequence Setting Method When the search is executed, the register address of the hit data in the CAM table (CAM table data that matches the input data) is stored in the HHA register. When a plurality of segments are searched by the AND condition of a plurality of comparand data, the lowest addresses of the plurality of hit segments are stored in the HHA register.

After executing the search, data can be output from the comparand register, the HHA register, and the CAM table to the output port. The output data and the output order are determined by the output sequence. Two output sequences (A channel and B channel)
Can be set. For each channel
The following settings can be made.

Which of the 16 comparand registers, the HHA register, and the data of the hit row in the CAM table is to be output is set to 16 AOs.
Set in each of the C registers. By setting the AOC register, the logical OR of the value of the comparand register and the value of the data of the hit row in the CAM table can be output. The data set in the first AOC register to the data set in the 16th AOC register are sequentially output from the output port. By setting the AOC register to output only the data of the comparand register, the data input to the input port 210 can be output from the output port 220 as it is.

The data of each segment of the hit row in the CAM table is irrespective of whether it is used for retrieval or not.
It can be output arbitrarily. The segment number of the output CAM table data is set in 16 AOSC registers associated with each of the 16 AOC registers. The output sequence advances one by one by the input of the RD pulse. Also, LOW for the SQRST pin
The output sequence returns to the beginning by inputting a pulse or an SQRST command from the CPU port.

(3-6) Execution of search When the SWIOP command is input after the search conditions have been set, the AP (AP) 102 is in the input / output mode (IOP).
Mode), and the search is executed according to the input from the input port 210. In this case, which of the A channel and the B channel is used for each of the input sequence and the output sequence is set by a command from the CPU port.

After setting the search conditions, SWIOP
When you enter the _SELECT command, AP (AP) 1
02 is an input / output mode with a channel selection condition (IOP_S
(ELECT mode). In this case, the initially input 32-bit data is compared with the values stored in the A channel selection register and the B channel selection register. If the initially input 32-bit data is the same as the value stored in the A channel selection register, the A channel is selected, and if it is the same as the value stored in the B channel selection register, the B channel is selected. Then input port 21
Perform a search on the selected channel according to the input from 0.

(3-7) Search from CPU Port Search data can also be input from the CPU port 210. The input search data is set in the CPU input register. If you then enter the SARCH command, A
P102 executes the search.

The search result can be output from the CPU port. The address of the hit CAM data is HH
Read from A register. The CAM data of the segment address set in the address register can be read by reading the Memory_AR register.

(4) Structure of Data Frame An ATM used on the ATM line 150 will be described with reference to FIG.
The data structure of the cell will be described. As shown in FIG. 6 (A), an ATM cell has a cell header of 5 octets and 48 octets.
It is composed of octet information fields. UNI (User Net) used between users and networks
work interface) and NN used between networks
The structure of the cell header in I (Network Network Interface) is shown in FIGS. 6 (B) and 6 (C).

In FIGS. 6B and 6C, the VPI
Is a virtual path identification, and VCI is a virtual channel identification. The VPI and VCI identify the destination of the cell. The values of VPI and VCI are usually set when an ATM connection is established and held until the ATM connection is released. PT is a payload type and indicates whether the information contained in the information field of the cell is user information or network information.

Ethernet type data frames or IEEE802.3 data frames are transmitted on the LAN line 152. FIG. 7 shows the data structure of the Ethernet type data frame, and FIG. 8 shows the structure of the IEEE802.3 data frame. 7 and 8,
TYPE indicates the protocol of data stored in the DATA field of each data frame. By TYPE,
For example, protocols such as IP, ARP, and ICMP are displayed.

FIG. 9 shows the structure of an IP data frame as an example of data stored in the DATA field. In FIG. 9, DEST is a destination address and indicates the destination of this data frame.

(5) Initial Setting of AP in this Embodiment (5-1) Setting of CAM Array FIG. 10A shows the definition (table configuration) of the CAM array 250 of the address processor 101. The CPU 121 sets the column size to 2 when the power of the exchange apparatus is turned on or when the definition change is input from the input device 125.

The VPI and VCI used in the receiving side line to which each AP is connected are stored in the segment 0. As shown in FIG. 6, VPI and VCI are not displayed in the lower 4 bits in the upper 4 octets of the ATM header. In UNI, V is set in the upper 4 bits of the ATM cell header.
PI and VCI are not stored. Therefore, 0 is stored in the upper 4 bits and the lower 4 bits. The output port number of the cell is stored in segment 1. The output port number of the cell corresponds to the "line number" of the present invention, and the VPI and VCI of the segment 0 correspond to the "data used for searching the number" of the present invention. FIG. 10B shows the definition (table configuration) of the CAM array 250 of the address processor 102. Set the column size to 3. LAN line 152
Above, IP data frames and other data frames are mixed. Therefore, the destination identification information stored in each data frame is stored in the segment 0.
For example, for IP, DEST shown in FIG. 9 is stored in segment 0. In segment 1, the port number of the line connected to the destination is stored, and in segment 2,
VPI, VCI, PT, C associated with the destination
Store the LP. Also, the initial value of GFC is stored in the upper 4 bits. In PVC, VCI and VPI are stored in advance, and in VC, VPI and VCI are set when a call is set up.
To store. The port number, VPI, and VCI correspond to the “line number” of the present invention, and the destination identification information or DES
T corresponds to the "data used for number search" of the present invention. When only one ATM line is connected, it is not necessary to select the ATM line port, so the column size is set to 2 and VPI and VC are set for segment 1.
Store I. VPI and VCI are logical line numbers and correspond to the "line number" of the present invention.

(5-2) Setting of input sequence of AP 101 The CPU 121 selects the input sequence of A channel,
The control register sets the effective data width of the input data to 8 bits, which is the same as the width of the NT output data. The VPI and VCI are displayed in the first to fourth octets of the ATM cell transferred to the AP. So the CPU 121 corresponds to those octets,
The 0th bit to the 3rd bit of the CUT register are set to 1 and the other bits are set to 0. The CUT register corresponds to the position storage means in the present invention. The 4-byte data of the first octet to the fourth octet is combined in the AP to become the first comparand data and stored in the comparand register.

Next, the third bit of the SEARCH register is set to 1 and the other bits are set to 0. Thereby, the search is executed when the fourth input data corresponding to the third bit is input. The SEARCH register corresponds to the search data position storage means in the present invention. Top 4
Bits and lower 4 bits are not used for searching. There 1
The upper 4 bits and the lower 4 bits of the mask register (first mask register) corresponding to the th search are set to 0, and the other bits are set to 1.

(5-3) Setting the input sequence of AP 102 Set the input sequence for IP on channel A, and set B
Set the input sequence for the data frame of another protocol in the channel. The CPU 121 sets, in the CUT registers of the A channel and the B channel, data indicating the range from the beginning of the data frame to the range where the destination identification information of various protocols can be stored, similar to the input sequence for the AP 101. Also, the input sequence of the A channel is selected, and the data position of the last byte where DEST is stored is set in the SEARCH register. Similarly, the position of the last byte in the destination identification information based on another protocol is set in the SEARCH register of the B channel.

Ethernet type or IEEE80
The TYPE value indicating IP in 2.3 is stored in the A channel selection register, and the TYPE value indicating the protocol used in the B channel is stored in the B channel selection register. The A channel selection register and the B channel selection register correspond to selection data storage means in the present invention, and TYPE corresponds to selection data. For each channel, the necessary CS register and mask register settings are made as in the AP 101.

(5-4) Setting of Output Sequence of AP 101 The output sequence of the A channel is selected, and the effective data width of the output data is set to 8 bits which is the same as the width of the input data of NT by the control register. In this embodiment,
Since no data is output from the AP 101 to the output port, data indicating that there is no output data is set in each AOC register. When the setting is completed, the CPU 121 issues a SWIOP command to the address processor 101 to shift the AP 101 to the IOP mode.

(5-5) Setting of Output Sequence of AP 102 The output sequence of the A channel is selected, and the effective data width of the output data is set to 8 bits which is the same as the width of the NT input data by the control register. Next, the sequence of output data is set by the AOC register. In this embodiment, GFC and VP in the output side network
It outputs I, VCI, PT, and CLP. Therefore, the first AOC register is set to output CAM data. VPI and VCI of output network
Is stored in segment 2, so the first AOS
Set segment 2 in the C register. Upon completion of these settings, the CPU 121 causes the address processor 102 to
To issue an SWIOP_SELECT command to cause the address processor 102 to transition to the IOP_SELECT mode.

(6) Search Operation of Switching Device With reference to FIG. 11, the search operation of the exchange of the present invention after the initial setting of each AP is completed and the input / output mode is entered will be described.

(6-1) Reception of data frame from LAN line 152 In NT301, one data frame is an internal FIFO
When it is stored in the AP, the TYPE is transferred to the AP 102 (S
100). If the data frame is an IP data frame (S110), the transferred data (TYP
Since the value of E) is the same as the value of the data stored in the A channel selection register, the AP 102 selects the A channel (S120). If the TYPE value is the same as the data value stored in the B channel, the AP 102 selects the B channel (S130). Subsequently, the NT 301 sends data from the beginning of the received data frame to the range in which the destination identification information of the data frame of various protocols can be included,
Request the DMAC 103 to transfer to the AP 102. The DMAC 103 outputs the address signal (ADR), the read signal (RD) and the chip select signal (CS) to the data transfer bus of the NT 301 to read the data, and the write signal (W to the input port of the AP 102.
Data is transferred by outputting T) and writing the data (S140).

Since the AP 102 has transitioned to the input / output mode, when the WT signal is input from the input port, the data on the input port is read according to a preset input sequence to perform a search. The AP 102 takes in the destination identification information from the transferred data according to the input sequence of the channel A or the channel B. Destination identification information of the input data frame (DEST in IP
(Corresponding to) is registered in AP102, AP1
02 finds the row by searching and issues an interrupt to the CPU 121. When an interrupt occurs (S1
50), the CPU 121 reads the segment address of the hit segment from the HHA register of the address register of the AP 102 (S160). Then, the value obtained by adding 1 to the read segment address is written in the address register of the AP 102 to specify the port address of the hit data (S170). Then Memory
The value of the output port is read from the _R register (S18
0), the connection from the port to which the AP is connected to the read output port is set to the SEU 111 (S1)
90).

(6-2) Transmission of data frame to ATM line 150 Next, the CPU 121 sets 4-byte data transfer from the AP 102 to the SEU 111 in the DMAC 103 (S
210). The DMAC 103 outputs the output enable signal (OE) and R to the output port 220 of the AP 102.
Data is transferred by outputting D and reading the data and outputting CS and WR to the SEU 111 and writing the data.

When the RD signal is input to the output port, AP 102 outputs data from the output port according to a predetermined output sequence. That is, the VPI and VCI of the line on the output side stored in the segment 2 are output every 8 bits. When the 4-byte data transfer from the AP is completed, the DMAC 103 issues an interrupt to the CPU 121. Then, the CPU 121 continues to NT
The data transfer of 48 bytes from 301 to SEU111 is set (S220).

The cell data input to the SEU111 is
Transferred to the output side port, DMAC of the output side port
The data is transferred to the output port NT301 by 103 (S230). The output port NT 301 converts the transferred data into serial data and outputs the AT network 15 on the output side.
Send to 0. LAN line 15 from S210 to S230
Repeat until all the data frames received from 2 have been transferred (S240). As a result, the data frame input to the exchange can be transferred. When the transfer is completed, the CPU 121 issues an SQRST command to the AP 102 and returns the input / output sequence to the beginning (S250).

[Others] In the first embodiment, an IWU for connecting a LAN and an ATM network to each other was used as an example of the exchange of the present invention, but the exchange of the present invention can also be applied to an exchange in an Ethernet or SNAP LAN. Needless to say. In this case, the port number to which the destination Ethernet or SNAP line is connected, or /
And the destination identification information used at that port is used as the target data of the address processor. The port number of the line connected to the destination Ethernet or SNAP, or the destination identification information used at that port corresponds to the "line number" in the present invention.

In the first embodiment, the transmission destination is searched after one data frame is stored in the NT 301, but the received information may be sequentially transferred to the address processor. In this case, set all bits in the CUT register to 1,
All the received data is taken into AP. Further, the bit of the SEARCH register corresponding to the last byte of the destination identification information counted from the beginning of the received data frame is set to 1. According to this tenth aspect, the port number or the like of the transmission destination can be searched at the time when the transmission destination identification information is transferred without receiving all the data frames. Therefore, the received data frame can be switched with a smaller delay time.

[0077]

As is apparent from the above description, according to the present invention, the search data, the identification number of the line associated with the search data, and the identification number of the destination line in the received data frame are used. Since the data position of the data and the data associated with the data position are stored in advance, when the data frame is received, it is possible to select which data position to use based on a part of the data in the data frame. You can Furthermore, it is possible to retrieve the identification number associated with the data at the selected data position and transmit the data frame received from the line of the retrieved identification number.
Therefore, according to the exchange and the exchange method of the present invention, it is possible to switch a plurality of data frames based on a plurality of protocols in which the storage location of the identification information of the transmission destination is different.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a network system of the present invention.

FIG. 2 is a hardware block diagram of the exchange of the present invention.

FIG. 3 is a hardware block diagram of an address processor (AP).

FIG. 4 is an explanatory diagram showing a structure of a CAM basic word.

FIG. 5 is an explanatory diagram showing a configuration of a CAM array.

FIG. 6 is an explanatory diagram showing the structure of an ATM cell.

FIG. 7 is an explanatory diagram showing a configuration of an Ethernet type data frame.

FIG. 8 is an explanatory diagram of an IEEE 802.3 data frame.

FIG. 9 is an explanatory diagram of an IP data frame.

FIG. 10 is an explanatory diagram showing setting of the CAM array of the AP 102.

FIG. 11 is a flowchart showing a search operation by the exchange apparatus of the present invention.

[Explanation of Codes] 10 ATM Network 11-17 ATM Switch 21-24 Terminal 31, 32 IWU 44-46 LAN Terminal 101, 102 Address Processor (AP) 103 Dynamic Memory Access Controller (D
MAC) 104 bus arbiter 111 switching element unit (SEU) 121 CPU 122 ROM 123 RAM 124 timer 125 input device 126 display device 131-134 address processor 150 ATM line 152 LAN line 160 data bus 170 CPU bus 210 input port 211 data formatter 212 input Port sequencer 220 Output port 222 Output port sequencer 230 CPU port 231 Flag logic 250 CAM array 251 Empty bit 252 Boundary bit 253 Segment number bit 254 Segment 255 Hit / miss hit flag 256 Access bit 301-308 Network terminator (NT)

Claims (8)

[Claims] 1. A switching device that receives a data frame and transfers the data frame to an output line associated with the data frame stores the search data and the identification number of the line associated with the search data. Storage means, position storage means for storing the position of data to be captured inside the data frame, capture means for capturing data at the position in the data frame, and used for searching the identification number in the captured data A search data position storing means for storing the position of the data, and a semiconductor device having a searching means for searching the identification number from the storing means on the basis of the position data stored in the position storing means, and the semiconductor device for searching A transmission means for transmitting the data frame from the line of the identified identification number Exchange apparatus according to claim. 2. The exchange apparatus according to claim 1, wherein the semiconductor device has a plurality of the position storage means and a plurality of the search data position storage means, and each search data position storage means has a respective position storage means. And a means for inputting selection data for selecting which position storage means and search data position storage means to be used, and which position storage means and search data position based on the selection data. An exchange apparatus further comprising a selection unit for selecting whether to use a storage unit. 3. The exchange apparatus according to claim 2, wherein at least one of the position storage means and the search data position storage means associated with the position storage means stores data including IP DEST. The location is stored, and the selection data is Ethernet or SNAP TY.
An exchange device characterized by being PE. 4. In a switching method of receiving a data frame and transferring the data frame to an output line associated with the data frame, search data and an identification number of the line associated with the search data are stored in advance. However, a plurality of data positions of data used for searching the identification number in the data frame are stored, selection data used for selecting which data position is used is input, and any data is selected based on the selection data. A switching method comprising selecting whether to use a position, searching for the identification number associated with the data at the selected data position, and transmitting the data frame from the line indicated by the identification number. 5. The exchange method according to claim 4, wherein the at least one data position is a position of data including DEST of IP, and the selected data is TY of Ethernet or SNAP.
An exchange method characterized by being PE. 6. A storage means for storing search data and output data associated with the search data, a position storage means for storing a position of data to be taken into the input data string, and an input data string. And a retrieval means for retrieving the retrieval data from the storage means on the basis of the data at a predetermined position in the retrieved data, An output device that outputs the output data associated with the search data, the semiconductor device. 7. The semiconductor device according to claim 6, comprising a plurality of the position storing means, the fetching means, and the searching means, each fetching means and each searching means in each position storing means. A semiconductor device, which is associated with the semiconductor device, further comprising selection means for inputting selection data for selecting which of the position storage means, the acquisition means, and the search means to be used. 8. The semiconductor device according to claim 7, wherein the selection means includes selected data storage means for storing data associated with each position storage means, each fetching means, and each search means. A semiconductor device, characterized in that, when the selection data is input, a position storage unit, a loading unit, and a search unit associated with the input selection data are selected.