JPH08102689A - Receiver provided with clock oscillation circuit - Google Patents
Receiver provided with clock oscillation circuitInfo
- Publication number
- JPH08102689A JPH08102689A JP26308494A JP26308494A JPH08102689A JP H08102689 A JPH08102689 A JP H08102689A JP 26308494 A JP26308494 A JP 26308494A JP 26308494 A JP26308494 A JP 26308494A JP H08102689 A JPH08102689 A JP H08102689A
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- Prior art keywords
- circuit
- receiver
- output
- clock
- oscillation circuit
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、クロック発振回路を備
えた受信機に関し、特に、ＣＰＵ等のロジック回路駆動
用のクロック発振回路出力の高調波等が受信機の受信帯
域周波数と一致またはその近傍周波数となる場合の不具
合を解消することができる受信機に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver provided with a clock oscillation circuit, and more particularly, the harmonics of the output of the clock oscillation circuit for driving a logic circuit such as a CPU or the like coincides with the reception band frequency of the receiver or the same. The present invention relates to a receiver capable of solving a problem in the case of a near frequency.
【０００２】[0002]
【従来技術】クロック発振回路を備えた受信機として
は、例えばセルコール受信機をはじめとして、セルラ用
無線機や自動車用携帯無線機、あるいはコードレス電話
用無線機等多くのものが考えられ、近年においてはほと
んどの受信機がＣＰＵを有することから、そのためのシ
ステムクロック発振回路は不可欠のものとなりつつあ
る。しかし、上記システムクロック出力は多くの高調波
を含んでいることから、その成分が受信帯域に混入する
と受信機の受信機能の妨害となる。特に、受信機がＰＳ
ＫやＦＳＫ等のデジタルデータ受信機である場合は、上
記高調波成分により復調ビットが誤った値となり、デー
タ誤りが頻発することになる。2. Description of the Related Art As a receiver equipped with a clock oscillation circuit, for example, a cell call receiver, a cellular radio, a mobile radio for an automobile, a radio for a cordless telephone, and many others are considered. Since most receivers have a CPU, a system clock oscillation circuit therefor is becoming indispensable. However, since the system clock output contains many harmonics, if the component is mixed in the reception band, it interferes with the reception function of the receiver. Especially when the receiver is PS
In the case of a digital data receiver such as K or FSK, the above-mentioned harmonic component causes the demodulated bit to have an erroneous value, resulting in frequent data error.
【０００３】従来、この不具合を解決するための方法と
して例えば特開平４−３２０１０２に提案されたものが
ある。この方法は、システムクロック発振回路の発振周
波数を三角波でＦＭ変調することによって単位時間当た
りに受信機の妨害となる周波数成分の平均電力を小さく
して妨害程度を軽減しようとするものである。しかしな
がら、上記特開平４−３２０１０２のようにシステムク
ロック発振回路出力を三角波等により変調する方法で
は、三角波発生回路が必要となり回路の複雑化をまねく
のみならず、不要な雑音の発生のおそれが生じる問題が
あった。Conventionally, as a method for solving this problem, for example, there is a method proposed in Japanese Patent Laid-Open No. 4-320102. This method is intended to reduce the degree of interference by performing FM modulation of the oscillation frequency of the system clock oscillator circuit with a triangular wave to reduce the average power of frequency components that interfere with the receiver per unit time. However, in the method of modulating the output of the system clock oscillator circuit with a triangular wave or the like as in the above-mentioned Japanese Patent Laid-Open No. 4-320102, a triangular wave generating circuit is required, which not only complicates the circuit, but also may cause unnecessary noise. There was a problem.
【０００４】[0004]
【目的】本発明は、上記事情に鑑みてなされたものであ
って、ＣＰＵ等のロジック回路駆動用のクロック発振回
路出力の高調波等が受信機の受信帯域周波数と一致しま
たはその近傍周波数となる場合の不具合を解消すること
ができる簡単な構成の受信機を提供することを目的とす
る。The present invention has been made in view of the above circumstances, and harmonics or the like of the output of a clock oscillation circuit for driving a logic circuit of a CPU or the like coincides with a reception band frequency of a receiver or a frequency in the vicinity thereof. It is an object of the present invention to provide a receiver having a simple structure that can solve the problem in the case of the above.
【０００５】[0005]
【発明の概要】上記目的を達成するため、本発明は、ロ
ジック回路用のクロック発振回路を備えた受信機におい
て、上記クロック発振回路には発振周波数変更手段を備
えると共に、上記受信機の復調出力信号電圧が所定期間
ほぼ同一電圧であることを検出する検出手段を備え、該
検出手段により復調出力信号電圧が所定期間ほぼ同一電
圧であることを検出した際に、前記ロジック回路用クロ
ック発振回路の出力周波数を変更する様にしたことを特
徴とする。SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a receiver provided with a clock oscillation circuit for a logic circuit, wherein the clock oscillation circuit is provided with an oscillation frequency changing means, and the demodulation output of the receiver is provided. The logic circuit clock oscillating circuit is provided with detecting means for detecting that the signal voltage is substantially the same voltage for a predetermined period, and when the detecting means detects that the demodulated output signal voltage is substantially the same voltage for the predetermined period. The feature is that the output frequency is changed.
【０００６】[0006]
【実施例】以下、図面に示した実施例に基づいて本発明
を詳細に説明する。図１は本発明に係るクロック発振回
路を備えた受信機の一実施例の要部ブロック構成図であ
る。同図において、１はインバータを増幅器として用い
たコルピッツ型水晶発振回路であって、インバータ２の
入力端とアース間にコンデンサＣ1 を、また出力端とア
ース間にバリキャップ（可変客量ダイオード）Ｄ1 を、
インバータ２の入出力端子間に水晶振動子Ｘを接続した
ものである。さらに、前記バリキャップＤ1 の両端には
抵抗Ｒを介して制御電圧発生部３が接続され、この制御
電圧発生部３には受信データ判定回路４が接続され、こ
の受信データ判定回路４には受信機５の復調回路ブロッ
クの出力が供給されるようになっている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram of a main part of an embodiment of a receiver including a clock oscillator circuit according to the present invention. In the figure, reference numeral 1 is a Colpitts type crystal oscillation circuit using an inverter as an amplifier. A capacitor C 1 is provided between the input end of the inverter 2 and the ground, and a varicap (variable customer quantity diode) is provided between the output end and the ground. D 1
The crystal unit X is connected between the input and output terminals of the inverter 2. Further, a control voltage generation unit 3 is connected to both ends of the varicap D 1 via a resistor R, a reception data determination circuit 4 is connected to the control voltage generation unit 3, and the reception data determination circuit 4 is connected to the reception data determination circuit 4. The output of the demodulation circuit block of the receiver 5 is supplied.
【０００７】上記構成のクロック発振回路を備えた受信
機の基本的な動作について説明する。通常は前記インバ
ータクロック発振回路１のバリキャップＤ1 には所定の
電圧が印加され、所定の発振周波数信号を発生し、図示
を省略した波型成形回路や必要に応じて挿入される分周
器等によってクロック信号とし、所望のロジック回路あ
るいはＣＰＵ等のシステムクロックとして利用される。
また、受信機５には図示を省略した受信高周波回路や局
部発振回路、混合回路、フィルタ回路、中間周波信号増
幅回路、復調回路、符号判定回路等が備えられている。
前記ロジック回路は、例えば受信チャネル制御やページ
ャ等にあっては、フレーム同期受信の制御その他複雑な
機能制御を行う。また携帯電話装置等にあっては、マル
チセルラゾーン（基地局の選択）や制御信号の解読等を
行うこともある。むしろ近年の無線送受信機にあっては
ロジック回路とシステムクロック発振回路を備えたもの
が一般的である。The basic operation of the receiver including the clock oscillation circuit having the above configuration will be described. Normally, a predetermined voltage is applied to the varicap D 1 of the inverter clock oscillation circuit 1 to generate a predetermined oscillation frequency signal, and a wave shaping circuit (not shown) or a frequency divider inserted as necessary. It is used as a clock signal according to the above, and is used as a system clock of a desired logic circuit or CPU.
Further, the receiver 5 is provided with a reception high frequency circuit, a local oscillation circuit, a mixing circuit, a filter circuit, an intermediate frequency signal amplification circuit, a demodulation circuit, a code determination circuit, etc., which are not shown.
For example, in the case of receiving channel control and pager, the logic circuit controls frame synchronous reception and other complicated function control. In addition, in a mobile phone device or the like, multi-cellular zone (selection of base station) and decoding of control signals may be performed. Rather, wireless transceivers of recent years are generally equipped with a logic circuit and a system clock oscillation circuit.
【０００８】このようにシステムクロック発振回路を備
えた受信機では、発生したクロック信号そのもの、ある
いはその高調波が、受信チャネル周波数と一致、または
その近傍の周波数の妨害波となることがある。この場
合、受信チャネル信号の受信電界強度が小さいとき、あ
るいは妨害波レベルが大きいとき、正常な受信を妨げる
こととなる。In the receiver having the system clock oscillation circuit as described above, the generated clock signal itself or a harmonic thereof may become an interfering wave whose frequency is equal to or near the reception channel frequency. In this case, when the reception electric field strength of the reception channel signal is small or the interference wave level is large, normal reception is hindered.
【０００９】ここで、妨害波が受信チャネルに混入する
と、その結果が、受信機の復調出力に現れる。例えば、
その受信機がＦＳＫやＰＳＫ変調波を受信するものであ
る場合は、システムクロック出力に基づいて妨害波の混
入により復調出力ビット列が、全て“１”または全て
“０”となる。Here, if an interfering wave is mixed in the reception channel, the result appears in the demodulation output of the receiver. For example,
When the receiver receives an FSK or PSK modulated wave, the demodulation output bit string becomes all "1" or all "0" due to the interfering wave mixing based on the system clock output.
【００１０】本発明は、このような現象を利用して、受
信機５の復調出力中に全て“０”または全て“１”のビ
ット値が出現した場合には、クロック発振回路出力が受
信機に妨害を与えたものと判定して、上記受信データ判
定回路４から出力を発生し、上記制御電圧発生部３に供
給する。上記制御電圧発生部３ではクロック発振回路１
のバリキャップＤ1 に供給する電圧をわずかに変化させ
ることによって、クロック発振回路１の発振周波数を変
化させる。この発振周波数の変化制御を行えば、クロッ
ク発振回路出力の受信機に対する妨害が解消される。The present invention utilizes such a phenomenon, and when bit values of all "0" or all "1" appear in the demodulated output of the receiver 5, the output of the clock oscillation circuit is the receiver. It is determined that the received data has been disturbed, an output is generated from the reception data determination circuit 4, and the output is supplied to the control voltage generation unit 3. In the control voltage generator 3, the clock oscillator 1
The oscillation frequency of the clock oscillation circuit 1 is changed by slightly changing the voltage supplied to the varicap D 1 . By controlling the change of the oscillation frequency, the interference of the output of the clock oscillation circuit with respect to the receiver is eliminated.
【００１１】なお、クロック発振回路の周波数の変化量
は、システムクロック周波数の許容周波数偏差以内とす
れば問題はない。さらに、システムクロック発振周波数
に周波数偏差の制限がない場合も考えられるから、その
場合の変化量は適宜決定することができる。また、周波
数を変化させる方法は、△ｆだけ増加する場合と減ずる
場合、さらには変化量△ｆの値についても自由度がある
から最初所定量変化させて、上述した受信機の復調出力
のビット値の列を判定し、もし、変化した後も受信妨害
が有りと判定された場合は、さらに△ｆの量を変更する
か、逆方向に変化させて妨害のない周波数を捜査するよ
うに構成すればよい。There is no problem if the amount of change in the frequency of the clock oscillation circuit is within the allowable frequency deviation of the system clock frequency. Further, since there may be a case where the system clock oscillation frequency is not limited by the frequency deviation, the amount of change in that case can be appropriately determined. In addition, the method of changing the frequency is to increase or decrease by Δf, and further, since there is a degree of freedom in the value of the change amount Δf, the frequency is first changed by a predetermined amount, and the bit of the demodulation output of the receiver described above is changed. The value sequence is determined, and if it is determined that there is reception interference even after the change, the amount of Δf is further changed or changed in the opposite direction to search for a frequency without interference. do it.
【００１２】図２は本発明の変形例を示すブロック構成
図であり、受信データ判定回路については少し詳細に図
示している。この変形例に示す構成は、インバータ発振
回路１０が、インバータ２と、その入出力端に接続した
水晶振動子Ｘと、コンデンサＣ1 、Ｃ2 とから成り、周
波数を変更するための手段としてコンデンサＣ1 に並列
に、コンデンサＣ3 とバリキャップＤ2 との直列回路を
挿入すると共に、前記バリキャップＤ2 に抵抗Ｒを介し
て制御電圧発生部３０の出力電圧を供給するように構成
したものである。FIG. 2 is a block diagram showing a modification of the present invention, in which the received data decision circuit is shown in some detail. In the configuration shown in this modification, the inverter oscillating circuit 10 includes an inverter 2, a crystal resonator X connected to its input / output terminals, and capacitors C 1 and C 2, and is a capacitor as a means for changing the frequency. A configuration in which a series circuit of a capacitor C 3 and a varicap D 2 is inserted in parallel with C 1 and the output voltage of the control voltage generator 30 is supplied to the varicap D 2 via a resistor R. Is.
【００１３】また、受信データ判定回路４０は、受信機
５０の復調出力信号からデータクロック信号を抽出する
ビット同期回路４１と、該データクロック信号によって
制御されるＮ段シフトレジスタ４２と、このシフトレジ
スタ４２のＮ個の出力を入力するＡＮＤ回路４３および
ＮＡＮＤ回路４４と、これら２つの回路４３、４４の出
力を入力するＯＲ回路４５とを備える。また、制御電圧
発生部３０はフリップフロップ回路３１を含み、前記受
信データ判定回路４０のＯＲ回路４５の出力によって出
力電圧が高電位かまたは低電位になる。The reception data determination circuit 40 also includes a bit synchronization circuit 41 for extracting a data clock signal from the demodulated output signal of the receiver 50, an N-stage shift register 42 controlled by the data clock signal, and this shift register. An AND circuit 43 and a NAND circuit 44 for inputting the N outputs of 42 and an OR circuit 45 for inputting the outputs of these two circuits 43, 44 are provided. Further, the control voltage generator 30 includes a flip-flop circuit 31, and the output voltage becomes a high potential or a low potential according to the output of the OR circuit 45 of the received data determination circuit 40.
【００１４】次に、図２に示す回路の動作を説明する。
今、受信機５０がＰＳＫあるいはＦＳＫ等のデジタルデ
ータ受信機であると考えると、その復調出力信号は
“Ｈ”と“Ｌ”が混在したデジタル信号となる。しか
し、もし妨害波が存在し、正常なデータの復調ができな
い場合は、復調出力ビット値が全て“Ｈ”または“Ｌ”
になる。また、復調信号中にはビット同期信号が含まれ
ることが多く、ビット同期回路４１においてこの信号か
らデータクロック信号を抽出するかあるいは、内蔵した
クロック発振回路出力をビット同期信号に同期させるこ
とによってデータクロックを生成する。Next, the operation of the circuit shown in FIG. 2 will be described.
Now, assuming that the receiver 50 is a digital data receiver such as PSK or FSK, the demodulated output signal is a digital signal in which "H" and "L" are mixed. However, if there is an interfering wave and normal data cannot be demodulated, the demodulated output bit values are all "H" or "L".
become. In addition, the demodulated signal often contains a bit synchronization signal, and the data clock signal is extracted from this signal in the bit synchronization circuit 41, or the output of the built-in clock oscillation circuit is synchronized with the bit synchronization signal. Generate a clock.
【００１５】前記Ｎ段シフトレジスタ４２にはこのデー
タクロックが供給され、同時に受信機５０の復調信号が
入力される。従って、もし受信機の復調出力のＮビット
分が全て“Ｈ”または“Ｌ”の場合は、ＡＮＤ回路４３
またはＮＡＮＤ回路４４のいづれか一方が“Ｈ”とな
り、ＯＲ回路４５の出力が発生してフリップフロップ３
１に入力される。以上のように、受信機５０の復調出力
のＮビット分が全て“Ｈ”または“Ｌ”の場合にインバ
ータ発振回路のバリキャップＤ2 に印加される電圧が変
化することから、その発振周波数が変更される。The data clock is supplied to the N-stage shift register 42, and at the same time, the demodulated signal of the receiver 50 is input. Therefore, if all N bits of the demodulated output of the receiver are "H" or "L", the AND circuit 43
Alternatively, one of the NAND circuits 44 becomes "H", the output of the OR circuit 45 is generated, and the flip-flop 3
Input to 1. As described above, when all the N bits of the demodulated output of the receiver 50 are “H” or “L”, the voltage applied to the varicap D 2 of the inverter oscillation circuit changes, so that the oscillation frequency is changed. Be changed.
【００１６】インバータ発振回路の出力が受信機の妨害
波となる例としては、例えば、受信周波数がｆCH、受信
帯域幅がｆBW、システムクロック周波数がｆ1 とする
と、 ｆCH−ｆBW／２≦Ｎ・ｆ1 ≦ｆCH＋ｆBW／２ …（１） の関係にある場合に妨害波となり、受信障害を生ずるこ
とがある。受信妨害となるとき、上述した制御によって
システムクロック周波数を変更すれば、妨害を回避する
ことができる。なお、以上本発明の一実施例について説
明したが、本発明の実施にあたってはこの例に限らず手
段の変形が可能であって、システムクロック発振回路は
インバータ回路に限らず周波数を可変できる種々の発振
回路に置換することができる。また、受信データ判定回
路および制御電圧発生部も他の回路で代用できることは
言うまでもない。As an example in which the output of the inverter oscillating circuit becomes the interference wave of the receiver, for example, if the receiving frequency is f CH , the receiving bandwidth is f BW , and the system clock frequency is f 1 , then f CH -f BW / In the case of the relationship of 2 ≦ N · f 1 ≦ f CH + f BW / 2 (1), an interference wave is generated, and reception failure may occur. When the reception interference occurs, the interference can be avoided by changing the system clock frequency by the control described above. Although one embodiment of the present invention has been described above, the means for carrying out the present invention is not limited to this example, and the means can be modified, and the system clock oscillator circuit is not limited to the inverter circuit, and various frequencies can be changed. It can be replaced with an oscillator circuit. Further, it goes without saying that the reception data determination circuit and the control voltage generator can be replaced with other circuits.
【００１７】[0017]
【発明の効果】本発明は以上説明したように構成し、か
つ、制御するので、クロック発振回路を有する受信機に
おいてクロック発振回路出力が受信機の妨害波となる不
具合を回避し、常に正常な受信が可能となる。Since the present invention is constructed and controlled as described above, it is possible to avoid the problem that the output of the clock oscillation circuit becomes an interfering wave of the receiver in the receiver having the clock oscillation circuit, and to keep the normal state. It becomes possible to receive.
【図１】本発明によるクロック発振回路を備えた受信機
の一実施例を示す概略ブロック構成図である。FIG. 1 is a schematic block configuration diagram showing an embodiment of a receiver including a clock oscillation circuit according to the present invention.
【図２】図１に示したクロック発振回路を備えた受信機
の変形例の回路構成図である。FIG. 2 is a circuit configuration diagram of a modified example of a receiver including the clock oscillation circuit shown in FIG.
【符号の説明】 １、１０…システムクロック発振回路、 ２…インバ
ータ、３、３０…制御電圧発生部、 ４、
４０…受信データ判定回路、５、５０…受信機、
３１…フリップフロップ回路、４１…
ビット同期回路、 ４２…シフトレジ
スタ、４３…ＡＮＤ回路、 ４４
…ＮＡＮＤ回路、４５…ＯＲ回路、
Ｃ1 、Ｃ2 、Ｃ3 …コンデンサ、Ｄ1 、Ｄ2 …バ
リキャップ、 Ｒ…抵抗、[Explanation of reference numerals] 1, 10 ... System clock oscillator circuit, 2 ... Inverter, 3, 30 ... Control voltage generating unit, 4,
40 ... Received data determination circuit, 5, 50 ... Receiver,
31 ... Flip-flop circuit, 41 ...
Bit synchronization circuit, 42 ... Shift register, 43 ... AND circuit, 44
... NAND circuit, 45 ... OR circuit,
C 1 , C 2 , C 3 ... Capacitor, D 1 , D 2 ... Varicap, R ... Resistor,
Claims (2)
えた受信機において、上記クロック発振回路には発振周
波数変更手段を備えると共に、上記受信機の復調出力信
号電圧が所定期間ほぼ同一電圧であることを検出する検
出手段を備え、該検出手段により復調出力信号電圧が所
定期間ほぼ同一電圧であることを検出した際に上記ロジ
ック回路用クロック発振回路の出力周波数を変更する様
にしたことを特徴とするクロック発振回路を備えた受信
機。1. A receiver provided with a clock oscillation circuit for a logic circuit, wherein the clock oscillation circuit is provided with oscillation frequency changing means, and the demodulation output signal voltage of the receiver is substantially the same voltage for a predetermined period. The output frequency of the logic circuit clock oscillation circuit is changed when the detection unit detects that the demodulated output signal voltage is substantially the same voltage for a predetermined period. A receiver equipped with a clock oscillator circuit.
え、ＦＳＫまたはＰＳＫ等のデジタル符号を受信可能な
受信機において、上記クロック発振回路には発振周波数
変更手段を備えると共に、上記受信機の復調出力の所要
ビット数の各値が全て“１”または全て“０”のいづれ
であるかを検出する手段を備え、該検出の結果、所要ビ
ット値が全て“１”または全て“０”である場合に、上
記クロック発振回路の出力周波数を変更することを特徴
とするクロック発振回路を備えた受信機。2. A receiver comprising a clock circuit for a logic circuit and capable of receiving digital codes such as FSK or PSK, wherein the clock oscillator circuit is provided with an oscillation frequency changing means, and a demodulated output of the receiver is provided. A means for detecting whether each value of the required number of bits is all “1” or all “0” is provided, and when the required bit values are all “1” or all “0” as a result of the detection, A receiver provided with a clock oscillation circuit, characterized in that the output frequency of the clock oscillation circuit is changed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26308494A JP3593159B2 (en) | 1994-10-03 | 1994-10-03 | Receiver with clock oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26308494A JP3593159B2 (en) | 1994-10-03 | 1994-10-03 | Receiver with clock oscillation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08102689A true JPH08102689A (en) | 1996-04-16 |
| JP3593159B2 JP3593159B2 (en) | 2004-11-24 |
Family
ID=17384614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26308494A Expired - Lifetime JP3593159B2 (en) | 1994-10-03 | 1994-10-03 | Receiver with clock oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3593159B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6564040B1 (en) | 1999-05-25 | 2003-05-13 | Matsushita Electric Industrial Co., Ltd. | Communication device and communication method |
-
1994
- 1994-10-03 JP JP26308494A patent/JP3593159B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6564040B1 (en) | 1999-05-25 | 2003-05-13 | Matsushita Electric Industrial Co., Ltd. | Communication device and communication method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3593159B2 (en) | 2004-11-24 |
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