JPH08101400A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To improve an opening rate and to increase auxiliary capacitance by forming auxiliary capacitor electrodes of transparent conductive layers and disposing these electrodes opposite to each other over the entire surface of display electrodes. CONSTITUTION: The transparent auxiliary capacitor electrodes 11 are entirely formed on a transparent substrate 10 and the light shielding layers 12 are formed on the auxiliary capacitor electrode 11. Interlayer insulating layers 13 are formed over the entire surface covering these auxiliary capacitor electrodes 11 and the light shielding layers 12. The auxiliary capacitor electrodes 11 are formed of the transparent conductive layers over the entire surface and the auxiliary capacitors are formed over the entire region of the display elelctrodes, by which the auiliary capacitance is increased and the opening rate is improved. The use of the transparent conductive layers for the auxiliary capacitor electrodes 11 further leads the acceleration of the higher opening rate in the structure of forming a black matrix on a TFT array substrate side. The transparent auxiliary capacitor electrodes 11 are disposed separately from the black matrix, by which the high opening rate and the large auxiliary capacitance are simultaneously realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which a black matrix is formed on the TFT array substrate side to improve the aperture ratio.

[0002]

2. Description of the Related Art Liquid crystal display devices are characterized by thinness, light weight and low power consumption, and are being put to practical use in the fields of OA equipment, AV equipment and the like. In particular, the active matrix type using a thin film transistor (hereinafter abbreviated as TFT) as a switching element can perform static driving with a duty ratio of 100% in a multiplexed manner in principle, and has a large screen and a high-definition moving image display. Is used for.

In an active matrix type liquid crystal display device, display pixels are arranged in a matrix so that a desired voltage can be applied to a liquid crystal capacitor in which liquid crystal is loaded between transparent electrodes arranged opposite to each other. The transparent electrodes are each supported by a transparent substrate, one is a display electrode formed in a matrix, and the other is a common electrode formed over the entire surface. A thin film transistor (TFT: Thin Film Transistor) is connected to each display electrode,
The input signal voltage is selected. Each TFT is selected by line-sequential scanning and turned on for all the same rows, and a data signal voltage synchronized with this is applied to the display electrodes. The voltage thus applied to the liquid crystal capacitor is held by the OFF resistance of the TFT until it is rewritten in the next field, and a constant electric field is formed in the liquid crystal layer. The liquid crystal reacts electrostatically to change its optical state and modulate the transmitted light. By controlling the light modulation for each pixel, the transmitted light is combined and visually recognized to form a display image.

When the TFT is a positive stagger type in which the gate is arranged in the upper layer with respect to the semiconductor layer, the TFT substrate can be manufactured with three masks, and the cost is low. FIG. 5 shows a liquid crystal display device having such a structure,
In particular, the unit structure of the pixel portion is shown for a black matrix formed on the TFT array substrate side for blocking unmodulated light between display pixels to improve the contrast ratio. (A) is a plan view and (b) is a cross-sectional view.
A gate line (57) for scanning signals is provided on the substrate (50) side.
L) and the drain line (54L) for the data signal are arranged to intersect with each other, and a display electrode (54P) is formed in a region surrounded by both lines (57L, 54L). At the intersection of both lines (57L, 54L), a transparent substrate (5
0) on the light-shielding layer (51) and the interlayer insulating film (53) covering the light-shielding layer (51), and further the source / drain electrodes (54
S, 54D), a-Si layer (55), gate insulating layer (5
6) and the gate electrode (57G) are sequentially laminated to form a TFT. An auxiliary capacitance electrode (52) is arranged on the periphery of the display electrode (54P) and is partially overlapped with the display electrode (54P) with the interlayer insulating layer (53) interposed therebetween to form an auxiliary capacitance.

In this structure, the auxiliary capacitance electrode (5
It is characterized by 2). That is, the auxiliary capacitance electrode (52) forms an auxiliary capacitance and is used as a light shielding layer by being formed in a shape covering the peripheral portion of the display electrode (54P).
By making this function as a black matrix, the aperture ratio is improved. Usually, when the black matrix is formed on the counter substrate side, the deviation at the time of bonding is large, so that a bonding margin of 5 to 10 μm is required to block unmodulated light leaking from the periphery of the display electrode. Effectively, the effective display area is reduced and the aperture ratio is reduced. On the other hand, the black matrix is TF
By forming it on the T-array substrate side, the alignment margin, which allows for misalignment during alignment, is reduced to 2-3 μm, and the aperture ratio is improved.

The auxiliary capacitance electrode (52) is formed of Cr or the like on the transparent substrate (50) such as glass together with the light shielding layer (51) for blocking the incident light from the back surface of the TFT. An interlayer insulating layer (53) such as SiNx is formed on the entire surface so as to cover them. The display electrode (54P) and the drain line (54L) are I on the interlayer insulating layer (53).
It is formed of TO or the like. A part of the display electrode (54P) and the drain line (54L) are close to each other to form a source electrode (54S) and a drain electrode (54D), and a channel layer is formed on both electrodes (54S, 54D). A-Si (55), SiNX
A gate insulating layer (56) such as and a gate electrode (57G) such as Al are stacked to form a TFT. The gate line (57L) is a-Si integrated with the TFT section.
It is arranged on the laminated body composed of (55) and the gate insulating layer (56). The gate line (57L) and the gate electrode (57G) are integrated, and the a-Si (55) and the gate insulating layer (56) are also formed in the same pattern. In addition, a-Si (55) and the source electrode (54S), and
Between the a-Si (55) and the drain electrode (54D),
Ohmic characteristics are improved by interposing N + type a-Si (55N) whose resistance is lowered by implanting impurity ions such as phosphorus. The entire surface covering these is subjected to surface treatment by forming an alignment film (58) of polyimide or the like and performing a predetermined rubbing treatment for the purpose of controlling the alignment of the liquid crystal.

On the substrate (60) arranged so as to face the TFT substrate having such a structure, a light shielding layer (61) having an opening removed corresponding to the display region is formed of Cr or the like. The ITO common electrode (62) is formed over the entire surface. Further, a polyimide alignment film (63) is formed on the surface similarly to the TFT substrate side, and serves as a counter substrate. A liquid crystal layer (70) is provided between both substrates.

[0008]

In the conventional structure shown in FIG. 5, in order to avoid the loss of the display area due to the non-transparent auxiliary capacitance electrode (52), the auxiliary capacitance electrode (52) is replaced by the display electrode (5).
4P). That is, by doing so, the loss of the display area due to the alignment margin of the auxiliary capacitance electrode (52) also serving as a black matrix and the loss of the display area due to the light shielding of the auxiliary capacitance electrode (52) forming the auxiliary capacitance are made to be the same area. In addition, the reduction of the display area is reduced to improve the aperture ratio. With this structure, for example, by corresponding to the loss of the display area when the black matrix is formed on the counter substrate side, the auxiliary capacitance is formed on the TFT array substrate side, so that the loss of the display area by the auxiliary capacitance electrode is eliminated. In addition, a considerably large auxiliary capacitance can be formed.

However, in this structure, when the loss in the display region is suppressed to the minimum by setting only the alignment margin of the auxiliary capacitance electrode (52), it is impossible to increase the auxiliary capacitance value more than that. Further, if the auxiliary capacitance having a predetermined value is formed, the loss of the display area cannot be avoided. That is,
With the conventional structure, it was not possible to achieve both a dramatic increase in aperture ratio and an increase in auxiliary capacitance.

Particularly, in the projection type TV such as a projection TV, the auxiliary capacitance is sufficiently large so as to obtain sufficient brightness and prevent leakage even if strong light is incident and the OFF resistance of the TFT is lowered. However, it is necessary to maintain the voltage holding characteristic.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to achieve this object. First, a plurality of gate lines and a plurality of drain lines which are arranged to intersect each other on one substrate, A plurality of display electrodes arranged in a region surrounded by the gate line and the drain line, and a drain electrode integrated with the drain line and a source electrode integrated with the display electrode are close to each other at an intersection of the gate line and the drain line. A thin film transistor in which a semiconductor layer is formed on the exposed region, an insulating layer is formed on the semiconductor layer, and a gate electrode integrated with the gate line is stacked on the insulating layer; and an auxiliary capacitor that faces the display electrode and forms an auxiliary capacitance. A capacitor electrode and a common electrode that is formed over the entire surface of the other substrate and that faces the display electrodes in common with the liquid crystal sandwiched therebetween and that forms a display pixel capacitance at each facing portion. In the liquid crystal display device, the storage capacitor electrode is a transparent conductive layer which is entirely formed on the substrate, is configured to face the common to the respective display electrodes sandwiching the interlayer insulating layer.

Secondly, in the first structure, a first light shielding layer is formed on the auxiliary capacitance electrode to cover the peripheral portions of the thin film transistor and the display electrode.
Thirdly, in the second configuration, the first light-shielding layer is provided over the entire area between the display electrodes, and the other substrate is two-dimensionally corresponding to the display electrode and the display is provided. In this structure, a second light-shielding layer having an opening larger than the opening of the display electrode except for the region where the periphery of the electrode is shielded by the first light-shielding layer is formed.

Fourthly, in any one of the first to fourth configurations, the auxiliary capacitance electrode is absent from the peripheral portion of the first substrate.

[0014]

In the first structure, the auxiliary capacitance electrode is formed of the transparent conductive layer and is disposed so as to face the entire surface of the display electrode, so that the entire area of the display electrode becomes effective as the display area and the loss of the display area is reduced. It disappears and the aperture ratio is improved. Further, since the entire area of the display electrode is used for the auxiliary capacitance, a large capacitance value can be obtained. That is, it is possible to achieve both a dramatic increase in aperture ratio and an increase in auxiliary capacitance.

In the second structure, the first light-shielding layer that covers the semiconductor layer is formed from the side opposite to the gate electrode,
Leakage current at the time of OFF due to light incident from the back surface is prevented, and the holding characteristic of the applied voltage of the display pixel amount is improved. Further, by forming the first light-shielding layer in a region covering the peripheral edge of the display electrode, the display electrode and the first light-shielding layer are aligned on the substrate side on which the display electrode is formed, and the substrate is bonded. It is possible to perform the mask alignment with a relatively higher accuracy than the time alignment. Therefore, the margin for reducing the display area is reduced and the aperture ratio is improved.

In the third structure, the second light-shielding layer having an opening larger than the opening of the substrate on the side where the display electrode is formed is formed on the side of the substrate on which the common electrode is formed, thereby bonding It is possible to prevent the aperture ratio on the common electrode side from protruding from the aperture on the display electrode side and lowering the aperture ratio due to misalignment. In addition, since the light modulated in the liquid crystal layer spreads and progresses due to the diffraction phenomenon, by making the opening on the common electrode side larger than the opening on the display electrode side, the utilization efficiency of the light transmitted through the display electrode is improved. As a result, the permeation amount increases, resulting in an increase in aperture ratio. Further, between the first light-shielding layer formed over the entire area between the display electrodes and the second light-shielding layer corresponding to the first light-shielding layer, the light sneaking from the edge portion of the light-shielding layer due to diffraction is reflected to open the aperture. It can be ejected from the part. As a result, the utilization efficiency of light is further increased and the amount of transmission is increased.

In the fourth structure, the auxiliary capacitance electrode is absent at the peripheral portion of the substrate, so that when the large substrate is cut and divided into each panel after the formation process of the conductive pattern is completed, the auxiliary capacitance electrode is separated from the substrate end. It is prevented from being exposed from the side of. As a result, short circuit and static electricity input at the connection with the drive circuit element are prevented, and the reliability is improved.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a plan view of a unit pixel of the liquid crystal display device according to the present embodiment, and FIG. 2 is a sectional view taken along the line AA of FIG. An auxiliary capacitance electrode (11) made of a transparent conductive material is entirely formed on a transparent substrate (10),
A light shielding layer (12) also serving as a black matrix is formed on the auxiliary capacitance electrode (11). An interlayer insulating layer (13) is formed on the entire surface covering the auxiliary capacitance electrode (11) and the light shielding layer (12), and a gate line (17L) and a drain line (14L) intersect on the interlayer insulating layer (13). Are arranged. At the intersection of both lines (17L, 14L), the auxiliary capacitance electrode (11), the light shielding layer (12), and the interlayer insulating layer (13) are laminated on the substrate (10) and the source electrode (14S) is formed. The drain electrode (14D) is arranged in close proximity to the semiconductor layer (15), the gate insulating layer (16), and the gate electrode (17G) are sequentially stacked on the drain electrode (14D) to form a TFT. Gate line (17L) is TF
The semiconductor layer (15) and the gate insulating layer (1
It is arranged on the laminated body composed of 6).

A display electrode (14P) is formed in a region surrounded by the gate line (17L) and the drain line (14L), and the auxiliary capacitance electrode (1) is sandwiched by the interlayer insulating layer (13).
It is opposed to 2) and constitutes a storage capacitor. Display electrode (14
A light-shielding layer (12) integrated with the TFT part is formed around P), and the display electrode (14P) is sandwiched by the interlayer insulating layer (13).
Is partially overlapped with the periphery of. In particular, in this embodiment, the light shielding layer (12) is also provided in the entire area other than the opening, that is, in the area above the gate line (17L) and the drain line (14L).

In the pixel portion, a light-shielding layer (21) is formed on a substrate (20) opposed to each other with a liquid crystal layer (30) interposed therebetween, and a common electrode (2) made of a transparent conductive layer is formed on the entire surface covering the light-shielding layer (21).
2) has been formed. The light shielding layer (21) is formed on the substrate (1
It is smaller than the light-shielding layer (12) on the (0) side, that is, the opening thereof corresponds in plan view to the light-shielding layer (1) on the substrate (10) side.
It is formed larger than the opening of 2).

Alignment films (18, 2) are formed on the surfaces of both substrates.
3) is formed to control the alignment of the liquid crystal. In the present invention, the aperture ratio is greatly improved by forming the light-shielding layer (12) also serving as the black matrix on the TFT array substrate (10) side as described above. That is, since the position is determined with high precision by mask alignment during photoetching, the positional deviation between the light shielding layer (12) and the display electrode (14P) is small, and the margin can be reduced. Therefore,
The loss of the display area due to the superposition of the light shielding layer (12) and the display electrode (14P) is reduced, and the aperture ratio is improved.

Further, the auxiliary capacitance electrode (11) is entirely formed of a transparent conductive layer, and the auxiliary capacitance is formed by the display electrode (14P).
The auxiliary capacitance is increased by forming the storage capacitor in the entire area of. Further, since the loss of the display area due to the light-shielding auxiliary capacitance electrode is eliminated as in the conventional case, the aperture ratio is improved. The use of the transparent conductive layer for the auxiliary capacitance electrode (11) further promotes high aperture ratio in the structure in which the black matrix is formed on the TFT array substrate side. That is, reducing the alignment margin and reducing the overlap of the auxiliary capacitance electrode also serving as the black matrix on the display electrode is accompanied by the reduction of the auxiliary capacitance, but the transparent auxiliary capacitance electrode (11) is provided separately from the black matrix. Thus, a high aperture ratio and a large auxiliary capacitance can be realized at the same time.

A positive stagger type in which the gate of the TFT is arranged above the semiconductor layer is suitable for such a structure having the auxiliary capacitance electrode (11). When applied to the inverted stagger type, the auxiliary capacitance electrode, the (light-shielding layer), the interlayer insulating layer, the gate electrode, the gate insulating layer, the semiconductor layer, and the source / drain electrode are sequentially stacked on the substrate. There is a problem. Since the gate layer is below the display electrode, the gate signal is distorted due to the parasitic capacitance between the gate and the auxiliary capacitance electrode. The distortion of the gate signal directly affects the switching operation of the TFT. In order to avoid this, if the interlayer insulating layer is thickened to reduce the parasitic capacitance, the auxiliary capacitance is reduced due to the thickness including the gate insulating layer, and the effect of adopting this structure is lost. In the structure in which the gate insulating layer is patterned and left only in the TFT part,
The step between the TFT and the display electrode becomes large, and the alignment film (18)
The unevenness of the surface disturbs the alignment of the liquid crystal, causing problems such as reverse tilt domain and disclination.

Further, in the present invention, in particular, on the ITO auxiliary capacitance electrode (11), a light-shielding layer (1) which becomes a black matrix is formed.
2) are laminated. Thereby, the high resistance of ITO is compensated to prevent the deterioration of the charging characteristics, and the light shielding layer (12)
This prevents breakage of the auxiliary capacitance electrode (11) due to the film thickness of. 3 is a plan view of the substrate end of the auxiliary capacitance electrode signal input side, and FIG. 4 is a sectional view taken along the line BB of FIG.

Similar to the pixel portion, the auxiliary capacitance electrode (11) and the light shielding layer (12) are laminated and formed on the substrate (10), and the interlayer insulating layer (13) is sandwiched therebetween to form the substrate (10). The auxiliary capacitance input electrode (14C) is formed in the band along the edge. The auxiliary capacitance input electrode (14C) has an end serving as an auxiliary capacitance input end (14P) to which, for example, a common electrode signal is applied. A capacitance is formed at the opposing portion of the auxiliary capacitance input electrode (14C) and the auxiliary capacitance electrode (11), and the floating auxiliary capacitance electrode (11) is commonly connected to the auxiliary capacitance in series. Thus, the auxiliary capacitance input electrode (14
With the configuration in which the signal is input from P), the auxiliary capacitance can be driven without forming a contact hole in the interlayer insulating layer (13), and the photoetching process can be reduced.

Further, in the present invention, the light-shielding layer (21) is also provided on the counter substrate (20) side to enhance the light utilization efficiency.
The light in the display area that has passed through the light shielding layer (12) on the TFT array substrate (10) side is scattered in the non-display area due to a diffraction phenomenon or the like. The light is not modulated in the portion where the electric field is not formed in the non-display area, and such transmitted light causes a decrease in the contrast ratio. In order to solve this, for example, a method in which the opening is made considerably smaller than the display electrode area to block all unmodulated light can be considered, but this will reduce the aperture ratio. Therefore, in the present invention, the light-shielding layer (12) is provided in the entire area outside the display region on the TFT array substrate (10) side, and also on the counter substrate (20) side, in the region facing the light-shielding layer (12).
A light shielding layer (21) smaller than the light shielding layer (12) is provided. As a result, the diffracted light is reflected between the light-shielding layers (12, 21), guided to the display area, modulated, and then emitted from the opening.

The electric field in the liquid crystal layer (30) has a distribution that spreads slightly outward from the display electrode (14P) toward the common electrode (22). Therefore, in order to transmit diffracted light with a small angle, the opening on the counter substrate (20) side is formed larger than the opening on the TFT array substrate (10) side, and only diffracted light with a large angle is formed. Is blocked and reflected.

Such a liquid crystal display device is manufactured as follows. First, on a transparent substrate (10) such as glass,
ITO is sputtered while covering a band of several hundred μm width at the peripheral portion with a metal mask or the like,
Laminate to a thickness of 0Å. As a result, the auxiliary capacitance electrode (11) is formed on almost the entire area of the substrate. The auxiliary capacitance electrode (11) does not have an electrode at the cutting portion in order to prevent the auxiliary capacitance electrode (11) from being exposed to the cut surface when the large substrate is cut and separated into panels in the final process of manufacturing the substrate. That is, the auxiliary capacitance electrode (11) is prevented from reaching the edge of the substrate after cutting to prevent the auxiliary capacitance electrode (11) from being exposed on the side surface of the panel, and may come into contact with the TAB portion to cause a short circuit or electrostatic discharge. You can avoid typing. It is to be noted that since the positioning of the auxiliary capacitance electrode (11) does not require such high accuracy, patterning is performed using a metal mask.

Then, Cr is sputtered to 20
A light-shielding layer (12) also serving as a black matrix is formed by stacking layers with a thickness of about 00Å and patterning the layers by photoetching to form openings corresponding to the display area. Next, SiO2 is deposited by CVD to 7000-1.
A film having a thickness of 0000Å is formed to form an interlayer insulating layer (13), and the auxiliary capacitance electrode (11) and the light shielding layer (12) are covered. Since the auxiliary capacitance can be formed sufficiently over the entire area of the display electrode (14P), the interlayer insulating layer (13) is thickened to reduce the adverse effect of the auxiliary capacitance electrode (11). That is, the light shielding layer (12) and the drain line (14L)
Applied to the light-shielding layer (12) integrally with the auxiliary capacitance electrode (11) while reducing the parasitic capacitance formed between the light-shielding layer (12) and the gate line (17L) to prevent signal distortion. It prevents the operation of the TFT from being affected by the voltage.

Next, ITO is formed on the interlayer insulating layer (13).
(14) is sputtered to a thickness of about 1000Å and N + a-Si (15N) is sequentially laminated to a thickness of about 200 to 300Å, and both films (14, 15N) are patterned by photoetching. By this, the surrounding 2
A display electrode (14) having a thickness of 3 μm superimposed on the light shielding layer (12)
P) and the display electrode (14P) between the drain lines (1
4L), the source electrode (14P) integrated with the display electrode (14P)
S) and a drain electrode (14D) integrated with the drain line (14L), and an auxiliary capacitance input electrode (14C) at the substrate end.

Then, a-Si is formed by plasma CVD on the substrate on which the source / drain wiring (14) is formed.
(15) is laminated to a thickness of about 500 to 1000 Å, and subsequently SiNX to be the gate insulating layer (16) is laminated to a thickness of 2000 to 4000 Å by plasma CVD.
Next, Al to be the gate wiring (17) is laminated by sputtering to a thickness of about 4000Å. Al, SiNx, a-Si, and N + a-S sequentially laminated in this way
For i, unnecessary portions are removed by etching using the same mask. Thereby, the source and drain electrodes (1
4S, 14D) on N + a-Si (15N), a-Si
(15), gate insulating layer (16) and gate electrode (17
G) is laminated to form a TFT, and a-S
A gate line (17L) made of Al is formed on the laminated body of i and SiNx. Further, a polyimide alignment film (18) is formed on the surface of the pixel portion, and the TFT array substrate is completed.

On one substrate (20), a light shielding layer (21) made of Cr as a black matrix is formed. The opening of the light shielding layer (21) corresponds to the opening of the light shielding layer (12) on the TFT array substrate (10) side and is formed to be large by about 10 μm. This light shielding layer (21)
A common electrode (22) of ITO is formed on the entire surface,
Further, a polyimide alignment film (23) is formed to serve as a counter substrate.

The counter substrate and the TFT array substrate are bonded to each other at their peripheral portions so as to face each other with a sealing material (40), and liquid crystal (30) is injected into the gap to seal the liquid crystal display device. . As described above, in the liquid crystal display device of the present invention, the number of masks required for manufacturing the TFT array substrate is 3, and the cost is low.

[0034]

As is apparent from the above description, according to the present invention, in the liquid crystal display device which can be manufactured by using three masks, the aperture ratio and the auxiliary capacitance are simultaneously increased, and the display quality is improved. did. In particular, it is suitable for a projection type TV such as a projection TV, a bright screen is obtained, and the voltage holding characteristic is not deteriorated even by strong light from the light source, and good display quality is maintained.

[Brief description of drawings]

FIG. 1 is an enlarged plan view of a pixel portion of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a plan view of a substrate end portion of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 4 is a sectional view taken along line BB of FIG.

FIG. 5 is a plan view and a cross-sectional view of a conventional liquid crystal display device.

[Explanation of symbols]

 10, 20 Substrate 11 Storage capacitor electrode 12, 21 Light shielding layer 13 Interlayer insulating layer 14 Source / drain wiring 15 a-Si 16 Gate insulating layer 17 Gate wiring 18, 23 Alignment film 22 Common electrode 30 Liquid crystal 40 Sealant

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (6)

[Claims] 1. A plurality of gate lines and a plurality of drain lines which are arranged to intersect on a first substrate, a plurality of display electrodes which are arranged in a region surrounded by the gate lines and the drain lines, and the gate lines A drain electrode integral with the drain line and a source electrode integral with the display electrode at the intersection of the drain line and the drain line, a semiconductor layer on the region, an insulating layer on the semiconductor layer, and an insulating layer on the insulating layer. A thin film transistor in which an integrated gate electrode is stacked on the gate line, an auxiliary capacitance electrode that faces the display electrode and constitutes an auxiliary capacitance, and is formed over the entire surface of a second substrate and sandwiches a liquid crystal between each of the above. In a liquid crystal display device having a common electrode facing a display electrode in common and forming a display pixel capacitance at each facing portion, the auxiliary capacitance electrode is entirely formed on a substrate. Made transparent conductive layer, a liquid crystal display device, characterized in that opposite the common to the respective display electrodes sandwiching the interlayer insulating layer. 2. The liquid crystal display device according to claim 1, wherein a first light-shielding layer that covers the thin film transistor is formed on the auxiliary capacitance electrode. 3. The liquid crystal display device according to claim 2, wherein a second light-shielding layer is formed on the auxiliary capacitance electrode to cover a peripheral portion of the display electrode. 4. The liquid crystal display device according to claim 3, wherein the second light shielding layer is integrated with the first light shielding layer. 5. The second light-shielding layer is provided over the entire area between the display electrodes, and the second substrate corresponds to the display electrodes in a plan view on the second substrate and surrounds the display electrodes. The third light-shielding layer having an opening larger than the opening of the display electrode excluding the regions shielded by the first light-shielding layer and the second light-shielding layer is formed. 4. The liquid crystal display device according to 4. 6. The liquid crystal display device according to claim 1, wherein the auxiliary capacitance electrode is absent on a peripheral portion of the first substrate.