JPH0799435A - Bus drive system - Google Patents

Abstract

PURPOSE:To provide a bus drive system preventing the occurrence of a bus fight in a bus line and preventing the impedance of the bus line from being high. CONSTITUTION:The bus drive system where output terminals of plural bus drive circuits A10, B10, C10 whose output stage consists of a CMOS transistor(TR) are connected to a common bus line X10 is provided with TRs a11, b11 and inverters a11, b11 being components of a switch circuit connected between sources of P-channel MOS TRs a13, b13 of an output stage of the bus drive circuits and a power supply terminal having been connected to the sources and receiving a potential of the bus line to control the interruption between the sources and the power supply terminal and with a NOR gate Y10 NORing inputs to an output stage of each bus drive circuit and outputting a resulting output to the bus line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus drive system having a plurality of bus drive circuits for transferring data between a plurality of functional blocks via a bus.

[0002]

2. Description of the Related Art FIGS. 5 and 6 are block diagrams showing a conventional example of a bus drive circuit of this type (Japanese Patent Laid-Open No. 3-82).
218). The structure of the bidirectional buffer is shown in FIG. An input buffer 1 is composed of a P-channel MOS transistor TP4 (hereinafter referred to as a transistor TP4) and an N-channel MOS transistor TN4 (hereinafter referred to as a transistor TN4). The input buffer 1 is connected to the bus line BUL1 and inputs signal information from the bus line BUL1. 2 is a P-channel MOS transistor TP3 (hereinafter transistor TP
3) and N-channel MOS transistor TN3
(Hereinafter referred to as a transistor TN3) and a control circuit 2a, which is a three-state output buffer,
It is connected to the bus line BUL1.

The control circuit 2a has an input selection signal C
1, ¬C1 (hereinafter ¬ is the negation of the symbol following ¬ or ¬
(The symbol following "indicates that it is low active") causes the bus line BUL1 to be in an output state, an input state and a high impedance state, or a P-channel MOS transistor TP2 (hereinafter referred to as a transistor TP2).
The level of the signal applied to the gate of is controlled. The transistor TP2 is connected between the power supply VDD and the bus line BUL1.

The transistor TP2 has an input selection signal C
When 1 goes from H to L level, it goes from OFF to ON operation and functions as a pull-up resistor. As a result, the level of the bus line BUL1 is fixed to the level of VDD. Further, the transistor TP2 is turned ON → OFF when the signal C1 goes to L → H level, and the pull-up function is released. As a result, the level of the bus line BUL1 depends on the voltage level applied to the bus line BUL1.

Similarly, in FIG. 6, instead of TP2 in FIG. 5, an N-channel MOS transistor TN2 (hereinafter referred to as transistor TN2) is connected between the ground VSS and the bus line BUL2. As a result, when the input selection signal C2 goes from H level to L level, the transistor TN2
Changes from OFF to ON and functions as a pull-down resistor. As a result, the level of the bus line BUL2 is V
It is fixed at the SS level.

8 and 9 are block diagrams showing another conventional example of the bus drive circuit (Japanese Patent Laid-Open No. 1-27963).
No. 0 publication). FIG. 8 is a block diagram showing the output buffer. An inverter 1 that inverts the logic level of the input signal DT, a first gate circuit 2 that performs a NOR operation of the control signal CN that changes in level in synchronization with the clock signal CK, and the output signal of the inverter 1, and the first gate circuit 2. A second gate circuit 3 that performs a NOR operation on the output signal of the gate circuit 2 and the clock signal CK, and a third gate circuit 3 that performs a NOR operation on the input signal DT, the control signal CN, and the clock signal CK.
, And an N-channel MOS transistor whose source is connected to the first power supply terminal (ground), whose drain is connected to the output terminal TO, and whose gate inputs and outputs the output signal of the third gate circuit 4 Q ₁ and a P-channel MOS transistor Q ₂ whose source is connected to the second power supply terminal (VCC), whose drain is connected to the output terminal TO, and whose gate inputs and outputs the output signal of the second gate circuit 3 It is configured with and.

The control signal CN controls the operation and non-operation of the bus drive circuit. When the control signal CN is L, the control signal CN is in the operation state, and when it is H, both Q ₁ and Q ₂ are in the OFF state and the non-operation state. The control signal CN is synchronized with the clock signal CK and changes at the rising edge of the clock signal CK.

When the clock signal CK is H, Q ₂ is forcibly turned on and the output signal Vo is set to H. Therefore, when shifting from the non-operating state to the operating state, when the clock signal CK rises, the output signal Vo becomes H, the control signal CN becomes L, and the input signal DT is not transmitted after the clock signal CK becomes L. As shown in FIG. 9, the bus drive circuit 10 is connected to the output terminals of the plurality of functional blocks 20A to 20C.
Even when the output terminals of 0 are commonly connected and connected to the next stage, Q ₁ ,
Since Q ₂ does not turn on at the same time, no shoot-through current flows between these bus drive circuits 10.

[0009]

[Patent Document 1] Japanese Patent Application Laid-Open No. 3-82218
Although the flow-through current can be avoided by the technique of bus line pull-up / pull-down disclosed in Japanese Patent Publications (FIGS. 5 and 6), a plurality of buffers are connected by a bus line X ₃ as shown in FIG. When the state is released, a bus fight occurs. In that case, no measures have been taken. If the output of the buffer 2 is H and the output of the buffer 6 is L, the transistor TP3 is on and the transistor TN7 is on, so that a flow-through current flows from the power supply VDD to the power supply VSS as indicated by an arrow.

Further, Japanese Patent Laid-Open No. 1-279630 (FIG. 8,
In 9), it is difficult to design the timing of the clock signal CK and the control signal CN, and the trailing edge of the clock signal CK falls to delay the data propagation time. As for the number of elements, three NOR gates for controlling the clock increase. Regarding the flow-through current, it does not flow when only one control signal is selected, but when two or more control signals are erroneously selected, for example, CNA = L, CNB = L, C in FIG.
When NC = H, DTA = H, DTB = L, DTC = L or H, the P-channel MOS transistor Q ₂ in 10A is turned on and the N-channel MOS transistor Q _{1 in} 10B is turned on, and a flow-through current flows. .

In view of the above problems, it is an object of the present invention to provide a bus drive system capable of preventing the occurrence of bus fight and preventing the bus line from having a high impedance.

[0012]

In the bus drive system of the present invention, the output ends of a plurality of bus drive circuits each having an output stage formed of CMOS are connected to a common bus line, and the output of the bus drive circuit. Dan P channel MO
A switch circuit that is inserted between the source of the S transistor and a power supply terminal connected to the source and that controls the connection between the source and the power supply terminal by using the potential of the bus line as an input; Or a NOR gate for taking the NOR of the input of each of the output stages and outputting the resulting output to the bus line, or for the source and the source of the N-channel MOS transistor of the output stage of the bus drive circuit. A switch circuit that is inserted between the connected power supply terminal and controls the connection between the source and the power supply terminal by using the potential of the bus line as an input, and an output stage of each bus drive circuit, respectively. And a NAND gate for outputting the resulting output to the bus line.

[0013]

[Effect] Even if all the output terminals of the bus drive circuit connected to the bus line become high impedance, the NOR gate or the NAND gate makes the bus line 0 or 1
To one of the logic levels. When any bus drive circuit tries to output an output of a logic level different from the logic level of the bus line set by the NOR gate or the NAND gate, the switch circuit blocks it,
Prevent the occurrence of bus fight.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the bus drive circuit of the present invention.

The drive circuit A ₁₀ receives the data signal A ₁₁ and the control signal A ₁₂ , and outputs the P-channel MOS of the output stage.
A load connected to the bus line X ₁₀ is driven via a transistor (hereinafter referred to as PMOS) a ₁₃ and an N-channel MOS transistor (hereinafter referred to as NMOS) a ₁₄ . In this case, PMOSa ₁₂ is inserted as a switch circuit that cuts the current path between the power supply terminal VDD and the source of PMOSa ₁₃ ,
PM in the inverter a ₁₁ that receives the signal from the bus wiring X ₁₀
It controls OSa ₁₂ .

Drive circuit B_Ten, C_TenDrive circuit
A_TenIt is a circuit similar to and the output is bus wiring X_TenConnected to
ing. Drives D1 and D2 are bus wiring X_TenAnd enter
is doing. Also, NOR gate Y_TenEach drive
A_Ten, B_Ten, C_TenNOR gate a₁₆, B₁₆, ...
Power A₁₃, B₁₃, C₁₃Is input. NAND gate
a ₁₅, NOR gate a₁₆, Inverter a₁₇By data
Signal A₁₁Control signal A₁₂Are controlled according to.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to the truth table shown in FIG. In FIG.
The drive C ₁₀ is omitted for simplicity of explanation. When the bus wiring X ₁₀ is in a normal high impedance state, that is, when the control signal A ₁₂ = 0 and the control signal B ₁₂ = 0, the output A ₁₃ = 0 and the output B ₁₃ = 0, and the NOR gate Y ₁₀ allows the bus wiring to be achieved. X ₁₀ = 1. Therefore, although the PMOS a ₁₂ and b ₁₂ are turned on through the inverters a ₁₁ and b ₁₁ ,
Since the MOSa ₁₄ and b ₁₄ are off, the bus wiring X ₁₀ is 1
Is held at and does not float.

Both control signals A ₁₂ and B ₁₂ are selected (A ₁₂ = 1 and B ₁₂ = 1), and data signals A ₁₁ = 1 and B ₁₁ =
When 0, so-called normal bus fight, the gate outputs A ₁₃ = 0 and B ₁₃ = 1 and the bus wiring X ₁₀ = 0.
The PMOS a ₁₂ and b ₁₂ are turned off, and VDD → a ₁₂ → a ₁₃
The current path of → X ₁₀ → b ₁₄ → GND is cut by the PMOSa ₁₂ . Similarly, when the control signals A ₁₂ = 1 and B ₁₂ = 1 and the data signals A ₁₁ = 0 and B ₁₁ = 1 are used, VDD → b ₁₂ → b ₁₃
The current path of → X ₁₀ → a ₁₄ → GND is cut by turning off PMOSb ₁₂ .

Next, a second embodiment of the present invention will be described with reference to FIGS. This embodiment is constructed based on the same principle as the embodiment of FIG. A switch circuit that disconnects the current path is inserted between the source of the output stage NMOS and GND. The drive circuit A ₂₀ receives the data signal A ₂₁ and the control signal A ₂₂ , and outputs the PMO of the output stage.
The load connected to the bus line X ₂₀ via the Sa ₂₃ and the NMOS a ₂₄ is driven. Insert the NMOSa ₂₂ between the source of the NMOSa ₂₄ and the ground (GND), and connect the bus wiring X _20.
The NMOS a ₂₂ is controlled by the inverter a ₂₁ which receives the signal of.

The drive circuits B ₂₀ and C ₂₀ are drive circuits A
_The circuit is similar to ₂₀ , and the output is connected to the bus wiring X ₂₀ . The NAND gate Y ₂₀ is for each drive circuit A ₂₀ , B
_20, NAND gates a _25, b ₂₅ of the C _20, and an input gate output A _23, B _23, C ₂₃ of .... The data signal A ₂₁ is controlled according to the control signal A ₂₂ by the NAND gate a ₂₅ , the NOR gate a ₂₆ , and the inverter a ₂₇ .

Next, the operation of this embodiment will be described with reference to the truth table of FIG. The drive circuit C ₂₀ is omitted from FIG. 4 to simplify the description. Bus wiring X
₂₀ is the normal high impedance state, that is, control signal A
_{When 22} = 0 and B ₂₂ = 0, the gate output A ₂₃ = 1 and B ₂₃ = 1
Then, the NAND gate Y ₂₀ results in the bus wiring X ₂₀ = 0. Therefore, through the inverters a ₂₁ and b ₂₁ , the NMOS
Although a ₂₂ and b ₂₂ are turned on, the PMOS a ₂₃ and b ₂₃ are turned off, so that the bus wiring X ₂₀ remains 0 and does not float. Both control signals A ₂₂ and B ₂₂ are selected (A
₂₂ = 1 and B ₂₂ = 1) and data signals A ₂₁ = 1 and B ₂₁ = 0, so-called normal bus fight, gate output A ₂₃
= 0, B ₂₃ = 1 and the bus wiring X ₂₀ becomes 1 through the NAND gate Y ₂₀ . Then NMOSa _22, b ₂₂ are turned off, thereby turning off the _{VDD → a 23 → X 20 →} b 24 → b 22 → GND current path in NMOSb _22. Similarly, control signals A ₂₂ = 1 and B ₂₂ = 1 and data signals A ₂₁ = 0 and A ₁₁ = 1
In case of, VDD → b ₂₃ → b ₁₃ → X ₂₀ → a ₂₄ → a ₂₂ → GN
The current path of D is cut off when the NMOS a ₂₂ is turned off.

[0022]

As described above, the present invention is competitive.
Even if the drive output stage PMOS and NMOS are turned off
NOR logical drive Y_TenOr NAND logical drive
Y₂₀Fixed to 1 and 0 with to prevent floating
It As a result, bus wiring X_Ten, X ₂₀Input as dry
The gate is through because the gate potential is 1 and 0 as described above.
No current flows.

Further, even when two or more drives are selected, the current is cut off by the control of the switch circuit, and the through current does not flow through the bus wiring.

Therefore, there is an effect of preventing malfunction such as latch-up due to the flow-through current and increase in current consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a bus drive circuit of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of the embodiment of FIG.

FIG. 4 is a diagram for explaining the operation of the embodiment of FIG.

FIG. 5 is a block diagram showing a buffer circuit in a conventional example (JP-A-3-82218).

FIG. 6 is a block diagram showing another buffer circuit in a conventional example (Japanese Patent Laid-Open No. 3-82218).

FIG. 7 is a block diagram showing a bus configuration of a conventional example (JP-A-3-82218).

FIG. 8 is a block diagram showing a buffer circuit in a conventional example (JP-A-1-279630).

FIG. 9 is a block diagram showing a bus configuration of a conventional example (Japanese Patent Laid-Open No. 1-279630).

[Explanation of symbols]

A ₁₀ , B ₁₀ , C ₁₀ , A ₂₀ , B ₂₀ , C ₂₀ drive circuit A ₁₁ , B ₁₁ , C ₁₁ , A ₂₁ , B ₂₁ , C ₂₁ data signal A ₁₂ , B ₁₂ , C ₁₂ , A ₂₂ , B ₂₂ , C ₂₂ control signals A ₁₃ , B ₁₃ , C ₁₃ , A ₂₃ , B ₂₃ , C ₂₃ gate output D 1, D 2 driver X ₁₀ , X ₂₀ bus wiring Y ₁₀ , a ₁₆ , b ₁₆ , a ₂₆ , b ₂₆ NOR gate Y ₂₀ , a ₁₅ , b ₁₅ , a ₂₅ , b ₂₅ NAND gate a ₁₁ , b ₁₁ , a ₁₇ , b ₁₇ , a ₂₁ , b ₂₁ , a ₂₇ , b ₂₇
Inverter a ₁₂ , b ₁₂ , a ₁₃ , b ₁₃ , a ₂₃ , b ₂₃ P-channel MOS transistor (PMOS) a ₁₄ , b ₁₄ , a ₂₂ , b ₂₂ , a ₂₄ , b ₂₄ N-channel MOS transistor (NMOS)

Claims (4)

[Claims] 1. A bus drive system in which output terminals of a plurality of bus drive circuits each having an output stage composed of CMOS are connected to a common bus line, wherein a source of a P-channel MOS transistor in an output stage of the bus drive circuit is used. A switch circuit that is inserted between the power supply terminal connected to the source and controls the connection and disconnection between the source and the power supply terminal by using the potential of the bus line as an input, and an output stage of each bus drive circuit. A bus drive system comprising: a NOR gate that takes the NOR of each input and outputs the output of the result to the bus line. 2. A bus drive system in which the output ends of a plurality of bus drive circuits each having an output stage composed of CMOS are connected to a common bus line, wherein the source of an N-channel MOS transistor in the output stage of the bus drive circuit is used. A switch circuit that is inserted between the power supply terminal connected to the source and controls the connection and disconnection between the source and the power supply terminal by using the potential of the bus line as an input, and an output stage of each bus drive circuit. A bus drive system, comprising: a NAND gate that takes a NAND of each input and outputs the output of the NAND to the bus line. 3. An output stage comprising a P-channel MOS transistor connected between the first power supply and the output end, and an N-channel MOS transistor connected between the second power supply and the output end. However, in a bus drive system in which a bus drive circuit for inputting a data signal and a control signal is connected to the same bus line via a plurality of output terminals, each bus drive circuit is provided in each of the bus drive circuits. When the input control signal is active, the logic level of the data signal is inverted and applied as the first gate drive signal to the gate of the N-channel MOS transistor in the output stage. When the input control signal is inactive, A first gate circuit that sets a first gate drive signal to a logic level 0, and a control circuit that is provided in each of the bus drive circuits and that receives the input signal. When the signal is active, the logic level of the data signal is inverted and applied as a second gate drive signal to the gate of the P-channel MOS transistor in the output stage. When the input control signal is inactive, the second A second gate circuit for setting a gate drive signal to a logic level 1, and a P-channel MOS transistor at the output stage and a first power supply, which are respectively provided in the bus drive circuits and when the output terminal is at a logic level 0. A bus drive system comprising: a switch circuit; and a NOR gate that takes the NOR of the first gate drive signal output from each of the bus drive circuits and outputs the result to the bus line. 4. An output stage comprising a P-channel MOS transistor connected between the first power supply and the output terminal, and an N-channel MOS transistor connected between the second power supply and the output terminal. However, in a bus drive system in which a bus drive circuit for inputting a data signal and a control signal is connected to the same bus line via a plurality of output terminals, each bus drive circuit is provided in each of the bus drive circuits. When the input control signal is active, the logic level of the data signal is inverted and applied as the first gate drive signal to the gate of the N-channel MOS transistor in the output stage. When the input control signal is inactive, A first gate circuit that sets a first gate drive signal to a logic level 0, and a control circuit that is provided in each of the bus drive circuits and that receives the input signal. When the signal is active, the logic level of the data signal is inverted and applied as a second gate drive signal to the gate of the P-channel MOS transistor in the output stage. When the input control signal is inactive, the second A second gate circuit for setting a gate drive signal to a logic level 1, and each of the bus drive circuits, which separates the N-channel MOS transistor of the output stage from the second power supply when the output terminal is at the logic level 1. A bus drive system comprising: a switch circuit; and a NAND gate that takes a NAND of the second gate drive signal output from each of the bus drive circuits and outputs the result to the bus line.