JPH0798995A - Linear feedback shift register - Google Patents

Abstract

PURPOSE:To generate plural longest system patterns different from each other in a linear feedback shift register (LFSR) used as a pseudo random pattern generator in a built-in self test (BIST) circuit. CONSTITUTION:On the way of the feedback loop 3 of the LFSR, a switch control system 10 is provided. In the switch system 10, a switch 11 is placed between fourth, fifth flip-flops 1, 1 and between with the feedback loop 3. Further, the switch 12 is placed between fifth, sixth flip-flops 1, 1 and between with the feedback loop 3. The switches 11, 12 become ON, OFF inverse states each other by an inverter gate 13. By a selection signal S1 to the switch control system 10, when the switch 11 is turned ON, and the switch 12 is turned OFF, the longest system pattern with four bits length is generated. Further, when the switch 11 is turned OFF, and the switch 12 is turned ON, the longest system pattern with eight bits length is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a built-in self test (Bu
ilt In Self Test Hereinafter referred to as “BIST”. ) Linear feedback shift register (Liner Feed-back Sh
ift Resister Hereinafter referred to as "LFSR". ) Is related to the circuit configuration.

[0002]

2. Description of the Related Art A conventional LFSR, as shown in FIG.
The flip-flop 1 for the number of bits of the pseudo-random pattern to be generated and the exclusive OR gate 2 are provided, and the flip-flop 1 at the position corresponding to the predetermined number of bits branches so as to return to the first flip-flop 1. The feedback loop 3 is configured. The flip-flop 1 at the bit position to be fed back is determined based on the primitive polynomial according to the code theory. And
The LFSR can generate 2 ⁿ -1 types of pattern signals excluding all 0s in a pseudo-random manner once every 2 ⁿ -1 times of clock application.

Here, n is the bit length of the LFSR,
This kind of LFSR is the LFS that generates the longest sequence pattern.
Called R. For example, in order to generate a 4-bit longest series pattern, feedback is applied from the fourth and third flip-flops to the least significant bit (first flip-flop), and as shown in FIG. Feeds back to the least significant bit from the eighth, seventh, fifth and third flip-flops 1.

In FIGS. 4A and 4B, the BIST circuit having the LFSR is mounted on the LS in which the test target modules M1 and M2 having 4-bit and 8-bit input terminals are mounted.
An example applied to an I chip is shown. As shown in FIG. 4A, the test target module M1 is connected to a 4-bit long LFSR 4 for generating a pattern and a compressor 5 for compressing an output response pattern. Module to be tested M
2 is an 8-bit LFSR6 for generating a pattern
And the compressor 7 for compressing the output response pattern are connected. Further, the test clock CK and the select signal for selecting the modules M1 and M2 are sent to the LFSRs 4 and 6 and the compressors 5 and 7 by a control circuit (not shown).

[0005]

The conventional BIST circuit described above requires two types of LFSRs having different bit lengths. Therefore, when the number of test target modules having different input bit numbers increases to three or more, it is necessary to prepare the LFSR having the bit length corresponding to each test target module. Therefore, there is a problem that the gate scale on the LSI increases.

On the other hand, as shown in FIG. 5, a configuration is conceivable in which the LFSR 6 having an 8-bit length is connected to the test target module M2, and 4 bits of the LFSR 6 are connected in parallel to the test target module M1 having an input bit number of 4. To be However, in this configuration, although the test module M4 is 2 ⁸ -1 or patterns in the clock application of 2 ⁸ -1 times can be applied once, the clock application of 2 ⁴ -1 times the test module M2 Since the same pattern appears several times, the LFSR cannot generate the longest series pattern for the test target module M2. Therefore, to apply 2 ⁴ −1 types of patterns, 2 ⁴ −
Since it is necessary to apply the clock at least once, there is a problem that the test time becomes long and the error oversight rate in the compressor increases by applying the same pattern twice or more.

An object of the present invention is to provide an LFSR that generates two or more longest series patterns to reduce the gate size of an LSI chip and the error-miss rate.

[0008]

According to the present invention, in an LFSR for a pseudo random pattern generator of a BIST circuit,
A linear feedback shift register is configured by providing a switch mechanism that opens and closes between the flip-flop output and the feedback loop to switch the branch position of the feedback loop so as to selectively output a plurality of patterns of different bit numbers. I did it.

[0009]

In the linear feedback shift register of the present invention, the switch mechanism is opened / closed by inputting a selection signal or the like to form a necessary feedback loop,
For example, a single circuit generates a plurality of longest series patterns having different 4-bit length or 8-bit length. Therefore, it is not necessary to individually prepare an LFSR corresponding to the number of input bits even for an LSI chip having a plurality of test target modules having different input bit lengths.

[0010]

Embodiments of the present invention will be described with reference to the drawings.
In the figure, the same components as those of the related art are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, the LFSR of this embodiment is
An example of the configuration for generating two types of longest sequence patterns of 4-bit length and 8-bit length is shown. In the figure, a switch control system 10 is provided on the way of the feedback loop 3. In the switch control system 10, the switch 11 includes the fourth and fifth switches.
The switch 12 is located between the flip-flops 1 and 1 and the feedback loop 3, and the switch 12 is located between the fifth and sixth flip-flops 1 and 1 and the feedback loop 3. The switches 11 and 12 are configured such that the inverter gate 13 inputs the reverse level signal. Therefore, depending on the state of the selection signal S1, the switches 11 and 12 are in the ON and OFF opposite states.

The LFSR of this embodiment is a switch control system 1
When the selection signal S1 is input to 0, the selection signal S1 changes to Hi.
In case of gh level, switch 11 is ON, switch 12
Is turned off, the equivalent circuit shown in FIG. 2 (A) is obtained, and the longest series pattern of 4 bits is generated.
On the other hand, when the selection signal S1 is at low level, the switch 1
Since 1 is OFF and switch 12 is ON, as shown in FIG.
An equivalent circuit as shown in (B) is generated, and a longest series pattern of 8-bit length is generated. As described above, depending on the selection signal S1 to the switch control system 10, the 4-bit length or 8
The longest sequence pattern of bit length can be easily switched.

In the above embodiment, 4 bits and 8 bits are adopted as the two different bit lengths, but other bit numbers can be applied as long as the bit numbers to which feedback is applied are common. it can.

[0014]

According to the present invention, in the LFSR for the pseudo random pattern generator of the BIST circuit, the flip-flop output and the feedback loop are opened and closed to selectively output a pattern having a plurality of different bit numbers. Since the linear feedback shift register is configured by providing the switch mechanism for switching the branch position of the feedback loop, by switching the switch so as to change the branch position of the feedback loop, one LF can be obtained.
Since a plurality of longest series patterns having different bit lengths can be generated by SR, LFSRs corresponding to the respective input bit numbers are individually provided to LSI chips having a plurality of test target modules having different input bit lengths. There is no need to provide it, the gate scale can be reduced,
This has the effect of reducing the false negative rate.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an LFSR according to the present invention.

FIG. 2A is a circuit diagram of an equivalent circuit of a 4-bit LFSR, and FIG. 2B is a circuit diagram of an equivalent circuit of an 8-bit LFSR.

FIG. 3 is a circuit diagram of a conventional 8-bit LFSR.

FIG. 4A is a block diagram of a conventional 8-bit BIST circuit, and FIG. 4B is a block diagram of a 4-bit BIST circuit.

FIG. 5 is a block diagram of a conventional 4-bit and 8-bit dual-purpose BIST circuit.

[Explanation of symbols]

 1 Flip Flop 2 Exclusive OR Gate 3 Feedback Loop 10 Switch Control System 11 Switch 12 Switch 13 Inverter Gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 11/22 310 B G11C 19/00 Z 29/00 303 D 6866-5L

Claims (1)

[Claims] 1. A linear feedback shift register for a pseudo random pattern generator of a built-in self-test circuit, wherein a flip-flop output and a feedback loop are opened / closed to selectively output a pattern having a plurality of different bit numbers. A linear feedback shift register, wherein a switch mechanism for switching the branch position of the feedback loop is provided in the.