JPH0797768B2 - Hybrid exchange type digital signal transmission system - Google Patents

Description

The present invention relates to a hybrid exchange type digital signal transmission system, and more particularly to a hybrid exchange capable of performing data exchange by packet exchange, circuit exchange or hybrid exchange using a communication cable. Type digital signal transmission system.

(Prior Art) With the spread of electronic computers and the development of digital signal processing technology, data communication in which a communication system and a data processing system are combined to process information online is in the limelight. In particular, in a small-scale communication system such as in-house communication carried out on the premises of government offices, companies, etc., because of its economical efficiency, reliability, and high transmission efficiency, a communication method in a packet form using a communication cable such as a coaxial cable is used. Has been particularly noticeable.

In this packet type communication system, a communication cable for bidirectional transmission is laid in a laboratory or the like, and a large number of stations (personal stations) are connected thereto. Then, each station transmits a message divided into data blocks of 1000 to 2000 bits, for example. Addresses, serial numbers, and other headers are added to the message. In this communication system, network self-confidence is a passive transmission medium without any control function, and control is completely distributed to each station. Therefore, each station confirms the availability of the transmission path, accesses the channel, and starts transmitting the message. If a collision with another packet occurs during transmission, both stations stop transmitting. Stations that have stopped transmitting will attempt to retransmit the message after a random wait time.

By the way, in this communication system, each station arbitrarily starts data transmission, and therefore packets may collide on the same transmission path. Therefore, there is a problem that the transmission delay time is not constant, which is unsuitable for real-time transmission such as conversational voice communication in which importance is attached to a real-time transmission / reception correspondence. Of course, this problem can be solved by permanently installing a master station and having each station make a reservation for channel access. However, in such a case, when the master station fails, data communication becomes impossible and the reliability of the system deteriorates.

In order to improve the above points, a digital signal transmission system called Modified Ethernet has been proposed and disclosed in Japanese Patent Laid-Open Publication No. 57-154956.

In this method, a large frame (frame) that is periodically repeated on the time axis is further divided into a plurality of small frames (blocks) on the time axis, and packet communication opportunities are given to each station (personal station) in units of these blocks. give. This allows each station to have equality in using the empty blocks, and in addition, if it wants to occupy a given block for the time required for the signal transmission, it will have an opportunity to transmit the signal each time the frame is repeated. Is given on a regular basis. That is, real-time transmission is possible.

FIG. 9 shows a frame structure of a signal in this modified Ethernet. A frame that is periodically repeated on the time axis is made up of N blocks # 0 to #N. Each block has various bit strings b ₁ shown below.
It is constituted by ~b _9.

b ₁ : Rearward guard time b ₂ : Preample b ₃ : Address bit b ₄ : Distance sign bit b ₅ : Control bit b ₆ : Information bit b ₇ : Check bit b ₈ : End flag b ₉ : Front guard time , Each of the bit strings b _{2 to} b ₅ , b ₇ , and b ₈ are necessary to form a packet and are collectively referred to as overhead (additional) bits. The two types of bit strings b ₁ and b ₉ are
These are collectively called the guard time. The guard time is a vacant bit string for avoiding a situation where the packets of each block are partially overlapped due to the adjacent packets due to the delay time generated when the packets propagate on the coaxial cable. This includes a backward guard time b ₁ to protect packets located behind it and a forward guard time to protect packets located in front of it.
There are two types, b ₉ .

Although the case where one block constitutes one packet has been described above, there are cases where a packet is constituted by a plurality of consecutive blocks. Also in this case, the contents of the packet are the same. Such a packet can be efficiently transmitted when the amount of information is large. Further, it is possible to reduce packet collisions as compared with the case where the packets are divided and transmitted.

FIG. 10 shows an outline of a communication system using the modified Ethernet having the frame structure described above. The coaxial cable 41 laid as a transmission line in this communication system is an impedance matching terminator having a resistance value equal to the characteristic impedance at both ends.
Connected to 42. Each station has a T connector (tap)
It is connected to the coaxial cable 41 through 43 ₁ ~43n. Since all of these stations have basically the same structure, only the main part of the A station connected to the T connector 43 ₁ is shown in the figure.

Each station has a user device 44 equipped with a computer and a telephone. The user device 44 includes a transmitter 45 for transmitting a packet-unit digital signal to another station, a receiver 46 for receiving the same packet-unit digital signal transmitted from another station, and a terminal. A terminal controller 47 and the like for controlling are provided. Of these, the signal output from the transmitter 45 is temporarily stored in the transmission buffer memory 51. Then, with a clock signal equal to the transmission speed on the coaxial cable 41 which is a transmission medium, it is collectively read at a predetermined time. The read signal is converted into a predetermined packet by the transmission logic circuit 52. Then, after passing through the transmission buffer amplifier 53, the coaxial cable 4 is passed through the T connector 43 _1.
One is sent up.

On the other hand, all the packet signals transmitted on the coaxial cable 41 are received by the reception buffer amplifier 54 through the T connector 43 ₁ . The reception logic circuit 55 selects only a packet addressed to itself from the received packets and temporarily stores it in the reception buffer memory 56. The stored signal is continuously read by the receiver 42 using a predetermined clock. As a result, a reception output signal is obtained.

Signals are transmitted and received as described above, and the transmission clock used for them is generated from the transmission clock oscillator 57. The frame counter 58 divides the transmission clock to generate a frame timing signal 59 and a block timing signal 60 which respectively indicate a frame timing and a block timing. The transmission control circuit 61 is
The terminal control unit 43 is controlled by the reception signal addressed to itself received from the reception logic circuit 55, and the transmission logic circuit 52 is controlled in accordance with the instruction of the terminal control unit 43.

Further, the collision detection circuit 62 detects, when the packet signal is transmitted in the block selected by the own station, whether or not a collision occurs with the packet signal of another station. Further, the transmission control circuit 61 of each station is provided with a memory (not shown) indicating the exclusive status of each block in the frame, and based on the packet signal of each station received by the reception buffer amplifier 54, Registration is to be done. A station which intends to send a new signal searches for an empty block in the frame established using this memory and sends a packet signal to it.

In this modified Ethernet communication system, it is necessary for each station to establish frame synchronization and block synchronization. Regarding frame synchronization, one of the transmitting stations takes the initiative. This station will be called the master station. The master station sends a packet signal based on the frame timing signal 59 and the block timing signal 60 output from the frame counter 58 of its own station. This packet signal is received by all stations via the coaxial cable 1. When each station packet signal is received, the master management circuit 63 resets the frame counter 58 of the own station at a predetermined timing. This establishes frame synchronization in all stations. Each station other than the master station obtains the block timing signal 60 from the frame counter 58 which is periodically reset, thereby establishing block synchronization.

(Problems to be Solved by the Invention) As described above, this modified Ethernet system enables circuit switching services and enables real-time voice transmission and image transfer requiring large-capacity data transfer. It was However, computers often handle small-capacity code data files, and if such files are transferred by a circuit switching system, there is a problem that redundancy is increased and an effective transmission path cannot be expected.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to realize circuit switching and packet switching on the same transmission line and provide a wide range of services.

(Means and Action for Solving Problems) A feature of the present invention is that a digital signal to be transmitted is fixedly positioned in a frame as a frame on a time axis in which a transmitted digital signal is periodically repeated. At the same time, one or a plurality of stations that are actually transmitting signals among the stations connected via taps on this communication cable form blocks that are further divided in the frame as small frames on the time axis. In a multi-station communication network that occupies a unit and transmits time-division multiplexed digital signals, the station that first makes a transmission request and becomes the master station has a master packet of one block length at the beginning of one frame. The other station establishes system timing synchronization with the master station, and the circuit-switched packet and the packet-switched packet have their identification code in the control bit in the packet. Then, the state of each block in one frame is registered in the line state storage means on the basis of the identification code, and when there is a request for transmission of a circuit switching packet, the contents of the line state storage means are checked to check the line state. Find the last block in the exchange area and assign the next block,
When a packet switching packet transmission request is made, a packet switching area is found based on the contents of the line state storage means, and the first block of the packet switching area or a randomly selected block is allocated and transmitted. By referring to the contents of the circuit storing means, the circuit switching packets are always formed in the front block in the frame so that the circuit switching area is formed, and the area other than the block occupied by the circuit switching packet in one frame is packetized. The point is that it was made an exchange area.

(Example) Hereinafter, the present invention will be described with reference to an example. FIG. 1 shows a block diagram of a hybrid exchange of one embodiment of the present invention.

In the figure, reference numeral 1 denotes a transmission line having terminators 2 for impedance matching at both ends, and assuming that a transmission signal exists on the transmission line 1, the transmission signal is transmitted via a T connector (tap) 3 to a reception amplifier 4 Entered in. The signal input to the reception amplifier 4 is amplified and waveform-shaped, and then sent to the decoder 5. The signal input to the decoder 5 is decoded into a binary signal consisting of 1s and 0s.

The decoded signal is used for the preamble end detection circuit 6,
The packet is input to the local station addressed packet detection circuit 7, the reception buffer memory 8 and the packet type determination circuit 9.

The preamble end detection circuit 6 detects the end portion (end portion) of the preamble b ₂ (see FIG. 2) which is one component of the packet of each block. The preamble end detection signal 6a is sent to the clear pulse generation circuit 10 and the memory writing circuit 11. When the preamble end detection signal 6a is input from the preamble end detection circuit 6 when the signal from the counter reset enable generation circuit 13 is enabled, the clear pulse generation circuit 10 outputs the preamble detection signal 6a as shown in FIG. As shown, delay to the end of the block and output a clear pulse 10a at the end of the block. This delay time can be calculated from the distance code bit b ₄ of the master packet and the distance information of the own station.

The own-station-destined packet detection circuit 7 detects whether or not the packet received from the address bit b ₃ which is one component of the packet is destined for the own station, selects only the packet signal addressed to the own station, It is temporarily stored in the reception buffer memory 8. The stored signal is continuously read by the receiver 12 of the user circuit using a predetermined clock. As a result, a reception output signal is obtained.

The packet type discrimination circuit 9 uses control bits in the packet.
From the signal put in b ₅ , whether it is a master packet or not,
And whether it is a circuit switched packet or a packet switched packet. The master packet detection signal 9a output from the packet type determination circuit 9 is sent to the counter reset enable generation circuit 13, and the circuit switching / packet switching determination circuit 9b is sent to the memory writing circuit 11. As will be described later, the memory writing circuit 11 stores the discrimination code for the line switching and the packet switching in a predetermined area of the line state storage device 17. The line status storage device 17 is
The storage area has at least the number of blocks in one frame.

The clock generation circuit 18 generates a clock which is the basis of the device of this embodiment. The bit counter 19 counts the clock and inputs the clear pulse 10a from the clear pulse generation circuit 10.
The counter is a counter that is cleared by 1. When a number of clocks corresponding to one block is counted, a carry signal is sent to the block counter 20 and the transmission timing generation circuit 21.
The block counter 20 is a counter that counts the carry signal and returns to 0 when the count value reaches a predetermined preset value (for example, 215). When it is cleared by the clear pulse 10a from the clear pulse generation circuit 10, for example,
It has a value of 1. The count value of the block counter 20 is the bus
It is sent to the memory write circuit 11, the counter reset enable generation circuit 13 and the comparator 22 through 20a.

The carrier detection circuit 23 and the collision detection circuit 24 perform carrier detection and collision detection by looking at the level of the transmission signal amplified by the reception amplifier 4, respectively. The carrier detection signal 23a is sent to the memory writing circuit 11, and the collision signal 24a is sent to the memory writing circuit 11, the packet switching interface 15,
It is sent to the circuit switching interface 16 and the transmission logic circuit 25. The packet switching interface 15 and the circuit switching interface 16 provide the terminal controller 26 of the user circuit with information indicating whether the packet addressed to the local station detected by the local station addressed packet detection circuit 7 is a circuit switched packet or a packet switched packet. At the same time, the transmission request signal and the transmission end signals 15a and 16a output from the terminal controller 26 at the time of transmitting the data packet are transmitted to the transmission block selecting means 27.

When there is a transmission request from the user circuit, the transmission block selection means 27 looks at the contents of the line state storage device 17 read by the memory reading circuit 28, and in the transmission request by circuit switching, the last block of the circuit switching area. And register the next block in register 29. On the other hand, if it is a transmission request by packet switching, a packet switching area is found based on the contents of the line state storage device 17 sent from the memory reading circuit 28, a block in the area is selected by, for example, a random number, and The block transmitted by the station is registered in the register 29. The comparator 22 compares the block number sent from the block counter 20 with the block number registered in the register 29, and if they match, the transmission enable signal 22
Send a to the transmission logic circuit 25.

The overhead writing device 30 receives overhead signals (b _{2 to} b ₅ , b ₇ , in FIG. 2) corresponding to the signal from the transmission block selecting means 27.
b ₈ ) is created. Signal identifying signal a transmission request is whether by or packet switching by the circuit switching, and Mashita whether signal identifying the are included in the control bit b _5. This overhead is added to the data sent from the transmitter 32 held in the transmission buffer memory 31.

When the output signals from the transmission timing generation circuit 21 and the comparator 22 are input to the transmission logic circuit 25, the signal of one block held in the transmission buffer memory 31 is transmitted to the transmission line 1 via the encoder 33 and the transmission amplifier 34. Read out all at once with a clock signal equal to the transmission rate.

The above is a schematic configuration description of reception and transmission of the station device of the present embodiment.

FIG. 3 illustrates the definition of the area according to the present invention. One frame is divided into a circuit switching area and a packet switching area. The circuit switching area is defined as an area in which circuit switching is performed and the next block, and the packet switching area is defined from the block next to the circuit switching area. Define up to the last block of the frame. In the example of FIG. 2, the 0th block, the 1st block and the 2nd block are the circuit switching areas, and the third block to the end of one frame are the packet switching areas. In the figure, there is a B station packet in the mth block of the packet switching area, and
The state where there is a C station packet in the block is shown.

The operation of this embodiment will be described in detail below.

The operation when the station device makes a packet transmission request will be described separately in (1) when there is already a master packet on the transmission path 1 and (2) when there is no master packet on the transmission path 1. For convenience of explanation, the operation will be described by focusing on the station apparatus in FIG. 1 (hereinafter referred to as the A station apparatus), but since the other station apparatuses also have the same configuration as the A station apparatus, they are the same. It is clear that the above operation is performed.

(1) When there is already a master packet on the transmission path 1 (when the station A that has made a transmission request becomes a slave station) When the station shown in FIG. 1 is started (when the power switch is turned on)
It is assumed that the packet P as shown in FIG. 4 (a) is transmitted on the transmission line 1. These packets are input to the A station device through the T connector (tap) 3. The packet is amplified and waveform shaped by the reception amplifier 4, and then encoded by the decoder 5. The encoded packet is input to the preamble end detection circuit 6 and the preamble end is detected. The preamble end detection signal 6a is detected at the timing shown in FIG. 4 (b).

When the power switch of the station device is turned on, the counter reset enable generation circuit 13 outputs the enable signal as shown in FIG. 4 (c), so that the preamble end signal 6a input to the clear pulse generation circuit 10 is Delayed until the end of the block to which the preamble belongs,
It is output from the clear pulse generation circuit 10 as a clear pulse 10a. The output timing of this clear pulse is as shown in FIG. 4 (d). When the clear pulse 10a is output, the bit counter 19 and the block counter 20 are cleared, the bit counter 19 is 0, and the block counter 20 is
Becomes 1.

Now, when the station A device receives the master packet MP1,
The packet type discrimination circuit 9 detects from the control pit that the received packet is a master packet, and outputs a master packet detection signal 9a (Fig. 4 (f)). When this master packet detection signal 9a is input to the counter reset enable generation circuit 13, the counter reset enable generation circuit 13 changes its output to disable. Therefore, after the master packet is detected, the clear pulse generation circuit
10 does not output the clear pulse. Therefore, the bit counter 19 and the block counter 20 are not cleared based on the preamble end signal 6a,
Free run is performed based on the clock output from the clock generation circuit 18.

The bit counter 19 outputs a carry when the clock corresponding to one block is counted. As a result, the block counter 20 counts up by one. The block counter 20 is designed to return to a count value of 0 when it reaches a count value (for example, 215) equal to the number of blocks forming one frame, and the block on the output side line of the block counter 20 is a block counter. Since the count value of 20 is always output, the block counter
When 20 returns to 0, 0 is sent to the output line until the next carry is input to the block counter 20.

The counter reset enable generation circuit 13 outputs an enable signal when the output of the block counter 20 is 0 after being disabled by the first master packet MP1, and outputs a disable signal when the output of the block counter 20 is other than 0 (fifth).
See FIG. (C)).

Therefore, as described above, the block counter 20 has a count value equal to the number of blocks constituting one frame,
When it returns to 0 by the next carry signal from the bit counter 19,
The counter reset enable generation circuit 13 outputs an enable signal. At this point, the next master packet MP
When 2 coincides with the time when it is input to the A station device and the master packet MP2 is input to the A station device, a clear pulse 10a based on the preamble end signal 6a of the master packet MP2 is output from the clear pulse generation circuit 10. It is output and clears the bit counter 19 and the block counter 20.

In this way, the station A device synchronizes with the master station that is sending the master packet. A specific circuit of the counter reset enable generation circuit 13 that outputs the counter reset enable signal as described above will be described in detail later.

Next, the operations of the memory writing circuit 11 and the line state storage device 17 will be described with reference to the time chart of FIG. The count value (FIG. 4 (e)) which is the output of the block counter 20 is input to the memory writing circuit 11. The memory writing circuit 11 accesses the line state storage device 17 using this count value as an address. Further, the memory write circuit 11 has a carrier detection signal 23 output from the carrier detection circuit 23.
a, a collision detection signal 24a output from the collision detection circuit 24, a preamble end signal 6a output from the preamble end detection circuit 6, a master packet, a circuit-switched packet, and a packet-switched packet output from the packet type determination circuit 9 Identification signals are input, and these signals are written to the address of the line state storage device 17 through the memory writing circuit 11.

FIG. 5 shows a conceptual diagram of data stored in the line state storage device 17. In the figure, # 0 to # 215 are addresses, CS is a carrier detection signal, C is a collision detection signal, PE is a preamble end signal, and the remaining bid D is a packet identification signal.

Next, when there is a transmission request from the terminal controller 26 of the user circuit of the station A device, it is determined that this transmission request is a packet switching transmission request via the packet switching interface 15.
On the other hand, a transmission request by circuit switching is output via the circuit switching interface 16. This transmission request signal is input to the transmission block selection means 27. At the same time or almost at the same time, data is sent from the transmitter 32 to the transmission buffer memory 31 at an appropriate timing.

When the transmission block selection means 27 receives the signal of the transmission request,
From the information in the line status storage device 17 read by the memory reading circuit 28, the block to be transmitted by the local station is determined. Since this operation is performed by software, it will be described with reference to the flowchart of FIG.

When the power switch of the station A device is turned on, the sending block selecting means 27 starts its operation, and by referring to the information of the line state storage device 17 read from the memory reading circuit 28, one frame period It is checked whether or not there is a master packet on the transmission path between them (steps S1 and S2).
If there is a master packet, the process proceeds to step S5.

In step S5, it is determined whether or not there is a packet switching transmission request. If yes, line status storage
Search the packet switching area from 17 and find the block in that area with a random number and write it in the register 29 (step S
6). The packet switching area is obtained by referring to the data area D (see FIG. 5) in the line status storage device 17.

When step S5 is NO or when step 1 of step S6 is completed, it is determined whether the station A device has transmitted a circuit switching packet in the previous frame (step S7). If the station A device is transmitting the circuit-switched packet in the previous frame, the process proceeds to the next step S8, in which the station transmits from the block before the block transmitted by the station itself, in other words, the 0th block of the master packet. It is judged whether or not there is a block whose transmission has been stopped by the time the selected block is reached by referring to the data area D of the line state storage device 17. If there is a block whose transmission has been stopped, the block number that has been moved forward by the number of free blocks is written to the register 29 (step S9). At this time, the block number is 0
Then, I realize that my station has become the master station. on the other hand,
If there is no block whose transmission is stopped by the clock before the block transmitted by the own station, the same block number as the previous one is written in the register 29 (step S10).

Next, it is determined whether or not there is a transmission request for circuit switching (step S11). When there is a transmission request for circuit switching, the last block sent from the circuit state storage device 17 in the circuit switching area is searched for, and the next block is written in the register 29 (step S12). When the process of step S12 is completed or when there is no transmission request for circuit switching in step S11, the process proceeds to step S13, and the processes of steps S5 to S12 are repeated while the power switch is on.

By the above processing, when there is a transmission request for circuit switching, the block number next to the last block in the circuit switching area is written in the register 29, and when there is a transmission request for packet switching, the block switching area The block number is selected by a random number and written in the register 29.

Again, description will be made with reference to FIG. When a block signal for transmission is written in the register 29, the block number is compared with the block number sent from the block counter 20 by the comparator 22, and if they match, a match signal 22a is sent to the sending logic circuit 25. When the coincidence signal 22a is input, the transmission logic circuit 25 sends the transmission packet stored in the transmission buffer memory 31 to the transmission timing generation circuit 21.
It is sent at the transmission timing created in. In the transmission buffer memory 31, the overhead sent from the overhead writing device 30 and the data sent from the transmitter 32 are combined to form a transmission packet of a predetermined format.

(2) When there is no master packet on the transmission line 1 (when the A station device that has made the transmission request becomes the master station) The transmission block selection means 27 detects that there is no master packet on the transmission line 1. It That is, in the processing of steps S1 to S3 in FIG. 6, it is determined whether or not a master packet appears on the transmission path until a transmission request is made, and if there is no master packet, the own station becomes the master station. Prepare. Specifically, in step S4, the master packet transmission block, for example, the 0th block is written in the register 29. It also sends a signal indicating that it has become the master station to the overhead writing device 30. Then, when the output value of the block counter 20 becomes 0 and the transmission of the master packet from the station A device succeeds, a signal indicating that the station has become the master station is sent to the counter reset enable generation circuit 13.

When the counter reset enable generation circuit 13 receives the signal indicating that it has become the master station from the transmission block selection means 27, it thereafter always outputs the disable signal 13a as shown in FIG. Therefore, the clear pulse is not output from the clear pulse generation circuit 10, and the bit counter 19 and the block counter 20 are not cleared. Therefore, the block counter 30 repeats the operation of returning to the zero count value when the self-confidence count value reaches the preset maximum value (for example, 215). That is, A
The station device will generate the synchronization signal by itself. On the other hand, the overhead writing device 30 sets the flag of the master packet to the control bit of the packet.

As described above, when the 0th block is written in the register 29, the comparator 22 compares the block number of this register 29 with the block number sent from the block counter 20, and if they match, the coincidence signal 22a is output. Output to the transmission logic circuit 25. When the transmission logic circuit 25 receives the coincidence signal 22a, the master packet stored in the transmission buffer memory 31 is passed through the encoder 33, the transmission amplifier 34 and the T connector (tap) 3 by the same operation as described in (1) above. It is sent to the transmission line 1.

In this way, the station A device becomes the master station and the data packet is transmitted.

In this embodiment, once the station A device becomes the master station, even if there is no data to be transmitted from the station A device, the power switch of the station A device is turned off and the master station is stopped until the operation is stopped. It is added that packets are sent out.

Next, the counter reset enable generation circuit of the A station device
One specific circuit example of 13 will be described with reference to FIG. As shown in the figure, the counter reset enable generation circuit 13 is a register that stores the master block number, for example, 0.
13b, a value held in the register 13b is compared with the count value from the block counter 20, and when they match, a comparator 13c that outputs a match signal, a first flip-flop 13d, a second flip-flop 13e, and a D flip-flop 13f. 13f and illustrated gate circuits 13g to 13j.

In this circuit, when the power switch of the station A device is turned on, the initial set signal is input to the reset terminals of the first and second flip-flops 13d and 13e and the D flip-flop 13f and reset. Therefore, the output of the first flip-flop 13d becomes L level, the Q output of the D flip-flop 13f becomes H level, and the output signal level of the AND gate 13g becomes H. This means enable, and is output to the clear pulse generation circuit 10 via the OR gate 13h.

Now, as shown in FIG. 4, when the master packet detection signal 9a is input to one input terminal of the AND gate 13i, this signal 9a is in the open state.
To set the first flip-flop 13d. As a result, the AND gate 13g is closed and the AND gate 13j is opened, and the L-level signal indicating disable is output from the OR gate 13h. After that, when the count value of the block counter 20 makes one round and returns to 0, the comparator 13c outputs an H-level match signal for one block period. Therefore, the coincidence signal is output as an enable signal through the AND gate 13j and the OR gate 13h. When the count value of the block counter 20 exceeds the period of 0,
The output of the comparator 13c returns to the L level again, and the output of the counter reset enable generation circuit 13 is disabled.

On the other hand, when the station A device is switched on, there is no master packet on the line, and the operation when the station A device becomes the master station is as follows.

First, the initial reset signal resets the first and second flip-flops 13a and 13e and the D flip-flop 13f, and the counter reset enable generation circuit 13 outputs an enable signal. After that, when the local station master signal 27a indicating that the local station has become the master station is input, the second flip-flop 13e is set and its output becomes the H level. In this state, block counter
When the output value of 20 becomes 0 and coincides with the value of the register 13b, that is, when the master packet is transmitted from the A station device, the coincidence signal is output from the comparator 13c and the output of the D flip-flop 13f becomes L level. Become. Therefore, the AND gate 13g is closed and the L-level signal is output from the OR gate 13h. That is, the disable signal is output from the counter reset enable generation circuit 13. This disable signal is output until the power switch of the local station is turned off.

The hybrid exchange type digital signal transmission system described in the above embodiment can be modified as follows.

(1) The packet length of data transmitted by circuit switching and packet switching is not limited to one block length and may have a plurality of block lengths.

(2) The station device that wants to perform packet switching, in an area (packet switching area) other than the area in which the circuit is switched in the frame, selects one or more than the first block of the area without obtaining a transmission block by a random number. The packets may be sequentially transmitted to the blocks.

(3) The station that wants to perform packet switching may send a packet having an arbitrary packet length at an arbitrary timing in the packet switching area.

(4) By setting the maximum number of blocks occupied by the circuit switching area in one frame, it is possible to always secure the packet switching area.

(5) By not setting the maximum number of blocks occupied by the circuit switching area in one frame, the circuit switching can be given priority over the packet switching.

(Effects of the Invention) As is clear from the above description, according to the present invention, the following effects are achieved.

(1) With a simple configuration, circuit switching and packet switching services can be realized on the same transmission line at the same time, and the line usage efficiency can be improved to provide a wide range of services.

(2) If a block in the circuit-switched area becomes available, data packets transmitting circuit-switched in the subsequent blocks are moved forward. Therefore, no vacant block is generated in the circuit switching area, and the packet switching area is increased by the amount of the data that has been packed in advance, so that the usage efficiency of the circuit is improved.

(3) Since the circuit switching area and the packet switching area are not fixedly set in advance, an empty block does not occur in the circuit switching area, and the circuit can be used efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a time chart of the output signals of the preamble end detection circuit and the clear pulse generation circuit in FIG. 3, FIG. 3 is an explanatory diagram of the circuit switching area and the packet switching area according to the present embodiment, and FIG.
FIG. 5 is a signal time chart of the main part of FIG. 1 when the station which has made a transmission request becomes a slave station, FIG. 5 is a conceptual diagram of data stored in the line state storage device, and FIG. FIG. 7 is a flow chart for explaining the operation of the transmission block selecting means shown in FIG. 7, FIG. 7 is a time chart of the signals of the main parts of FIG. 1 when the station with a transmission request becomes the master station, and FIG. FIG. 9 is a block diagram showing a specific example of the counter reset enable generation circuit shown in FIG. 9, FIG. 9 is a diagram showing a frame structure of a signal in modified Ethernet, and FIG. 10 is a schematic block diagram of a communication system by the modified Ethernet having the frame structure. Indicates. 1 ... Transmission line, 6 ... Preamble end detection circuit, 9
...... Packet type discrimination circuit, 10 ...... Clear pulse generation circuit, 11 ...... Memory writing circuit, 13 ...... Counter reset enable generation circuit, 15 ...... Packet switching interface, 16 ...... Line switching interface, 17 ...... Line State storage device, 22 ... Comparator, 27 ... Sending block selecting means, 28 ... Memory reading circuit, 29 ... Register, 30
...... Overhead writing device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9466-5K H04L 11/20 A

Claims (2)

[Claims] 1. A digital signal transmitted on a communication cable is fixedly positioned in a frame as a frame on a time axis which is periodically repeated and is connected to the communication cable via a tap. Among the stations, one or a plurality of stations that actually transmit signals occupy a block as a small frame on the time axis, which is further divided in the frame, as a unit, and are time-division multiplexed digital. In a multi-station communication network that transmits signals, a station that first makes a transmission request and becomes a mask station sends a master packet of one block length at the beginning of one frame, and the other stations communicate with the master station and the system. Establishing synchronization of timens, circuit-switched packets and packet-switched packets have their identification code in the control bits in the packet, and the state of each block in one frame is identified by the identification code. If there is a request to send a circuit-switched packet based on the above, the contents of the circuit-state storage means are checked to see if there is a block whose transmission has been stopped in the circuit-switched area. If there is a block whose transmission is stopped, it is justified by the number of empty blocks, then the last block in the circuit switching area is found, the next block is allocated, and the circuit switching packet is transmitted. When there is a packet switching packet transmission request, a packet switching area allocated to an area other than the circuit switching area is found based on the contents of the circuit state storage means, and the first block of the packet switching area or A hybrid switching digital signal characterized in that randomly selected blocks are allocated and the packet switching packet is transmitted. No. transmission method. 2. The hybrid according to claim 1, wherein the circuit switching is given priority by not setting an upper limit on the number of transmission blocks of packets transmitted by circuit switching. Switchable digital signal transmission system.