JPH0797569B2 - Method for forming electrodes on P-type region of group III-V semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a technique for obtaining a very high concentration of P-type doping in a surface region of a III-V semiconductor material, and an excellent ohmic property in the above region. The present invention relates to a technique for forming electrodes.

[Prior Art and its Problems] When a bipolar transistor of III-V group material is manufactured, particularly in the case of gallium arsenide bipolar transistor, it is necessary to attach electrodes to both N-type and P-type material regions. is there. There is a problem that it is difficult to manufacture an ohmic electrode excellent in the III-V group region by using a standard electrode material. The same can be said for the Au-Zn alloy, which is the most excellent P-type electrode material. The inventor has found that if the doping level near the surface of the P-type region is not higher than about 10 ¹⁹ per cubic cm, the electrode will be defective, ie will have high resistance. However, when the doping level in the P-type region is about 10 ²⁰ or more per cubic centimeter, the properties of the electrode to that semiconductor region are significantly improved. Therefore, the problem is how to obtain a high-concentration doping layer near the surface of the P-type region.

Zinc is an important acceptor-type dopant in III-V semiconductors, can give high-concentration doping of acceptor impurities to the surface of the P-type region of the semiconductor, and has a very large diffusion coefficient. Diffusion of zinc in gallium arsenide follows an interstitial-substitutional (interstitial-substitutional) model, that is, zinc moves faster in the interstitial than the substitutional position. The diffusion coefficient in gallium arsenide (and indium phosphide) depends on the concentration and follows the D to N ² rule. This N ² dependence is a result of the charge state change equal to 2 in the dissociation reaction (change from zinc at the gallium position to zinc at the interstitial position). The doping distribution of zinc is steep, and the junction depth depends on the surface concentration and is given by the following equation.

X = 1.092 (D _surface · t) ^1/2 Thus, the junction depth is almost equal to (D _surface · t) ^1/2 . Where D _surface is the diffusion constant at the surface and t is time.

Closed and open tube processes are commonly used to effect the diffusion of zinc into gallium arsenide. As is well known, in these methods, as a zinc source, zinc alone, zinc-arsenic compound, diethyl zinc, etc. are used. Most of the conventional methods involve control of arsenic pressure and control of zinc surface concentration. The reason why the arsenic substrate is used in the above-mentioned closed tube process is to eliminate the escape of arsenic from gallium arsenide, which usually occurs when heated. This result is highly variable, so rarely is the use of zinc diffusion in solid-line gallium arsenide technology. Solid diffusion source in an open tube method (SiO ₂ -ZnO) may also be used. The diffusion source is deposited by oxidation of a mixed gas of silane and diethylzinc and is covered by phosphosilicate glass. 3000 for open tube diffusion
Heat to 600 ° C for 20 minutes for typical diffusion of Å units. The use of pure zinc or zinc oxide in such processes is not possible because it damages the surface of the substrate. Ion implantation of zinc is not preferred because it requires annealing for activation, during which redistribution of zinc occurs and zinc escapes from the sample if the surface is not protected. Is. Furthermore, zinc easily moves from the surface in the semiconductor, and the acceptor concentration on the surface decreases. In addition to these, it is well known that the use of arsenic compounds is very dangerous and therefore undesirable.

[Problems to be Solved by the Invention] Therefore, as is apparent, in order to form an excellent ohmic electrode to the P-type region in III-V technology, particularly in gallium arsenide devices, it is higher than 10 ²⁰ per cubic cm. There is a great need to obtain highly doped P ⁺ layers. As will be further appreciated, prior art methods for providing such high concentrations are unsatisfactory and undesirable for production.

The description below is for gallium arsenide, but other
It will be appreciated that III-V materials can also be used in the processes described herein.

In the production of gallium arsenide bipolar transistor,
Beryllium is often implanted to obtain the P ⁺ region, and A to form the alloy to form the ohmic electrode.
u: Zu / Au metal is deposited. The heavily doped P ⁺ layer improves the contact resistance and reduces the parasitic resistance as already mentioned, thus allowing the use of different metals such as Au: Ge / Ni. However, Au: Ge / Ni is usually used only as an electrode to the N ⁺ region. The thickness of the P ⁺ layer need not be precisely controlled for this application. Moreover, by using the same electrode material as that normally used for the N ⁺ region also in the P ⁺ region,
Process steps can be omitted.

Beryllium is a P-type dopant that is normally provided deep into the P-type region by ion implantation. Since ion implantation destroys the crystal lattice of the semiconductor, an annealing process is required to regenerate the lattice structure. However, the beryllium to which the heat of the annealing process was injected moves around,
Therefore, it prevents the presence of very high surface dope pink levels. Therefore, diffusion must be used to create high doping levels at the surface of the P-type region. Further, it is necessary to solve the problems encountered in the diffusion of zinc into the gallium arsenide substrate of the prior art, and it is desirable to further shorten the time for the diffusion of zinc into gallium arsenide. This is because the longer the diffusion time, the greater the opportunity for zinc to desorb from the surface and reduce its concentration there.

[Means and Actions for Solving Problems] According to the present invention, a nitride mask is mounted on the substrate, and P
A high-concentration diffusion of zinc into gallium arsenide is performed by opening a hole in the mask over the mold region. A layer containing zinc oxide and silicon oxide is deposited on the unmasked area. It is desirable for zinc oxide to make up about 20% of the deposit, but the use and / or proportion of silicon oxide per se is not essential to the invention. The reason for diluting zinc oxide with silicon oxide is to prevent or minimize lateral diffusion of zinc oxide in the substrate.
It has been found that dilute zinc oxide causes less lateral diffusion problems than a pure zinc oxide layer. A thin cap of silicon nitride or silicon dioxide is deposited on a substrate containing a zinc oxide deposit, which is then pulse annealed at 700 ° C. for about 10 seconds. This time and temperature may vary. Diffusion depth is a function of both time and temperature.
Accordingly, other temperature and time combinations can be used to obtain the same or different diffusion depths. The silicon dioxide, silicon nitride and zinc oxide remaining on the surface of the substrate are then removed by standard methods using, for example, HF and dilute hydrochloric acid.
Deposition of gold, gold-zinc alloy, aluminum, etc. is then performed on the P-type region using standard procedures such as thermal process of electrode formation. It is also possible to deposit a gold-germanium alloy to form the electrodes. The use of this material is very advantageous since gold-germanium alloys can also be used for electrodes to the N ⁺ region. Next, an alloying process is performed at about 400 ° C. for 2 to 3 minutes to melt the metal or alloy to be alloyed to form the electrode and solidify it on the gallium arsenide substrate. In this way, the electrode is completed, and it is possible to obtain an electrode having good adhesion to the substrate and high conductivity.

If necessary, before depositing the electrode metal alloy, etch the substrate to a depth of approximately 200Å to remove residual zinc oxide and laterally diffused zinc that may have penetrated to a depth of approximately 50 to 100Å. May be. This minimizes the possibility of short circuits between the semiconductor N-type region and the P-type region due to lateral diffusion.

Example In the process according to the present invention, thin-film solid Zn is used as a zinc source.
A thermal pulse drive-in is used to achieve precisely controlled diffusion of zinc into gallium arsenide using an O _X film. The ZnO _x film is preferably deposited by sputtering. With a typical thermal pulse of 700 ° C for 10 seconds, a junction depth of 2000Å can be reached. Silicon nitride or silicon dioxide is used as a cap and later with HF
Removed with HCl. Through this process 500Å to 50
A diffusion depth of 00Å is achieved.

Referring now to FIG. 1 (a), there is shown a substrate 1 on which an N-type collector (or emitter) region 3, an ion-implanted beryllium layer, a P-type base region 7, and a P-type base region 7 are shown. An electrode region 5 and an N-type emitter (or collector) region 9 are included. A silicon nitride mask 11 is preferably formed on the upper surface of the substrate 1 by plasma vapor deposition (PC
VD). As shown in FIG. 1 (b), a hole is formed in the silicon nitride layer 11 in the region above the P-type region 5, and then as shown in FIG. Silicon, preferably 20% zinc oxide and 80
A mixture with a percentage of silicon oxide of 15% is deposited 15 in a standard manner into the region 13 from which the silicon nitride mask portion has been removed. A thin layer 17 of silicon dioxide or silicon nitride is then deposited over the entire substrate including the deposited zinc oxide 15 and the substrate is then pulsed annealed at 700 ° C for 10 seconds.

As can be seen from FIG. 1 (c), zinc from the deposited layer 15 enters the upper surface 19 of the P-type region 5 and provides an acceptor concentration of at least 10 ²⁰ per cubic cm in that region. Although some lateral diffusion appears to occur, such lateral diffusion is small due to the low concentration of zinc oxide in the silicon dioxide in the originally deposited layer 15 as described above.
Both the silicon dioxide and / or silicon nitride layers 11 and 17 together with any remaining silicon oxide and any zinc oxide that has not diffused into the substrate can be formed by standard methods such as using a combination of HF and dilute hydrochloric acid. Will be removed. As an additional process other than this at this point, the upper surface of the substrate 1 is etched to a depth of about 200Å,
The zinc oxide remaining on the surface may be removed and the substrate region where lateral diffusion of zinc occurs may be removed to minimize shorting with the adjacent N-type region 9.

At this point, as shown in FIG. 1 (d), the electrode 21 is formed on the region 19 having a high acceptor concentration.
Is installed. This electrode 21 has gold-zinc alloy, aluminum, gold-germanium, which has appropriate adhesion to the P-type region containing a high concentration of acceptors on the surface.
Other materials may be used. The gold-germanium electrode material is N
It is also an excellent electrode material for the mold region and is therefore particularly useful as it can be co-deposited with the N-type region electrode. Next, if necessary, the substrate is placed in an atmosphere of 400 ° C. for 2 to 3 minutes to alloy the electrode material 21. As a result, the alloy forming the electrodes is melted and solidified on the gallium arsenide substrate. This step is also carried out in the case of pure metal electrodes. In this way, in a simple process, an adhesion electrode to the P-type region of the gallium arsenide substrate is formed without the dangers present in the previously mentioned prior art methods.

It can be seen that according to the invention a very high surface concentration of zinc is obtained. FIG. 2 shows the zinc concentration distribution as a function of depth when using the method of the present invention. Since the concentration is very high, a dry probe can be used as an electrode. Due to such high surface concentrations, any metal such as aluminum may be deposited to form ohmic contacts. By using Au: Zn alloy electrodes on these layers, a specific contact resistance of about 3 × 10 ⁻⁷ Ω · cm ² is obtained. For convenience of treatment, when Au: Ge / Ni metal is used, the specific contact resistance is about 5 × 10 5 after alloying at 430 ° C. for 2.5 minutes or thermal pulse alloying at 430 ° C. for 20 seconds. ^-6
Ω · cm ² is obtained. As described above, according to this method, it is not necessary to use two different kinds of metals for the N-type ohmic electrode and the P-type ohmic electrode.

The advantages of the method of the present invention are as follows. Precise control of junction depth, selective doping, distribution independent of diffusion source layer thickness, prevention of arsenic loss from the substrate, minimization of lateral diffusion, use of hazardous gases such as diethylzinc and arsenic Eliminating the need to Furthermore, the very high surface concentration of acceptor dopants allows the use of dry probes and allows testing early in the process.

Although the invention has been described with reference to specific examples thereof, zinc oxide, it will be apparent to those skilled in the art that numerous changes and modifications are possible. Therefore, the present invention should be construed broadly in the scope of the claims, and includes changes and modifications of the embodiments from the viewpoint of the prior art.

[Brief description of drawings]

1 (a) to 1 (d) are schematic views showing steps of a method used for manufacturing a semiconductor device according to the present invention. FIG. 2 is a graph showing the depth distribution of the zinc acceptor concentration in gallium arsenide with temperature as a parameter. FIG. 3 is a graph showing the junction depth and the sheet conductivity as a function of pulse time with the temperature distribution as a parameter. 1 ... Substrate 3 ... N-type collector 5 ... P-type electrode area 7 ... P-type base area 9 ... N-type emitter 11 ... Mask 13 ... Mask hole area 15 ... Zinc oxide, silicon oxide deposited layer 17 …… Silicon dioxide or silicon nitride 19 …… P-type surface 21 …… Electrode material

Continuation of the front page (56) Reference JP-A-59-11721 (JP, A) JP-A-49-130190 (JP, A) Applied Physics Letters, Vol. 43, No. 5, (1983), PP. 505-507 Applied Physics Letters, Vol. 48, No. 6, Fe b. 1986, PP. 415-416

Claims (1)

[Claims] 1. A method of forming an electrode in a P-type region of a III-V semiconductor device, comprising: (a) fabricating a III-V semiconductor device having at least one P-type region extending to a surface of the device. And (b) depositing a layer containing a group II acceptor impurity and silicon oxide that prevents lateral diffusion on the surface of the P-type region, and (c) pulsing the acceptor impurity into the P-type region. And a step of maintaining the impurity concentration of at least 10 ²⁰ / cm ^{3 on} the surface of the region by removing the layer containing the deposited acceptor impurities, and (e) Providing a conductive metal electrode material on the surface of the P-type region.