JPH0796314B2 - Printer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus, and more particularly to a printing apparatus suitable for multicolor printing using a multi-nozzle ink jet recording head.

[0002]

2. Description of the Related Art Conventional color printing apparatuses are roughly classified into (1) those using silver salt photographs and (2) those using non-silver salt recording, depending on the recording materials used. The one using the silver salt photograph of (1) is famous as a printing machine with a long history since Gudenberg, but since the equipment is large and silver salt paper is expensive, it is expensive (running cost) to print a small number of sheets. In addition, there are drawbacks such as difficulty in interfacing as a computer output device in recent years. The non-silver salt recording method of (2) includes various recording methods such as electrophotography, heat sensitive recording, electrostatic recording, ink jet recording, discharge breakdown recording, and electrophotographic as a color printing apparatus capable of multicolor printing. , Wire dot, Thermal transfer, Inkjet recording method.

Comparing these color recording systems, the electrophotographic system has drawbacks that the device size is large and the device cost is high. This is because three or four photosensitive drums are required and there are many process stations for developing, transferring and fixing. The wire dot method has the drawbacks that it is noisy, the printing speed cannot be increased, and color mixing of the ribbon easily occurs. The thermal transfer method has a difficulty in increasing the resolution. This is due to the thermal diffusion through the ink support and the uneven surface of the printing paper. Moreover, it is difficult to change the transfer density in an analog manner. Further, since the ink film which has been used once cannot be reused, it is inefficient and the printing cost becomes high.

On the other hand, the ink jet recording system is low in noise, high-speed printing is possible, inexpensive plain paper can be used, kanji and figures can be recorded, and character font and size can be easily changed. Since it has the expandability of functions, it does not have the drawbacks of the above-mentioned methods and is expected to be the most suitable recording method as a color recording method. In such a recording apparatus, in order to perform color image recording, a plurality of recording heads (including a plurality of recording element arrays) having different recording colors are arranged side by side and mounted on a head carriage, and the head carriage is mounted on a recording material. The recording is performed while relatively scanning.

[0005]

[SUMMARY OF THE INVENTION However, in the conventional method, it is difficult to prevent color misregistration that attributable to the spacing of the recording head mounted on the head carriage (registration). Also, to improve the recording speed
Reciprocal printing is performed.
Registration in the scanning direction changes.

The present invention has been made to solve the above problems, and reduces color misregistration due to the intervals (registrations ) of the reciprocal scanning of a plurality of recording heads in each scanning direction , and has a simple structure. The purpose is to provide a device.

[0007]

In order to achieve the above object, the present invention provides a memory (381 in FIG. 8 in the embodiment) with a plurality of recording heads (410 in FIG. 8) along with reciprocating scanning of a plurality of recording heads. The address corresponding to each recording head of
(20 7 in FIG. 8, FIG. 1 2) reading means for reading the stored recording data to the corresponding said each recording head and, starting to supply the address to the read means corresponding to said plurality of recording heads each said memory timing, equipped the the registration of each scan direction of the reciprocating scanning timing control means for controlling in response to the (110 in FIG. 11) (20 5 in FIG. 8, FIG. 1 1), between said plurality of recording heads It is characterized by

[0008]

According to the present invention, the start timing for supplying the address corresponding to each of the plurality of recording heads is controlled according to the registration in each scanning direction of the reciprocal scanning between the plurality of recording heads. Round trip between recording heads
It is possible to correct the registration in scanning with a simple configuration.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an example of the construction of the printing apparatus of the present invention, in which 101 is an input device for supplying color image information, such as a three color separation scanner device, a computer, an image file, a word processor, and a facsimile device. Is. Reference numeral 102 is an image processing unit that processes the image information supplied from the input device 101, 103 is a frame memory that stores the image density bit pattern information supplied from the image processing unit 102, and 104 is for printing. 105 is a buffer memory that receives the required amount of information from the frame memory 103 and temporarily stores it.
Is a driver that drives the print head of the output device 106 based on the image information supplied from the buffer memory 104.

The output device 106 has a multi-nozzle ink jet head as a print head and reproduces and prints a color original image on a recording medium such as recording paper. Reference numeral 107 denotes the control signals 109 to 111, 1 for the entire devices 101 to 106 described above.
A control computer (CPU) 108 is controlled via 13 and 114, and 108 is a CPU input / output device (control console) having a keyboard section for connecting to the computer 107 to set various printing conditions and a monitor section for displaying control information. )
Is.

The details of the configuration and operation of each device of FIG. 1 will be described later with reference to the drawings starting from FIG. 2, but before that, the outline of the operation of the entire device of FIG. 1 will be described.

Color image information (signals) read from the original image by the input device 101 and subjected to color separation and photoelectric conversion are supplied to the image processing unit 102 to undergo necessary image processing. That is, in the image processing unit 102, the compressed density information composed of the upper bits obtained by adding the dither signal to the input original image density information is used as a pattern generator.
Is converted into the original image density bit pattern information by, and this is supplied to and stored in the frame memory 103. The pattern generator can also perform complementary color conversion and change the density curve. In addition to the digital halfton expression processing for performing halftone expression on this output image, masking processing,
The image processing unit 102 also performs screen corner processing, black plate processing, undercolor removal processing, and the like.

Next, the buffer memory 1 stores the image information for each minimum unit required for printing from the frame memory 103.
04, the buffer memory 104 performs appropriate processing to facilitate printing, and transfers the buffer memory 104 to the driver 105.

The driver 105 controls the address of the frame memory 103 at the time of printing, and selectively energizes the print head based on the image information supplied from the buffer memory 104 to reproduce and print a color image on the recording paper. At that time, the output device 1
It is preferable to drive the multi-nozzle No. 06 by energizing in a distributed manner without energizing at once. That is, the image information amounts for the multi-nozzles are serially arranged, divided into several groups, the image information is sent through a signal line prepared for each divided group, and the divided serial image signals are printed for each group. Signals are distributed by a synchronization signal synchronized with the nozzles. Further, the driver 105 causes the multi-nozzle head to reciprocate in the head scanning direction so that image printing is performed during both reciprocating scans. As the head, for example, a head having 128 nozzles and 4 heads for 4 colors, which is one multi-nozzle head, is suitable.

FIGS. 2 and 3 show an example of the configuration of the input device 101 of FIG.
An image reading apparatus using an m film as an original will be taken as an example. Here, 501 is a light source, for example, a color temperature 38
00 ° K, 100W, 28lm / W (1m is lumen)
For example, a halogen lamp. Reference numeral 502 is a cooling fan motor for cooling the halogen lamp 501 and the reflection plate 503.

Reference numeral 504 is a heat ray absorption filter, 505 is an optical system for making parallel light, and 506 is a slit plate having a slit wider than the traveling width of the film surface. 507 is a film container, 508 is a film feed sprocket, 50
Reference numeral 9 is the entire developed color film, 510 is an image reading film screen, 511 is a film feed drive motor such as a pulse motor, and 512 is a detector for detecting the film position. For example, slit holes or screen edges. The film position is detected from.

Reference numeral 513R is a photodetector composed of a CCD line sensor, for example, a Toshiba T having 2048 photodetectors.
CD101C or the like is used. Reference numeral 514R is a second optical system including a relay lens, 515 is a first optical system including a field lens, 516B is a CCD light receiver, 517B is a third optical system having the same function as the second optical system 514, and 51.
8 is a dichroic mirror that reflects red light and transmits light of other wavelengths, 519 is a dichroic mirror that reflects blue light and transmits light of other wavelengths, 520G is an imaging optical system, 52
1G is a CCD light receiver.

Next, the operation of the image reading apparatus 101 shown in FIG. 2 will be described. First, the light emitted from the halogen lamp 501 is directly radiated, and the light is reflected from the reflection plate of 503 and passed through the heat ray absorption filter 504, and then put into an optical system 505 for making parallel light, and irradiating the film surface unnecessarily. The slit plate 506 for preventing such a phenomenon limits the width of the image reading film 510, and then the image reading film 510 is passed through the first optical system 515 to irradiate the dichroic mirror 518. The red light image reflected by the dichroic mirror 518 is input to the second optical system 514R, and the film 5
The 10 scanning planes are imaged on the light receiver 513R. At this time, a color correction filter may be attached between the light receiver 513R and the second optical system 514R.

On the other hand, the light transmitted through the dichroic mirror 518 is reflected by the next dichroic mirror 519 as blue light and only the light of other wavelengths is transmitted. The blue light reflected by the dichroic mirror 519 is focused on the optical system 517B to form a blue light image on the light receiver 516B. The light transmitted through the dichroic mirror 519 becomes green light, and this green light is imaged on the CCD light receiver 521G by the imaging optical system 520R to form a green light image. It is advisable to insert a color correction filter in front of this CCD light receiver 521G.

Each CCD 513R, 516B and 521
Each color original image signal formed on G is photoelectrically converted to obtain each CC.
A time series signal is output to the outside of the CCD through a shift register (not shown) in D. After the scanning of one line of the film 510 is completed, the film feed drive motor 511 feeds the film 510 for one line in the arrow direction, and the next line is moved to the CCDs 513R, 516B and 5 in the same manner as above.
Image is separated on 21G.

FIG. 3 shows an example of the circuit configuration of the input device 101 of FIG.

First, the output information of the CCD 513R for detecting the red light image is amplified by the video amplifier 315R through the data line 320R, and this is converted into an analog digital amount by the analog / digital converter 316R. Reference numeral 317 is a signal line for giving analog-digital conversion (ADC) sampling timing to the analog-digital converter (ADC) 316R. In this respect, the other CCDs 516B and 521G have the same configuration. 319 is a film position detection signal line, 322 is each CCD 513R, 516
B, 521 G sampling pulse lines and 323 are clock pulse lines. The sampling pulse line 322 controls the light receiving time to the CCDs 513R, 516B, 521G, and the clock pulse line 323 controls the image signal output speed. A film feed pulse motor signal line 324 is connected from the power line 325 to the film feed drive motor (pulse motor) 511 via the amplifier 309.

FIG. 4 shows an example of the configuration of the image processing unit 102 of FIG. The operation of digital halftone expression and data compression will be described with reference to FIG. Since the lines of each color have almost the same configuration, only the red light image line will be described for the sake of simplicity.

The image data in which the density of the original image is expressed by a digital amount is supplied from the line 354R, and is usually 8 bits.
It has a density resolution of about (bit) (256 gradations).
The dither signal periodically generated from the counter 363 is input to the digital adder 350R via the dither signal line 359 and added to the above-mentioned image data.

At this time, for example, when the dot diameter of the image on the output side 106 is 100 μmφ and one pixel is represented by a 4 × 4 dot matrix, the length of one side of one pixel to be output is

[0027]

[Equation 1]

Therefore, the number of basic gradations is 17. In terms of resolution, it is not desirable to increase the size of one pixel more than this, so in this example, it is set to about 282.8 μm. Therefore, since the data line 355R in this case only needs to have 5 bits, the number of dither bits is (8 bits).
-5 bits) = 3 bits. Therefore, the counter 36
Reference numeral 3 is a 3-bit counter. In addition, the counter 36
The input terminal 3 is connected to the initial value setting data line 369 and the step pulse lines 367 and 368 which generate one step pulse per pixel in the X-axis and Y-axis directions in the printing direction.

The dither-added upper 5 bits are output from the digital adder 350R to the data line 355R, and the lower 3 bits are omitted. The line memory 351R stores data for one CCD line supplied via the data line 355R. Reference numeral 360 indicates an address and a read / write control line of the line memory 351R. 364 is an address counter for line memory and a control signal generator. The counter (CNT2) 364 is the control CPU 107.
The initial value is latched by the signal supplied from the line 371 to the counter value CNT2 by the increment pulse signal supplied from the line 370 when scanning one line sequentially. Also,
The counter 364 controls the read / write of the line memory 351R, the address, and the control line 360. The line memory 351R consists of 5 bits per pixel, and if the CCD 513R has 1728 pixels, it is 864.
It requires a memory capacity of 0 bit. Reference numeral 356R is a data line which is read from the line memory 351R and supplies data, which is also a 5-bit data line.

352C is a pattern generator,
Here, while converting the density data into a density pattern,
Also performs complementary color conversion. Furthermore, the density curve can be changed by changing the value of the pattern generator (PG) by the generator 352C. Reference numeral 357C is a pattern line of cyan density which is a complementary color of the red light image. This line 357C is 4 bits. Reference numeral 353C is a 16-bit parallel register (LATCH), which collects 4-bit data input for easy transfer to the frame memory 103 four times to generate 16-bit data, and transfers the 16-bit data to the frame memory 103. Reference numeral 362 is an address and control line for sequentially latching data in the 16-bit parallel register 353C four times by 4 bits. Reference numeral 366 is a counter for switching and storing 4-bit data in the parallel register (latch circuit) 353C. 373
Is a signal line for sending the latch timing from the external CPU 107 to the counter 366.

FIG. 5 shows an example of the configuration of the frame memory 103 of FIG. The capacity of the page memory 381, for example, input information amount is 1500 × 1500 pixels, 1000 ² × per color 4 ² bit = 16,000,000bit
= 16 Mbit = 1 MW (megaword) of memory is required. A bit pattern of image data is stored on the page memory 381. A data output line 382Y has a 16-bit configuration. Reference numeral 383 denotes an address control line for page memory, which naturally includes a page select line and a read / write control line. 384 is a counter (CNT5). 385 is an initial address setting line, 3
86 is an increment and decrement pulse line.

6 and 7 show an example of a timing chart of a series of image signal generation from the input device 101 to the image processing unit 102 and the page memory unit 103. First,
The control CPU 1 sends a start signal (1A) indicating that the original image signal for one line should be stored in the line memory 351R.
Release from 07. As a result, the latch circuit (not shown) inside the input device 101 causes the ready / busy (R
The EADY / BSY) signal (1F) is set to high (High, hereinafter referred to as H). Light source for reading 50 before this state
Since 1 etc. are set up, a latent image is formed on the CCD 513R, so the electronic shutter signal (1
The signal photoelectrically converted in the CCD 513R by C) is transferred to the shift register (not shown) side. When this transfer is completed, the original image signal is output in time series according to the internal clock (1D), so that this original image signal is converted to analog / digital (A / D) by the analog / digital (A / D) sample signal (1E). D conversion). Based on the A / D converted original image information, the control CPU 107 sets the initial value in the counter 363 through the data line 369. Therefore, the initial value of the first original image information is added by the adder 350R, and the upper 5 bits of the result are output to the data line 355R. This dither-added high-order 5 bit data is used as a line memory read pulse (2
The line memory 351R is read by B).

Since the initial value of the line memory address at this time is set in the counter 364 via the line 371, if the initial value is set to 0 now, the counter 364 will be CN.
Since T2 = 0, the data is written in the address 0 of the line memory 351R. Next, the data of the second pixel is A / D converted by the clock pulse (1D) of the second pixel, and at the same time, the step pulse of the dither counter 363 is input from the line 367 and the counter C of the counter 363 is input.
The NT1 value is incremented by 1 (step up). At the same time, the line memory address is supplied from the line 367, and the counter 3
Step by one. Therefore, the value CN of the counter 363
The data of the initial value + “1” is set in T1, and the counter value of the counter 364 is CNT2 = 1. In this manner, the A / D-converted second pixel data and the counter CNT1 value are added, and the upper 5 bits thereof are output onto the data line 355R. This output data is stored in the first line memory 351R by the second line memory read pulse (28).

Similarly, each pixel data is subjected to dither addition, and the upper 5 bits of the result are stored in the line memory 351R in the order of addresses. When this operation is performed for 1000 pixels, the line memory 351R becomes full. A counter (not shown) that counts the number of pixels (1000 pixels)
Output resets the READY / BSY signal (1F). As a result, A / D conversion for one original line,
Complete the dither addition and memory store operations. 1
Before the READY / BSY signal (1F) for the line is reset, one step pulse (1B) is sent to the film feed motor 511 to transfer the film 509.

One of the reasons for performing the dither addition is that the dot diameter on the output side is usually about 100 μmφ and therefore the size of one pixel matrix cannot be increased. If it is increased, gradation is increased but resolution is deteriorated. Is. Normal,
In non-silver salt recording, about 4 × 4 matrix is generally used. However, in the 4 × 4 matrix, a pseudo contour for 17 gradations is generated and the image quality is not good.

On the other hand, as for human visual characteristics, many gradations can be judged in a large area, but resolution is required in a small area and gradation cannot be judged so much. Due to such visual characteristics, the lower 3 bits are not cut off from the 8-bit data of the original image signal, but the dither signal is added to the original image signal to change the appearance probability of the basic density pattern according to the original image density signal, and the equivalent The average image density is changed to. As a result, when uniform density expression is performed over a relatively large area, the equivalent 8 bi
t, that is, 257 gradations can be expressed, while 283
With a pixel of about μm, it can be reduced to 17 gradations. However, this allows the gradation expression to be expanded without affecting the resolution, and thus the image quality is further improved. Further, another reason for performing the dither addition is that the density expression equivalent to 8 bits can be expressed by an equivalent 5 bits, which results in memory compression.

Next, the operation of storing the original image data corresponding to one CCD line in the line memory 351R, performing the complementary color conversion of the density data, converting the density pattern data, and arranging as 1W (word) data will be described with reference to FIG. 7 and FIG. 4 and FIG.

The operation of storing the density data stored in the line memory 351R in the page memory 381 as bit pattern data is started by the conversion start signal (2G) as shown in FIG. When the READY / BSY signal (2H) becomes H by the conversion start signal (2G),
The initial value of the line memory address supplied from the control CPU 107 is set in the counter 364 through the line 371. However, the initial value at that time is set to 0. Therefore, the value CNT2 of the counter 364 becomes CNT2 = 0. The address (2C) is sent to the line memory 351R, and the line memory read pulse signal (2D) supplied via the line 360 outputs the data stored at the address on the data line 356R. That is, the first pixel density data is the PG address line 35.
It is output on 6R. On the other hand, in the initial stage, the address counter 365 for the pattern generator 352 and the address register 366 for the parallel register 353 are initialized by the control CPU 107. The initial values are usually CNT3 = 0 and CNT4 = 0, respectively. Therefore, in this case, the pattern generator (PG) 352C
The address value (ADR) of the density data on the line 356R and the address value (ADR) output from the counter 365 are all one address value (ADR). There are two address lines 361 for transmitting the address output from the counter 365, and there are 2 bits.
Transmit data. This address is for selecting the column address of the 4 × 4 matrix.

Next, in response to the register latch signal (2F), the bit pattern of the first row of the first pixel data is output in parallel every 4 bits through the data line 357C, and this is output in parallel register (latch circuit) 35.
Latch to 3C. At this time, 353C of the register 366
Since the value CNT4 of the selection address for use is 0 as described above, the first row bit pattern of the first pixel is stored in the first of the latch addresses. After this storage, the line memory address increment pulse is sent to the control line 3
70, and the counter value of the counter 364 is CN
T2 = 01 _H , the counter value of the register 366 is CNT4
= 01 _H , and the counter value of the counter 365 is CNT.
It remains 3 = 0. Line memory 351R in this state
The second address data of is output by the line memory read pulse signal (2D), and this is output by the data line 356.
The address of the pattern generator 352C is set via R. In this state, the PG address (2E) of the counter 365 is the same as the first pixel address,
The pattern generator 352C outputs the first row of the second pixel on line 357C. This output data is stored in the 4th to 7th bits of the parallel register 353C by the second register latch pulse (2F).

Similarly, when this cycle is repeated four times, the P1 cycle shown in FIG. 7 is completed. 16 bits at this point, 1W
The operation of transferring data to the page memory 381 is started. That is, at the initial stage, the page memory address set value is set from the control CPU through the control line 385 to the counter
Give to 4. At this time, the page select line information is also included, as described above with reference to FIG. Counter 3
Since the value of 84 is generally 0 at the beginning, 0 is set to the address of the page memory 381 from the address control line 383. In this state, page memory write pulse (3
A) is released, and the first 1-word (Word) data is stored in the address 0 of the page memory 381. After sending the page memory write pulse (3A), the page memory address increment pulse (3B) enters the counter 384 through the pulse line 386. This counter value of the counter 384 becomes CNT5 = 01 _H.

The above P1 cycle processing and transfer to the frame memory 103 are performed for one line of the CCD 513R (162).
It is repeated every 3 pixels), and this cycle is set to P0. 162
When the line memory address pulse (2C) of the third pixel is released, the pattern generator address increment pulse is output at the same timing. Thus the value of the register 365 becomes CNT3 = 01 _H. When the 1623rd pixel data is converted to a bit pattern and transferred to the frame memory 103, the value of the counter 364 becomes CN.
It is initialized through the control line 371 so that T2 = 0. At the same time, the value of the counter 366 is also initialized to CNT4 = 0. This initialization is a process in the first half, and for the density data for the first CCD line, only the bit pattern for the first row of the dot matrix is stored in the page memory 3.
It is done because it has entered 81.

Next, the value of the register 365 is CNT3 = 0.
In the state of 1 _H , the same operation as described above is repeated and the density data for one line stored in the line memory 351R is read again. At the time of reading the line memory for the second time, the pattern generator 352C is switched to the bit pattern for the second row. 16 bits every 4 times
Frame memory 10
Transfer to 3.

In this way, the original image density data for one CCD line input from the input device 101 is read four times and the pattern generator 352C is accessed. At that time, the column address of the bit pattern is set to 2 in the counter 365.
Switch every time by bit signal. Parallel register 35
It is input to the 3C in units of 4 pixels and transferred to the frame memory 103. As a result, the image information is stored on the page memory 381 in the state of the density bit pattern of the original image.
As described above, after the cycle P0 is repeated 4 times,
The READY / BSY signal (2H) becomes low (Low, hereinafter L). This completes a series of processes for converting the original image density data into a bit pattern and transferring it to the frame memory 103.

FIG. 8 shows an example of the configuration of the apparatus from the transfer of data from the frame memory 103 to the driving of a recording head 410 (see FIG. 15) described later, where 109A is used.
And 109B are communication lines for communicating signals between the input device 101 and the control CPU 107. This line 10
9A or 109B, film feed pulse motor control pulse, sample pulse of A / D converter 316,
And signals such as the film leading edge detection pulse come in and go out.
A control line 110 transmits signals such as initial address set values of the counters 363 to 366 and increment pulses from the control CPU 107. Image processing unit 10
The 16-bit 1-word data signal processed in 2 is transferred to the data bus 2 at the address destination given by the control board 204.
Through 13 the page memory 38 of the frame memory 103
Store in 1. Therefore, the counter 384 of the frame memory 103 is mounted in the control board 204. A control circuit 211 includes a frame memory clock generator and a refresh controller incorporating a refresh address counter. Control circuit 2
Reference numeral 11 has a function of forcibly switching to the refresh mode when data is not accessed from outside the frame memory 103 and when the frame memory 103 is accessed for 1 msec or more. The above-mentioned data bus 213, address bus 214 and control bus line 11
1A is also connected to the control board 207 and the latch circuit 208 of the buffer memory 104, and the data of the frame memory 103 is transferred to the D line through the bus lines 213 and 214.
Data is transferred to the latch circuit 208 of the buffer memory 104 by MA (Direct Memory Access Method).

Reference numeral 205 denotes a control board for controlling the print start and finish timings of the heads 410 so that the print dots can be correctly overlapped during printing against the positional deviation of the heads 410 for four colors, and also control during printing. To do. Two
Reference numeral 06 is a controller that controls the entire control boards 205 to 209. An address counter unit 207 is for setting a frame memory address. Latch circuit 2
Reference numeral 08 latches the address data designated by the address counter unit 207 through the data bus 213. Also,
Since the print head 410 has 128 nozzles for each color, the latch circuit 208 transfers 16-bit data to the data bus 2
The data is read 8 times through 13, and this data is sent to the head driver 105. The multi-nozzle head 410 is operated by the head drive signal of the head driver 105 to print an image.

FIG. 9 shows the controller (control board) 2 of FIG.
An example of the configuration of 06 is shown. First, the frame memory 104
The reference signal (φ _cp ) is supplied from the clock generation unit 211 to the main substrate 206 via the line 237. Reference signal φ _cp
Is a continuous pulse whose period is the minimum interval at which the data in the frame memory 104 can be accessed. Φ ₁ , φ in the figure
_{The second} clock is a clock having a half frequency of the reference signal φ _cp and both are 180 ° out of phase with each other.

Initial reset pulse IRS when power is turned on
T (not shown) is generated. Latch circuits 801, 805, 814, 8 are generated by this initial reset pulse IRST.
28 is cleared, and at the same time, counters 808, 819, 82
Also clear 4,832. Initial reset pulse IRST
Becomes low (Low, hereinafter referred to as L) several msec after the power is turned on, so various latch circuits 801, 805,
814,828 and counters 808,819,82
The initialization of 4,832 is completed.

Next, when the print start pulse STR is released from the control CPU 107, the latch circuit 801 outputs Q = H.
high (hereinafter referred to as H). The print start pulse STR usually has a pulse width of about 1 msec. Therefore, the output of the AND gate 803 is 1 mse.
Since a set pulse of H of about c is output, the set pulse is input to the latch circuit 805 and its Q output becomes H. Therefore, a pulse synchronized with the reference signal φ _cp is output from the AND gate 807 to the counter 808 (CNT
Step 1) is entered and a stepping motion is performed. Reference numeral 808 denotes an N-ary binary counter, and the value of this counter 808 can be arbitrarily changed by the set value of the setter 811. Reference numeral 810 denotes a comparator, which outputs a coincidence pulse when the value of the counter 808 and the value of the setter 811 coincide with each other, thereby causing the timer T1 to operate.
Is operated to reset the counter 808 and the latch circuit 805 via the OR gates 809 and 806. The timer T1 (RST1) is used for each I.S. The variation of the reset time of C is corrected. The one-shot pulse from the timer T1 is also input to the latch circuit 814, and the output Q of the latch circuit 814 is set to H.

In the above period, the frame memory 10
A memory read signal MRE informing that the access is to be started is output from the Q output of the latch circuit 805.
Accordingly, the chip select signals CS0 to CS3 for accessing the page memories 381 for four colors are supplied from the counter 808. At the same time, the one-shot timer (T7) 818 generates a strobe pulse MSTRB for reading the data value of the address supplied to the frame memory 103 into the buffer memory 104. Address increment pulse ADR. PLS is generated by timer T8. Time charts of these pulses are shown in FIGS. 10A and 10B, and details of one cycle of the memory read signal MRE are shown in FIG. 10B.

By the chip select signals CS0 to CS3 supplied from the counter 808, 16 items for each of 4 pages of 4 colors are obtained.
The bit data is read in time series, and the latch circuit 2 of the buffer memory 104 is generated by the strobe pulse MSTRB.
Latch at 08. That is, the counter 808 is set to an octal counter by the setter (SET1) 811,
The address to the frame memory 103 is 1 pulse of address increment pulse ADR.
Emitted from PLS and incremented or decremented. The control CPU changes the increment / decrement of the address.
It is controlled by / 07.

As is clear from the above description, the period in which the Q output of the latch circuit 805 is H is the period in which one word (Word) of data is being transferred to the page memory of each color. When the transfer of one word (Word) is completed, the latch circuit 814 is set. Multi nozzle head 410
The latch circuit 814 has an output Q of H
In the meantime, a shift pulse for converting 1-word (Word) data latched in the previous term into 128-bit serial data is created.

The shift pulse is output from AND gate 816 as pulse SFT1. This shift pulse S
The shift register (not shown) provided in the buffer memory 104 is operated by FT1. When the output Q of the latch circuit 814 becomes H, the AND gate 81 is driven by the clock φ2.
7 to activate the counter 819,
Of the counter 8 and the value set by the setter 821 are compared by the comparator 820.
Set 19 to any counter value. Comparator 8
With the output of 20, the timer (T2) 822 is output in the same manner as described above.
Is operated to reset the counter value of the comparator 820, while the counter 824 is operated. A time chart during this time is shown in circle B-maru C in FIG.

16-bit, 1-word data is read out from the frame memory 103 once by the buffer memory 1.
This data is serially arranged bit by bit for transfer to the latch circuit 208 of No. 04. Therefore, 16 pulses of the shift pulse SFT1 are emitted at one time. 16
When the shift pulse SFT1 of the second generation is released, the coincidence pulse is released from the comparator 820, and the latch circuit 814 is released.
At the same time, the latch circuit 805 is set through the OR gate 804, and the mode for accessing the frame memory 103 is entered again. At that time, since the address counter 207 has been incremented or decremented by one from the previous time, as a result, 16 bits of the next data of the previous time is input and latched in the latch circuit 208 of the buffer memory 104. Less than,
Similar to the above, the data latched this time and the data 32bit, 2Word inputted to the shift register last time
The whole is shifted by 16 bits again by the shift pulse SFT1.

Reference numeral 824 is a counter, which controls how many times 16-bit data is input to the buffer memory 104. In the present embodiment, since the multi-nozzle head 410 is 128 per unit, it is sufficient to receive the data from the frame memory 103 128/16 = 8 times. Therefore, it is necessary to decode the number of times the data is received from the frame memory 103 by the decoder 825, extract the output with the predetermined decode value, and stop the various input pulses thereafter. Therefore, the decode output from the decode 825 is supplied to the OR gate 815 and the latch circuit 8 is supplied.
14 is reset, and at the same time, the latch circuit 805 is also reset via the OR gate 806. This stops the generation of various control pulses thereafter. On the other hand, the decoder 825
The timer (T3) 827 is actuated by the output of, and the counter 824 is stopped and the operation of the latch circuit 828 is started.

The time chart of the above operation is shown in circles A to D in FIG. Φ3 in the figure is a clock from a free-running oscillator (not shown) provided in the control board 206. The cycle of the clock φ3 may be set longer than the nozzle energization time T _H for the multi-nozzle 410. When the latch output Q of the latch circuit 828 becomes H, the printing start mode is set. A pulse synchronized with the clock φ3 is output from the output of the AND gate 829, and the timer (T4) 830 is operated.
The timer (T4) 830 is a timer that determines the energization time for each of the multi-nozzles 410. T4 timer 8
The falling edge of the 30 pulse starts the operation of the counter 832. This counter (CNT4) 832 controls the number of times of printing with 128 bits.

The nozzle drive pulse output from the timer (T4) 830 passes through the safety circuit 831, and one of them generates the shift pulse SFT2 by the timer (T7) 818,
The other directly enters a line 1306 in FIG. 14 described later.
The nozzle drive pulse of the timer (T4) 830 also enters the counter 832, and the output pulse from the timer 830 is 16
Control to get out individually. 16th pulse is decoder 8
Upon exiting 33, the pulse is sent to timers 834 and 83.
5, the latch circuit 801 is reset, so that the data for one head of the multi-nozzle is transferred to the frame memory 10.
The operation from receiving from No. 3 to printing is completed. At the same time, various latch circuits 805 ..., And of FIG.
The counters 808 ... Are reset and initialized.

A control line 1305 shown in FIG.
The signal supplied to the counter is generated by the counter 838 of FIG. That is, the counter 8 is driven by the SFT2 clock.
The counter of 38 is incremented and the counter is gated by the signal WRT. The above time charts are shown in circles D to E of FIG.

FIG. 11 shows an example of the configuration of the control board 205 for controlling the print timing deviation amount between the print heads and the print control in FIG. 8, where 1101 is a registration setting value reading port for each color, and the control CPU 107. Registration registration value data is sent from. 1
102 is a presettable counter. An input terminal 1103 receives the control pulse PX sent from the control CPU 107. The presettable counter 1102 is a down counter, which starts printing and starts the pulse motor 4
Each time 04 (see FIG. 15 described later) advances, the control pulse PX is sent from the CPU 107 through the input terminal 1103, and the count number is decremented by one pulse. When the count value becomes 0 or less, the counter 1102 outputs a carry to the output line 1104 and changes from H to L. Therefore, the pulse PX supplied from the terminal 1103
Input to the counter 1102 is stopped. As a result, the head 410 for the preset registration amount is obtained.
A signal for stopping printing is output as a signal PRT via the AND gate 1106 and the selector circuit 1111.

Reference numeral 1108 is a print width control counter.
A print width setting switch (paper width setting device) 1109 is common to all colors (each page). 1105
Is an AND gate, the signal PX is at the terminal A, the counter stop signal of the counter 1102 is at the terminal B, and the counter 11
The counter stop signal of 08 enters the terminal C. The print width control counter 1108 is a down counter similar to the counter 1102. When the head 410 scans for registration, the B terminal of the AND gate 1105 becomes B = H, and the signal PX is input to the counter 1108 through the terminal A. To do. At this time, the counter 1108 has the switch 110.
Since the data of 9 has already been read, output line 11
The output of 07 is H. The data in the counter 1108 decreases in response to the input of the signal PX, and the switch 1109
When the signal PX is input by the number of pulses set to, the output line 1107 changes to L, and the AND gate 1105 stops the input of the signal PX to the counter 1108. Therefore, the AND gate 1106 outputs a signal that becomes H when the head 410 advances more than the registration amount and is within the print width.

Reference numeral 1110 is a color setting device (page setting device), and the AND gate 110 is operated via the selector circuit 1111.
The output signal of 6 is output to one of the 4-bit lines 1113. The output from the 4-bit line 1113 is used as the PRT signal indicating the printing period.

FIG. 12 shows an example of the configuration of the address counter unit 207 which sets the frame memory address in FIG. 8 and controls the address to the frame memory 103, where 1201 is from the 4-bit line 1113 (see FIG. 11). This is the line of the print start command signal PRT sent. 12
02 is a switch for selecting a board according to which color (that is, which page) of the four address control boards is instructed because signals of four lines for four colors are input from the line 1113. is there. 1203 is an AND gate, which is a print start command signal PRT and a counter 808.
(See FIG. 9) from the address increment / decrement pulse signal ADR. P
Up / down counter 120 is obtained by taking a logical product with LS.
Supply to 6. The counter 1206 is switched up / down by the up / down signal UP / DWN supplied from the control CPU 107 via the control line 1204.

Reference numeral 1205 denotes a line for setting an initial address value to the frame memory 103, which is set at every start of printing scanning from the control CPU 107. The address resulting from the increase / decrease to the initial value enters the line driver 1208 through the line 1207.

The frame memory 103 is an image processing unit 102.
Also, the driver 1208 is a three-state line driver. Frame memory 10
The timing of address access to signal 3 is the signal M supplied from the latch circuit 805 of FIG. 11 through the line 1210.
It is determined by RE and the page select signal CS sent through the line 1211 from the counter 808 of FIG. Reference numeral 1214 is a page setter of the address counter board 207, and a 2-bit output signal enters the comparator 1212 through the line 1213. Comparator 121
The coincidence pulse from 2 enters the AND gate together with the signal MRE and supplies the logical product to the line driver 1208 via the line 1215 to control the line driver 1208. As a result, the address line 214 is opened except when the data is fetched from the frame memory 103. 1209 indicates the address bus line 214
Shows the connection line to.

FIG. 13 shows an example of the configuration of the latch circuit 208 of the buffer memory 104 of FIG. 8, in which 1001 is a pair of OR gates, and the control board (controller) 2
06 and the control pulse SFT1 or the control pulse SFT2 described later are ANDed and input to the shift terminal of the parallel serial register 1006 and the shift terminal of the shift register 1007. 1002 is a bus line for 16-bit data supplied from the frame memory 103. The data latch timing is performed by the memory strobe pulse MSTRB and the page select signal CS supplied from the control board (controller) 206.

That is, the page select setting device 1003
When the output value of 1 and the page select signal CS match, a pulse output is emitted from the comparator 1004, and the data DATA on the data bus 1002 is latched in the parallel serial register 1006 at the pulse timing gated by the AND gate 1005. The 16-bit parallel data latched by the register 1006 is transferred to the shift register 1007 in 16-bit units by the pulse SFT1.

FIG. 14 shows an example of the configuration of the head driver 105. When 128 bits, that is, the data amount for one head is prepared in the shift register 1007 in the latch circuit 208 of the buffer memory 104, this video signal (image data) is transferred to the head driver 105.
The head driver 105 needs to be integrated and attached near the head 410. This is because if the distance between the driver heads is long, the drive waveform becomes bad and the voltage drop between the lead wires is not preferable for head operation.

On the other hand, since the print head 410 is moved in this embodiment, it is desired that the number of signal transmission lines to the head 410 be as small as possible. On the other hand, from the printing conditions of the head 410, the energization time for one nozzle is usually about 10 μsec, and the cooling time is 1 mse.
It is about c. In addition, since a current of about 0.2 A is required to operate one nozzle, 128 × 0.2 A = 25.6 A is required when all 128 nozzles are operated at once, which requires a large head power supply capacity. And Therefore, under such a nozzle driving condition, the head power supply capacity is reduced when the nozzle driving is distributed so that the load sharing becomes uniform with respect to the time axis without driving all the nozzles at once. The head driver 10 without reducing the printing speed.
The number of input signal lines to 5 can be reduced. Under the above nozzle driving conditions, 1000 μsec / 10 μse
c = 100, 128/100 = 1.28 → 2, that is, 128 heads are divided into groups of two nozzles to form 64 groups, and if the nozzles are driven in time series, the maximum required current is 0.2 A × 2. = 0.4A However, in reality, in order to reduce the time required to drive the head because it is necessary to increase the printing speed, in the present embodiment, one line of 128-bit head is scanned by switching 8 groups and 16 times. The maximum current in this case is 0.2 × 8 = 1.6.
A, the nozzle driving time is 12 at the pulse interval of the clock φ3.
If it is μsec, 12 μsec × 16 = 192 μsec
Becomes

12 stored in the shift register 1007
The 8-bit video signal is set to 1 by the pulse SFT2 driven by the falling pulse of the output of the timer 830 in FIG.
6-bit 8-column parallel line driver 1008
And is transmitted to the head driver 105 (see FIG. 13). On the head driver 105 side, the buffer memory 1
The video signal from 008 enters from the input terminal 1309.
The control whether to print the supplied video signal,
Both the print signal PRT input to the line 1307 and the nozzle energization width control pulse signal Video-Out sent from the safety circuit 831 to the line 1306 are used. That is, when the print signal PRT becomes L and the nozzle energization width control pulse signal Video-Out becomes H, the video input terminal 1309 is first passed through the NAND gate 1308.
The video signal from the device enters the driver circuit 105.
Reference numeral 1305 denotes a switching code signal line for sequentially energizing 16 nozzle groups, which is formed of 4 bits. 1303 and 1304 are multiplexers for switching to 16: 1. That is, one video signal input to the multiplexer 1303 appears on any one of the 16 output lines by the switching code signal line 1305. Head driver units 1301 and 1302 drive the head 410 by amplifying a TTL level video signal in voltage and current. An output terminal 1310 is connected to the multi-nozzle head 410 via a flexible cord or bonding 414.

FIG. 15 shows an example of the configuration of the output device 106 shown in FIG. 1, in which 410 is a printing head (four-color recording head). For example, as shown in the figure, an on-demand type multi-nozzle ink jet head is used. For four colors, use four equipped. This head 410 has 12 nozzles.
A multi-nozzle head having eight heads 41
An example of the structure of 0 is shown in (A) to (D) of FIG.

As shown in FIG. 8, four heads 410 having such a structure are prepared for yellow Y, magenta M, cyan C, and black BK, one for each color, and a common movable table ( (Carriage) 416. 401 is a printing paper feed motor, for example, a pulse motor is used. 402 is a paper feed roller, 403 is printing paper, 40
4 is a drive motor for moving the 4-color recording head 410, 4
Reference numeral 05 is driven by the motor 404 to drive the head unit 410.
Belt 406 for moving
Of the timing belt gears 407 and 415 for converting the rotational movement of the head unit 41 into the linear movement, respectively.
A detection device for detecting the movement position of 0, 408 is a guide rail for guiding the movement of the head unit 410, 409 is a power feeding cable for sending an electric signal to the head 410, 41
Reference numeral 1 denotes an ink supply pipe for supplying ink to the head 410, which communicates with the pipe 1507 in FIG. 412 is an ink tank, 413 is a power supply cable 4.
09 is a connector forming a relay board and a driver circuit printed board. Reference numeral 414 denotes a flexible wiring board on which a signal line for transmitting a signal sent from the buffer memory 104 is printed.

FIG. 16A shows an example of a heating element unit of the head 410, in which 1501 is a polyimide layer, 1502 is an aluminum layer, 1503 is a heating element layer,
1504 is a silicon dioxide (SiO ₂ ) layer, 1504 '
Is a silicon (Si) substrate, and these layers are formed by vapor deposition. Reference numeral 1505 is a plate that also serves as a substrate support and heat dissipation, and is made of aluminum. Also, this plate 1505
Are glued together. (B) of the figure shows the entire nozzle, where 1509 is a metal member for supporting the head unit,
Reference numeral 1506 denotes the heating element unit shown in (A) of the figure, 1507 denotes an ink supply pipe, and 1508 denotes glass which is cut into a lump shape.
Stick to No. 6. (C) of the figure shows the cross section of the nozzle, (D) of the figure shows the surface of the heating element side substrate of the multi-nozzle, where 1510 is a common electrode, 1511 is a base agent,
Reference numeral 1513 is a lead wire portion. Explaining the principle of ink ejection, the ink supplied from the ink supply pipe 1507 enters the common liquid chamber and reaches each nozzle. In the normal state, the surface tension of the ink does not cause the ink to project to the outside of the nozzle, but when a voltage is applied to the heating element 1503 to generate heat, bubbles are generated due to the dissolved air in the ink. Project.

Next, a procedure for taking out the image data input to the frame memory 103 and printing the image data will be described with reference to a flow chart described later. The main controls necessary for printing are address control to the frame memory 103, registration control between the print heads 410, and print width control.

For simplification of description, FIG. 17 shows the relationship between the address and data arrangement in the frame memory 103 when the number of input pixels is 512 × 512 and the basic density matrix of one pixel is 4 × 4. About.

18A and 18B show an example of correspondence between data in the frame memory 103 and print addresses. As shown, C input from the input device 101
In the 512 pixels of the CD1 line, the density data is converted into a bit pattern by the image processing unit, and each pixel (A1 to R
1), (A2 to R2) ... Since it is stored every 16 bits on the frame memory 103,
Addresses (hereinafter referred to as ADR) 0 (A1 to D1, A
2 to D2, A3 to D3, A4 to D4) 16 bits, A
For DR = 0001 _H (A5 to D5, A6 to D6, A7
~ D7, A8 ~ D8) 16 bits. Therefore, the 512 × 512 pixels converted into the bit pattern are 0 to
The address of 262143 is required. FIG. 18 (A)
Is 128 with respect to the address of 512 × 512 pixels described above.
The state when printing with the bit multi-nozzle 410 is shown.

For the first print scan, for example, address 1
27-120, then 255-248, ..., 26
A row of 2143 to 262136 and the rightmost 128 bits of the original image is printed. In this case, print head 410 scans from left to right. During this time, the head 410 steps 2048 times. At the 2048th step, the print sheet 403 is stepped by the 128-nozzle sheet feed motor 401. Subsequently, the addresses 262128 to 262135 are printed, the printing direction is switched from right to left, and the step is advanced 2048 times in the same manner as described above, and the second head scanning is completed.

FIG. 18B shows an example of a specific address setting procedure when printing 512 × 512 pixels.
Therefore, with 512 × 512 pixels, the head scans eight reciprocations 16 times to complete printing.

FIG. 19 shows the control computer 107
An example of a control procedure for controlling the above-mentioned devices will be shown. Next, based on this flowchart, the control CPU in the print mode
The operation of 107 will be described.

First, in the printing process, step 1401
Perform various initial settings with. For example, in step 1401, various control data are set in the memory in the control CPU 107 from the CPU input / output device 108, for example, the teletype.
The control data includes, for example, each head registration value, print width value, initial speed value for trapezoidal drive control of the head feed pulse motor, number of rising and falling pulses, constant speed value.

Based on the input information in step 1401, the energization time of the head feed pulse motor 404 is calculated in step 1402. Register CNT in CPU 107
The number of pulses PM of the head feed pulse motor 404 by R
X is counted, but the value of the register is initialized in step 1403. In subsequent step 1404, the CPU 107 inputs the registration initial value to the presettable counter 1102 through the line 1101 (see FIG. 11). During this time, the paper width setting device 1109
Data is read from the print width control counter 1108. In step 1405, the event timer in the CPU 107 is set based on the set value in step 1401 and the timer is activated. In step 1406, an initial value for accessing the frame memory is set in the counter 1026 through the line 1205 (see FIG. 12). In this case, the address 127 is set,
Suppose it is down-counted.

In the next step 1407, the data is supplied from the latch circuit 801.

[0081]

[Outer 1]

If the contents can be judged to start printing (see FIG. 9),

[0083]

[Outside 2]

Therefore, the processing advances to step 1408. In the initial state, the IRST signal

[0085]

[Outside 3]

Therefore, the processing shifts to step 1408. In step 1408, the CPU 107 outputs the STR pulse signal to the above-mentioned latch circuit 801. As a result, the frame memory address set by the address counter unit 207 of FIG. 12 is released from the line 1209, the data is transferred to the buffer memory 104 by 16 bits, and this is performed 8 times for 4 pages of 4 colors, and the buffer memory 104 of each color is transferred. Store 128 bits of data in
Further, these 128-bit image data are subjected to nozzle switching 16 times 8 groups by the head driver circuits 1301 and 1302 of the head driver 105 to perform print control for 128 nozzles in total by hardware (see FIG. 14). Therefore, after step 1408, the image data is handled by hardware, and the control CPU 107 controls the pulse motor 404, the address control to the frame memory 103, and the head registration control for each color.

In step 1409, the CPU 107 outputs the registration advance pulse PX to the input terminal 1103 of the control board 205 (see FIG. 11). In the next step 1410, it is determined whether or not the value of the internal counter CNTR of the CPU 107, which indicates the sum of the head feed pulse motor steps for 512 pixels, is equal to or greater than a predetermined set value S _ALL , and if the determination is affirmative, 1 Since the line has been printed, step 1 to control the printing paper feed etc.
The routine proceeds to step 414 and thereafter. If the value of the counter CNTR is less than or equal to S _ALL , the printing of one line has not been completed, so the process proceeds to step 1411 and the pulse motor 405
Step forward. Here, the head feed pulse motor 404
Is generally designed to advance one pulse of 62.5 μm, the multi-nozzle head 410 is, for example, 8 lines /
mm, that is, if the nozzles are manufactured with a pitch of 125 μm, it is necessary to feed the head 410 at a pitch of 125 μm, and therefore, it is necessary to output a PMX pulse from the 2-pulse CPU 107 every time one line is printed. At the same time, in step 1411, the PMX total step count counter CN
Increment TR by +1. In step 1412, the CPU1 started in the previous step 1405.
It is determined whether or not the time set by the event timer built in 07 has elapsed. This is a pulse motor 40
When the pulse interval becomes short when activating No. 4, the motor 404 does not rotate, which is higher than the self-starting frequency, that is, a so-called step-out state is shown. Therefore, the pulse interval is initially set to a long time so that the acceleration torque of the pulse motor 404 becomes constant. This is because the value is set in step 1405 (step 1405) and shortened as the speed increases. To set these times, a time constant is calculated in advance at step 1402 and C
A so-called table lookup method is adopted in which the data is stored in the memory table of the PU 107 and is retrieved as needed. Therefore, in step 1412, an affirmative determination is made if the time calculated in step 1402 has elapsed,
Proceed to step 1413. However, the first of the head 410
When printing the second line, the processing of step 1405 does not make much sense, and when printing the second and subsequent lines, it functions as a timer that determines the drive cycle of the pulse motor 404 described above.

At step 1413, the first pulse motor operating pulse is output. The timer for step 1413 is activated in step 1420. This completes the printing operation for one line of the head, so step 1421
In the next step, the start address of the frame memory 103 to be printed next is determined and the address counter unit 2 in FIG.
07 up / down to line 1204 (UP / DW
N) control decisions and timer actuation are processed in parallel. In order to print the second line of the head, the head address of the second line may be set to 255 and the process may proceed in the subtraction direction, as shown in FIG. The head address a _N of the Nth line of the print head 410 is a _N = 127 ± 12
8 (N-1). The plus sign in the formula is the head 4
10 corresponds to the case of moving from the left side L to the right side of FIG. 15, and the minus sign corresponds to the case of moving from the right side R to the left side L. The print direction of these heads 410 is the control CPU
Since the determination is made inside the CPU 107 by the register provided in 107, this register is referred to when the address is calculated, and the addition code is determined. Also, of course,
A 1-bit rotation direction switching control signal is sent from the CPU 107 to the driver of the pulse motor 404.

At step 1422, the second pulse motor operating pulse is issued at step 1424, and therefore, the value of the counter CNTR is incremented by "+1" before that.
The time up of step 1420 is checked in step 1423. That is, in step 1423, it is determined whether the first pulse time width has elapsed. When a predetermined time has elapsed, the hard timer of the CPU 107 performs an interrupt process, and it is determined that the time is up. Therefore, the process goes through step 1423, and the second pulse motor operating pulse is output in step 1424, and then step 14
Return to 05. The second timer setting time is step 14
It is set in 05.

By the above control procedure, the frame memory 1
03, while controlling the generation of the registration pulse and the print width, the head 410 is driven line by line based on the input image data to print an image on the recording paper 403. When the 2048th line is printed, the start address to the frame memory 103 is 262143 as shown in FIG. When the data of 8 words from this head address is transferred from the frame memory 103 to the buffer memory 104 and printing is completed, the value of the counter CNTR becomes equal to the set value S _ALL, and therefore a positive determination is made in the determination procedure of step 1410 and step 1414. Then, the drive pulse is sent to the paper feed pulse motor 401, and the printing for one scan of the head is completed.

Therefore, in the next printing, the head 410 switches from the right side R to the left side L in the printing direction. Where 4
Assuming that the multi-nozzle head 410 of the book has cyan C, magenta M, yellow Y, and black BK from the left, black BK, when printing from left L to right R,
Yellow Y, magenta M, and cyan C are printed in this order, but when printing from right side R to left side L, cyan C, magenta M, yellow Y, and black BK are printed in that order. Therefore, it is necessary to replace the registration between the heads according to the printing direction, and therefore, in step 1415, the registration replacement work is performed. In this case, it is assumed that the four heads are mechanically arranged at equal pitches. This is because if the head-to-head pitch is misaligned, the registration will shift depending on the printing direction.

At the next step 1416, the initial address to the frame memory 103 is calculated. As is clear from FIG. 18B, the start address of the second head scan is 262135, which is the first head scan end address 262143 plus -8. At step 1417, which follows step 1417, the direction switching line to the pulse motor driver is reversed in response to the reversal of the head feed direction. As a result, printing for one scan of the head is completely completed, so the value NSCAN of the scanning counter register provided in the CPU 107 is set to "+".
1 "increment. In Step 1419,
The number of scans NSTOP previously input from the keyboard of the CPU input / output device 108 is compared with the above-mentioned counter value NSCAN, and when NSCAN is equal to or larger than NSTOP, printing is stopped. When NSCAN is smaller than NSTOP, the process returns to step 1403 and the same operation as described above is repeated.

The actual printing is performed by the bus 1113 in FIG.
It is controlled by the signal PRT sent from the. That is, the signal PRT enters the bus 1307 of FIG. 14 to control the printing, and the address increment pulse ADR. Control over whether or not to input PLS to the frame memory access address counter 1206 in FIG. 12 is also performed via the bus 1201. Therefore, even if the head address for frame memory access is input from the CPU 107 to the counter 1206 in FIG. 12, the signal PRT is not output to the bus 1113 unless both the registration and print width detection counters 1107 in FIG. 11 are enabled. The initial value of the frame memory address is output, the initial data of the address is input to the buffer memory 104, and the head driver 10
Even if the data is transmitted up to 5, the printing is stopped in the driver units 1301 and 1310, and the actual printing cannot be performed.

Although the above description has been mainly given in detail for one color and one page, the devices 205 and 2 of each block in FIG.
If 07, 208, and 209 are provided for each color and a page select switch for each color is provided, the internal circuits thereof are exactly the same.

As is clear from the above description, the color printing apparatus of the present embodiment adds the dither signal to the input image density and stores the upper bit in the line memory, and the compressed density data stored in the line memory. Is stored in the frame memory as a bit pattern through the pattern generator (pattern generator), and the image information is transferred to the buffer register for each minimum unit required for printing from the frame memory. Reciprocal printing can be facilitated and printing speed can be improved. Further, since the multi-nozzles are driven in a distributed manner without energizing at once, it is possible to reduce the head power supply capacity without decreasing the printing speed.

Furthermore, in this embodiment, the image information amount for multi-nozzles is serially arranged and divided into several groups, and the image signals are sent through the signal lines corresponding to the divided number, and each group is also sent. Since the serial image signal divided into two is distributed by the synchronizing signal for synchronizing with the nozzle to be printed, the number of electric signal supply lines to the moving head can be reduced, and the apparatus can be miniaturized. For example, in this embodiment, the nozzle cycle is 1 mse.
c. Simultaneous printing of 8 lines with energization width of 10 μsec and 512 × 512 pixel printing of 1 pixel in 4 × 4 matrix enables printing in about 20 seconds or less with paper feed time. A print was obtained.

In this embodiment, in order to improve the printing speed, the print head is scanned left-to-right and right-to-left for reciprocal printing, but the ink clumping order changes for each scan. Or, if the registration between the heads does not match mechanically, reciprocal printing cannot be performed, so
Printing is performed by unidirectional scanning. The one-way scan is
It can be easily realized by changing the address order.
One-way scanning printing is also included in the scope of the present invention because it can be easily found by referring to (A) and (B).

As described above, the conventional color printing apparatus has the drawback of being either expensive or slow in printing speed, but in this embodiment, the original image input density information is used as information. After compression, the compression information is converted into a density dot pattern and stored in the memory section, and the address of the memory section is controlled at the time of printing to reproduce and print the original image. Thus, reciprocal printing can be performed, thereby providing an extremely inexpensive and high-speed color printing device.

Therefore, according to the present embodiment, the image of the color printing apparatus which has been conventionally expensive and large is renewed and used not only as a color printing machine but also as various computer terminal apparatuses such as EDP and word processor, and facsimiles. Since it can be easily used in various fields as an output means of various video signal input sources, a great effect can be obtained in the information industry field.

[0100]

As described above, according to the present invention,
The start timing of supplying an address corresponding to a plurality of recording heads each, since the control according to the registration of each run <br/>査direction of reciprocal scanning between multiple recording heads, a plurality of recording heads It is possible to correct the registration in the reciprocal scanning between them with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a printing apparatus of the present invention.

FIG. 2 is a perspective view showing an example of an internal configuration of the input device of FIG.

FIG. 3 is a block diagram showing an example of a circuit configuration of the input device of FIG.

FIG. 4 is a block diagram showing an example of a configuration of an image processing unit in FIG.

5 is a block diagram showing an example of a configuration of the frame memory of FIG.

FIG. 6 is a signal waveform diagram showing an example of signal generation timing in the devices of FIGS. 3 to 5.

FIG. 7 is a signal waveform diagram showing an example of signal generation timing in the devices of FIGS. 3 to 5;

8 is a block diagram mainly showing an example of a configuration of a buffer memory in FIG.

9 is a block diagram showing an example of a configuration of the controller of FIG.

10A and 10B are signal waveform diagrams showing timings of output waveforms of the controller of FIG. 9, respectively.

11 is a block diagram showing an example of a configuration of the control board of FIG.

12 is a block diagram showing an example of a configuration of an address counter section in FIG.

13 is a block diagram showing an example of a configuration of the latch circuit of FIG.

FIG. 14 is a block diagram showing an example of a configuration of the driver of FIG. 1 or 8.

FIG. 15 is a perspective view showing an example of a configuration of the output device of FIG.

16A to 16D are an enlarged front view of a main part, a plan view of the main part, a cross-sectional view of the main part, and an overall plan view showing an example of the configuration of the nozzle of the head of FIG.

17 is a diagram showing an example of an array relationship between addresses and data in the frame memory of FIG.

18A and 18B are diagrams showing an example of a correspondence relationship between data in a frame memory and a print address.

FIG. 19 is a flowchart showing an example of a control operation of the control computer of FIG. 1 or 8.

[Explanation of symbols]

101 Input Device 102 Image Processing Unit 103 Frame Memory 104 Buffer Memory 105 Driver 106 Output Device 107 Control Computer (CPU) 108 CPU Input / Output Device 501 Light Source 502 Cooling Fan Motor 503 Reflector 504 Heat Absorption Filter 505 Optical System 506 Slit Plate 507 Film Storage device 508 Sprocket 509 Color film 510 Film screen 511 Film feed drive motor 512 Film position detector 513R Optical receiver (CCD) 514R Optical system 515 Optical system 516B Optical receiver (CCD) 517B Optical system 518,519 Dichroic mirror 520G Optical system Light receiver (CCD) 309 Amplifier 315R Video amplifier 316R Analog-to-digital converter 317 ADC Sampling tie NG film 319 Film position detection signal line 320R Data line 322 Sampling pulse line 323 Clock pulse line 324 Film feed pulse motor signal line 325 Power line 350R Digital adder 351R Line memory 352C Pattern generator 353C Parallel register (latch register) 354R, 355R, 356R Data line 357C, 358C Pattern line 359 Dither signal line 360, 362 Address and control line 363 Counter 364 Line memory address counter 365 Pattern generator address counter 366 Parallel register address register 367,368 Advance pulse 369 Initial value setting data Line 370,371 Control line 373 Signal line 381 page memory 382Y data output line 383 page memory address control line 384 counter 385 initial address setting line 386 increment and decrement pulse line 109A, 109B communication line 110 control line 111A control bus line 204 control board 205 control board 206 controller (control) Substrate) 207 Address counter unit 208 Latch circuit (buffer memory) 211 Control circuit 213 Data bus 214 Address bus 219 to 237, 240, 241 Line 238, 239 Pulse motor (= 404) 801, 805, 814, 828 Latch circuit (flip-flop) ) 802, 804, 806, 809, 815, 823, 8
26,836,837 OR gate 803,807,816,817,829 AND gate 808,819,824,832,838 Counter 810,820 Comparator 811,821 Setter 818,822,827,830,834,835, T
1, T7 timer 825, 833 decoder 831 safety circuit 1101 registration setting value reading port 1102 presettable counter 1103 control pulse input terminal 1104 output line 1105, 1106 AND gate 1107 line 1108 print width control counter 1109 print width setting switch ( Paper width setting device) 1110 Color setting device (page setting device) 1111 Selector circuit 1112 line 1113 4 bit line 1201 Print start command signal line 1202 Selection switch 1203 AND gate 1204 Up / down control line 1205 Frame memory address initial value setting line 1206 Up / down counter 1208 Line driver 1212 Comparator 1214 Address counter Board page setter 120 , 1209,1210,1211,1213,
1215 line 1001 OR gate 1002 16-bit data bus line 1003 page select setting device 1004 comparator 1005 AND gate 1006 parallel serial register 1007 shift register 1008 buffer memory 1009 output line 1301, 1302 head driver unit 1303, 1304 multiplexer 1305 switching code signal line 1306 1307 line 1308 NAND gate 1309 input terminal 1310 output terminal 1311 NOR gate 401 printing paper feed motor 402 paper feed roller 403 printing paper 404 drive motor 405 timing belt 406 gear 407, 415 head unit moving position detection device 408 guide rail 409, 409Y power supply cable 410, 410Y for printing Head (4 color recording head unit) 411, 411Y Ink supply pipe 412, 412Y Ink tank 413 Connector 414 Flexible wiring board 416 Common moving base (carriage) 1501 Polyimide layer 1502 Aluminum layer 1503 Heating element layer 1504 Silicon dioxide (ceramic) layer 1504 ′ Silicon substrate 1505 Substrate support 1506 Heating element unit 1507 Ink supply pipe 1508 Glass substrate 1509 Head unit support metal fittings 1510 Common electrode 1511 Base agent 1513 Lead wire section 1401 to 1424 Control procedure PMX Pulmotor X pulse CNTR PMX counter REG resist PCNT address Preset RDY / BSY print check STR start pulse PX resist, print width counter Step pulse S _ALL PMX Total pulse NSCAN Scan count counter NSTOP Total scan count

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location B41J 3/04 101 A (72) Inventor Nobutoshi Mizusawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Kya Non-Incorporated (72) Inventor Shoji Ota 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) Reference JP-A-53-102036 (JP, A)

Claims (2)

[Claims] 1. A plurality of print heads, which are arranged at a predetermined interval in the scanning direction and have different print colors , and print data corresponding to each of the plurality of print heads are recorded.
A memory for storing the data based on the dress, and an address corresponding to each of the plurality of recording heads is supplied to the memory along with the reciprocal scanning of the plurality of recording heads, and the stored recording data is supplied to each of the corresponding recording heads. Read-out means for reading and start timing for the read-out means to supply addresses corresponding to each of the plurality of recording heads to the memory,
And a timing control unit that controls the reciprocating scanning between the plurality of recording heads in accordance with registration in each scanning direction. 2. The printing apparatus according to claim 1, wherein the plurality of recording heads eject ink of different colors.