JPH0795705B2 - Backup line switching control circuit - Google Patents

Description

The present invention relates to a transmission device having a working line and a protection line, and more particularly, to a control circuit for preferentially controlling switching to the protection line when the working line requiring priority processing becomes abnormal. I want to give priority to using the protection line when the protection line is in operation.The purpose is to provide a protection line switching control circuit that can prioritize and switch to the protection line even if an error occurs on the service line later. When the switching information issued later by the switching control unit is a switching signal to another channel, after the latch means is cleared by the signal developed by the switchback decoder for the switching back signal for the previous channel switching signal. As long as the other channel is switched to the protection line, the priority channel switching control means detects a signal requesting priority processing from the advance channel switching signal already held in the latch means. In this case, the priority channel switching control means holds the previous channel switching signal held in the latch means, clears the signal held in the latch means, and sends a switching signal for switching the subsequent channel to the protection line. The latch means is configured to hold and output.

[Industrial application field]

The present invention relates to a transmission device having a working line and a protection line, and more particularly to a control circuit for preferentially controlling switching to the protection line when the working line requiring priority processing becomes abnormal.

For example, in a transmission device in which one protection line is prepared for n service lines, if one of the n service lines becomes abnormal, that line is switched to the protection line and operated through the protection line. To be done.

At this time, in order to switch back to the normal working line once switched to the standby line, the current control method causes an error in another working line unless a switchback command is issued, and Even if a switching command is issued, it cannot respond to the switching.

Therefore, for example, even if an important line becomes abnormal and priority processing is required, it cannot be switched when the protection line is already in operation.

If such an important line becomes abnormal and priority processing is required,
It is necessary that the switching process be prioritized even if the process occurs later.

[Conventional technology]

FIG. 4 is a diagram for explaining the status of issuing switching information to the protection line switching control circuit, FIG. 5 is a diagram for explaining a conventional example of the protection line switching control circuit, and FIG. 6 is a diagram for explaining a conventional example of the protection line switching control circuit. The figure explaining each switching control example is shown.

FIG. 4 shows an outline of the configuration of a transmission device in which n channels (CH1 to CHn) are used as regular lines and one channel is set as a standby line. This is composed of two switch units 1 and 2 and a switching control unit 4.
The switch units 1 and 2 are provided on the input side and the output side of the n normal lines for signal transmission and one protection line, and the protection line switching control circuits 3a and 3b are mounted therein. ing.

On the other hand, the switching control unit 4 synchronously controls ON / OFF and switching of the switch units 1 and 2 via the protection line switching control circuits 3a and 3b, and disconnects the common line from a monitoring / alarm panel (not shown). By detecting the alarm (ALM1 to ALMn) that is issued when the switch is not usable,
A switching control command is issued to the internal protection line switching control circuits 3a and 3b.

The alarm (ALM1 to ALMn) signals are alarms issued corresponding to each common line.

The standby line switching control circuits 3a and 3b in the switch units 1 and 2 and the switching control unit 4 are connected by a bus, and the same content is used as switching control information from the switching control unit 4 to the standby line switching control circuits 3a and 3b. Is.

That is, the switching control information includes a chip select signal for selecting the switching CH, a clock CLK designating the switching timing, and an 8-bit serial code designating the switching CH.

Protection line switching control circuit for receiving such switching control information
A detailed configuration of 3a and 3b is shown in FIG. 5, and the configuration includes a serial / parallel conversion circuit 31, a decoder 32, and a latch section 33.
A logical OR circuit (hereinafter referred to as an OR circuit) 34 and a switchback decoder 35.

The serial / parallel conversion circuit 31 shown in FIG. 5 converts the 8-bit serial code sent from the switching control section 4 shown in FIG. 4 into an 8-bit parallel code. , 8 from the serial / parallel conversion circuit 31
The parallel code of bits is expanded to a CH-compatible switching signal (CH1 switching signal to CHn switching signal), and the latch unit 33 expands the CH switching signal (CH1 switching signal to CHn switching signal) in the decoder 32. The OR circuit 34 logically ORs the CH switching signals in the output state in order to hold the output of the decoder 32, and the OR circuit 34 configures the CH
It is fed back as a holding signal to the corresponding latch circuits 33 (1) to 33 (n), and the switchback decoder 35 has a switchback code for recovering the switching of the 8-bit serial code to the protection line. In the case of, the signal is detected and developed into a signal for clearing the latch unit 33.

Next, details of the switch switching information output from the switching control unit 4 to the protection line switching control circuits 3a and 3b having the above-described configuration are shown in FIG.

That is, the 8-bit serial code output from the switching control unit 4 is "000000" shown in Examples 1 to 3 of FIG.
It is displayed as 01 "," 00000010 "," 10000000 ", etc. After this serial code was output, the chip select signal rose and the serial code was instructed.
The CH is selected, and the timing for switching to the selected CH is specified by the clock CLK.

In addition, the serial code of this example changes CH1 switching to “0000000
1 ", code for requesting priority processing even in case of later switching of CH2," 00000010 ", switchback code for returning from standby line to regular line," 10000000 ", code for CH switching, failback or no CH switching This is the case where a code having no meaning other than "00000011" is set.

Further, switching signals CH1 to CHn in the figure are signals which are developed by expanding the above-mentioned serial code by the protection line switching control circuits 3a and 3b shown in FIG. 5, and show the output state at the rising edge.

Here, the example 1 in FIG. 6 is the case where the code "00000011" having no meaning is issued after the CH1 switching code "00000001", and the example 2 is from the starter after the CH1 switching code "00000001". This is the case when the CH2 switching code "00000010" is issued that requests the switching with priority (requesting the later arrival priority). In Example 3, the switchback code "10000000" is issued after the CH1 switching code "00000001". That is the case.

Next, the hold signal is for holding the CH switching signal in the output state, as described in FIG. 5, and shows the output state at the rising edge.

In the following, generally, the output state of signals and the like will be indicated by "H", and the non-output state or zero state will be indicated by "L".

For example, in a normal state in which no abnormality has occurred, the protection line switching control circuits 3a and 3b send "00000000" to the switching control unit 4.
Receive the serial code of.

Even if the decoder 32 expands this, the switching signals of each CH1 to CHn are all in the "L" state, so that the holding signal which is the output obtained by ORing these is also "L".

Each of the latch circuits 33 (1) to 33 (n) is expanded by the decoder 32 based on the 8-bit parallel code when the output (corresponding to the clock) obtained by ORing the OR circuits 34 is "L". Was
CH switching signal is output as it is without switching.

Next, for example, when CH1 becomes abnormal and the protection line is unused, the serial code "00000001" indicates the protection line switching control circuit 3a, as shown on the left side of Examples 1 to 3 in FIG.
3b, and the decoder 32 expands the CH1 switching signal to “H” and outputs it.

In this case, when the protection line is already used, switching to CH1 is disabled because the corresponding latch circuit 33 (1) is cleared by another CH switching signal.

Next, when the CH1 switching signal is output at "H", the output of the OR circuit 34 also becomes "H", and the latch circuit 33 (1) latches the CH1 switching signal at the rising time of the hold signal which is the output of the OR circuit 34. And hold.

While continuing to hold the CH1 switching signal in the latch circuit 33 (1), another switching instruction code, for example, CH shown in Example 2 of FIG. 6 is used.
Code "0" that gives priority to processing of switching 2
0000010 ", a switching instruction code, a switchback code, or a meaningless code that has no meaning other than a code indicating no switching (the next occurrence of" 00000011 "in Example 1 in FIG. 6) is ignored. , CH1 switching signal will be output continuously.

Next, when CH1 returns to the normal state, the protection line switching control circuit 3
The states a and 3b receive the serial code "10000000" and are expanded by the switchback decoder 35 are shown in Example 3 of FIG.

That is, the serial / parallel conversion circuit 31 converts the serial code “10000000” into a parallel code, and the switchback decoder 35 detects the serial code and outputs the expanded signal as “H”. All the latch circuits 33 (1) to 33 (n) in 33 are cleared.

At this time, since the decoder 32 expands "L", the latch unit
33 continues until the CH1 switching signal clears the latch unit 33.

Next, since the latch circuit 33 (1) in the latch unit 33 is cleared, the CH1 switching signal and the holding signal of the OR circuit 34 return to “L”, the standby line is released from the operating state, and the next CH switching is performed. The instruction code can be accepted.

In addition, in the example 2 of FIG. 6, the CH2 switching code "0000001" that requests the late arrival priority switching after the serial code "00000001"
Even if "0" is issued from the switching control unit 4 shown in FIG. 4, since the switchback code "10000000" has not been expanded before that, it is not possible to switch to CH2, and therefore the CH2 switching signal is not output. It shows the state where the CH1 switching signal is continuously output.

[Problems to be Solved by the Invention]

As described above, the protection line switching control circuits 3a and 3b shown in FIG.
In the conventional example, if the standby line is in the operating state after switching once, the switching code to another CH is changed unless the operating state (“H” state) of the standby line is cleared by the switchback signal. If you receive it, ignore it.

That is, for example, even if the service line that wants to preferentially use the protection line becomes abnormal, if the protection line is in operation at that time, it cannot be switched to the protection line unless the switchback signal is detected.

The present invention provides a protection line switching control circuit that can preferentially switch to a protection line even if an abnormality occurs in the service line that wants to preferentially use the protection line when the protection line is in operation. With the goal.

[Means for Solving the Problems]

FIG. 1 shows a diagram for explaining the principle of the protection line switching control circuit of the present invention.

The principle diagram of the protection line switching control circuit 3'of the present invention shown in FIG. 1 is the decoder 32 and the switchback decoder 35 described in FIG.
In addition, a latch means 330 and a priority channel switching control means 340 are newly provided and configured. The above-mentioned latch means 330 holds a channel switching signal developed by the decoder 32, and the priority channel switching control is performed. The means 340, while holding one channel switching signal in the latch means 330, detects a code requesting priority switching as information for requesting the next channel switching, and prioritizes the subsequent channel switching signal. The above-mentioned means is provided to provide control for switching.

[Work]

While the decoder 32 develops the channel switching information input from the switching control unit 4 which instructs switching from the regular channel to the spare channel, and while holding this as the CH switching signal in the latch means 330, Even if channel switching information is input, the next channel switching cannot be performed unless the latch means 330 is cleared by the switchback decoder 35, and the previous CH switching signal is retained in the latch means 330.

On the other hand, if the next channel switching information is a late arrival priority processing signal requesting priority processing over the first channel switching signal,
Priority channel switching control means 340 that has detected this signal,
While holding the CH switching signal currently being sent which is being held in the latch means 330, the latch means 330 clears the holding of the preceding CH switching signal and holds the CH switching signal corresponding to the late arrival priority switching information with priority. Send it out.

Then, when the processing corresponding to the late arrival priority switching processing is completed, the priority channel switching control means 340 sets the pending CH switching signal of the starter in the latch means 330 and sends the corresponding CH switching signal.

By performing the above-mentioned processing, even when the protection line is in operation, when the signal for the late arrival priority processing is detected, it is possible to immediately and preferentially switch the signal.

〔Example〕

The gist of the present invention will be specifically described below with reference to the embodiments shown in FIGS. 2 and 3.

FIG. 2 is a diagram for explaining an embodiment of the protection line switching control circuit of the present invention, and FIG. 3 is a diagram for explaining a time chart in the embodiment of the protection line switching control circuit of the present invention. The same reference numerals denote the same objects throughout the drawings.

The embodiment of the protection line switching control circuits 3c and 3d of the present invention shown in FIG. 2 is a latch means 330 which constitutes the protection line switching control circuit 3'described in FIG. In this example, the priority CH switching control unit 340a is configured as 340.

In addition, this embodiment shown in FIG.
In addition to 40a, a serial / parallel conversion circuit 31, a decoder 32, and a switchback decoder 35 that perform the same operation as described in FIG. 5 are provided.

In addition, this embodiment shown in FIG. 2 has three working lines (CH1 to C).
H3) and one protection line. FIG. 3 shows the serial code, the chip select signal and the serial code instructed by the switching control unit 4 shown in FIG. 4 in the above embodiment. Based on three examples, the output states of the CH switching signals developed by the protection line switching control circuits 3c and 3d are shown.

Further, Examples 1 to 3 in FIG. 3 are operation examples when the same serial code as in Examples 1 to 3 described in FIG. 6 is input from the switching control unit 4 shown in FIG. The same code is used in the example of the serial code.

Next, the reset signals 1 to 3 (D to F) in FIG. 6 are applied to the latch circuit 330 constituting the latch section 330a shown in FIG.
This is a signal for setting the outputs of (1) to 330 (3) to "L" or "H".

The latch section 330a of the present embodiment shown in FIG. 2 is composed of three latch circuits 330 (1) to 330 (SR type flip-flop circuits).
It consists of (3).

The reset signals 1 to 3 (D to F) described above are sent to the reset terminal R of the SR type flip-flop circuit forming the latch circuits 330 (1) to 330 (3), and
The outputs A to C developed in 32 are sent to the set terminal S.

Normally, when the set terminal S is "H" and the reset terminal R is "L", the SR type flip-flop circuit outputs its positive output Q "H", and the reset terminal R is "H" and the set terminal S is In the case of "L", the positive output Q outputs "L".

Next, the priority CH switching control unit 340a of the present embodiment shown in FIG. 2 comprises a priority CH switching detection unit 340b and a reset signal generation unit 340c, and the priority CH switching detection unit 340b outputs an output requesting priority switching. B
When the decoder 32 expands to "H", it detects this and holds the CH switching signal in the "H" state until then. The reset signal creating unit 340c outputs the outputs A to C expanded by the decoder 32. And the signals from the priority CH switching detection unit 340b to output signals D to F (reset signals 1 to 3) for setting the outputs of the latch circuits 330 (1) to 330 (3) to "L" or "H". It is created and output.

If a non-significant code “00000011” other than a code requesting switching for each CH or a code not requesting switching for CH is detected from the serial code converted by the decoder 32 into parallel code by the serial / parallel conversion circuit 31 , Its outputs A to C are expanded so as to continue the CH switching signal so far.

On the other hand, when the serial code is the code "00000001" for switching CH1 to the protection line as shown in Examples 1 to 3 of FIG. 3, the decoder 32 develops it into the CH1 switching signal and outputs its output A as "H". To do.

Then, when the chip select signal becomes "H", CH1
CH1 switching signal (corresponding to output A) to select switching
Is latched in the latch circuit 330 (1) and output.

At this time, the reset signal generator 340c causes the latch circuit 330 to
A signal for resetting the outputs of the latch circuits 330 (2), 330 (3) other than (1) to "L" when the output A rises.
Create E and F.

However, when the CH3 switching signal is latched by the latch unit 330a before the code “00000001”, the output D, E of the reset signal generation unit 340c is changed by the output C “H” of the decoder 32.
Becomes "H" and the latch circuits 330 (1) and 330 (2) are reset, so the CH1 switching signal is sent to the latch circuit 330 (1).
I can't hold it.

In the present embodiment, if the pre-defined switchback code "10000000" is input and detected by the switchback decoder 35, the signal developed by the switchback decoder 35 is the latch circuit 330 ( Clear all 1) to 330 (3) at the same time. The processing after the clearing is the same as that described in FIG.

Also, the time chart at this time is, as shown in Example 3 of Fig. 3, that the CH1 switching signal in the output state is cleared and changes from "H" to "L", and the reset signals 2 and 3 (outputs E and F) are also " L ".

Next, the switching information input to the protection line switching control circuits 3c and 3d is issued as the next issue of the example 1 in FIG. 3 and is a code requesting switching for each CH or a code not requesting switching for CH. Code that has no meaning other than "00000011"
At this time, the outputs A to C of the decoder 32 are output as "L".

Therefore, the CH1 switching signal thus far held in the latch circuit 330 (1) is continuously sent.

At this time, the outputs E and F of the reset signal generation unit 340c become "H" and are reset to the latch circuits 330 (2) and 330 (3), so that the outputs of the latch circuits 330 (2) and 330 (3) are output. Holds "L".

Next, if the late arrival priority code "00000010", which is the information requesting the priority processing, is input even if it is a latecomer that is predefined in the state where the CH1 switching signal is being output as in Example 2 of FIG. The result of conversion by the serial / parallel conversion circuit 31 and expansion by the decoder 32 sets the output B to "H".

When the output B becomes "H", the priority CH switching detection unit 340b
When this is detected, the CH1 switching signal being output is internally held, "H" of the output B of this decoder 32 is drawn into the reset signal generating section 340c, and reset based on the signal from the priority CH switching detecting section 340b. The signals 1 and 3 (outputs D and F) are set to "H" to reset the corresponding latch circuits 330 (1) and 330 (3).

On the other hand, the latch circuit 330 (2) holds "H" of the output B as a CH2 switching signal and outputs this CH2 switching signal.

Next, when the CH2 switching processing of the priority processing request is completed, the output B of the decoder 32 becomes "L", so that the CH2 switching signal becomes "L".

Priority CH switching detector 340b that was monitoring this CH2 switching signal
Generates a signal D for setting the held and held CH1 switching signal to "H" by the reset signal creating unit 340c, so that the output of the latch circuit 330 (1) becomes "H". Reset and output CH1 switching signal again.

As described above, in the embodiment of the present invention, as shown in Examples 1 to 3 in FIG. 3, when the request for the subsequent priority processing is made, the CH switching signal in operation is held even if there is no switchback signal, It is possible to immediately respond to the request for the subsequent priority process.

〔The invention's effect〕

According to the present invention as described above, even if the protection line is in operation, when the last-arrival priority switching code is input, the working line corresponding to the last-arriving priority switching code can be immediately switched to the protection line switching. A control circuit can be provided.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the backup line switching control circuit of the present invention, FIG. 2 is a diagram for explaining an embodiment of the backup line switching control circuit of the present invention, and FIG. 3 is a backup line switching control of the present invention. FIG. 4 is a diagram for explaining a time chart in the embodiment of the circuit, FIG. 4 is a diagram for explaining the issuance status of switching information to the protection line switching control circuit, and FIG. 5 is a diagram for explaining a conventional example of the protection line switching control circuit. FIG. 6 is a diagram for explaining a switching control example of the protection line switching control circuit, respectively. In the figure, 1 and 2 are switch units, 3a to 3d and 3'are backup line switching control circuits, 4 is a switching control unit, 31 is a serial / parallel conversion circuit, 32 is a decoder, 33 and 330a are latch units, 33 (1 ) -33 (n), 330 (1) -330 (3) is a latch circuit, 34 is an OR circuit, 35 is a switchback decoder, 330 is a latch means, 340 is a priority channel switching control means, and 340a is a priority CH switching. A control unit, 340b is a priority CH switching detection unit, and 340c is a reset signal generation unit.

Claims (1)

[Claims] 1. A switching control unit (4) for detecting an unusable line of a plurality of regular lines and issuing information for switching to a protection line, and receiving switching information from the switching control unit (4). Decoder (32) for developing a signal for switching to the protection line
And a protection line switching control circuit (3 ') having a switchback decoder (35) for detecting a signal for switching back the protection line to the normal line, the decoder (32) comprising: Latch means (330) for holding the expanded channel switching signal, and when a signal requesting priority switching over the preceding signal is detected from the subsequent signal expanded by the decoder (32), the subsequent channel switching signal And a priority channel switching control means (340) for performing control for preferentially switching, when the switching information issued subsequently by the switching control unit (4) is a switching signal to another channel, Only after the latch means (330) is cleared by the signal developed by the switchback decoder (35) from the switchback signal for the preceding channel switching signal from the switching control section (4), the other channel is switched. When the priority channel switching control means (340) detects a signal requesting priority processing from the advance channel switching signal already held in the latch means (330), the priority channel switching control is performed. The means (340) is the latch means (330).
Hold the current channel switching signal held by the latch means (330), clear the signal held by the latch means (330), and switch the switching signal for switching the subsequent channel to the protection line by the latch means (330). ) To hold and output the backup line switching control circuit.