JPH0794680A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

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Publication number
JPH0794680A
JPH0794680A JP5236136A JP23613693A JPH0794680A JP H0794680 A JPH0794680 A JP H0794680A JP 5236136 A JP5236136 A JP 5236136A JP 23613693 A JP23613693 A JP 23613693A JP H0794680 A JPH0794680 A JP H0794680A
Authority
JP
Japan
Prior art keywords
film
layer
ruo
electrode
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5236136A
Other languages
Japanese (ja)
Inventor
Kota Yoshikawa
浩太 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5236136A priority Critical patent/JPH0794680A/en
Publication of JPH0794680A publication Critical patent/JPH0794680A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To improve contact with a substrate without sacrifice of oxygen barrier properties while preventing production of hillock in the formation of a conductive oxide electrode. CONSTITUTION:When a two layer electrode of ruthenium oxide (RuO2) 5/ Ruthenium(Ru) 4 is formed as the lower electrode of a capacitor on a semiconductor substrate using a dielectric oxide film 6, a first layer 4 of Ru is grown under the conditions that 300Angstrom <d<500Angstrom and 300 deg.C<Ts<450 deg.C where (d) is the film thickness and Ts is the substrate temperature whereas a second layer 5 of RuO2 is grown under the conditions that 1000Angstrom <d<3000Angstrom and 350 deg.C<Ts< 700 deg.C. A conductive oxide 5 is also grown as the lower electrode of the capacitor under a lowest crystal growth temperature or at a highest growth rate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
係り, 特に, キャパシタの下部電極として導電性酸化
物,例えば酸化ルテニウム(RuO2)及びルテニウム(Ru)の
2層膜を形成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a two-layer film of a conductive oxide such as ruthenium oxide (RuO 2 ) and ruthenium (Ru) as a lower electrode of a capacitor. Regarding

【0002】DRAMの高集積化, 微細化にともない, キャ
パシタの誘電体膜として高い誘電率を有する酸化物誘電
体が検討されている。この際,導電性酸化物がキャパシ
タの下部電極として多く用いられている。
Along with the high integration and miniaturization of DRAMs, oxide dielectrics having a high dielectric constant have been studied as dielectric films for capacitors. At this time, a conductive oxide is often used as the lower electrode of the capacitor.

【0003】[0003]

【従来の技術】現在の1トランジスタ/1キャパシタで
構成されるメモリセルを有するDRAMにおいては,キャパ
シタの下部電極はトランジスタのソース/ドレインに接
続されねばならない。従って,下部電極はシリコン(Si)
基板に設けられた拡散層,あるいはシリコン基板上に形
成された金属膜で構成される。
2. Description of the Related Art In a current DRAM having a memory cell composed of one transistor / one capacitor, the lower electrode of the capacitor must be connected to the source / drain of the transistor. Therefore, the lower electrode is silicon (Si)
It is composed of a diffusion layer provided on the substrate or a metal film formed on a silicon substrate.

【0004】シリコンを電極として酸化物誘電体膜を形
成すると,その界面に二酸化シリコン(SiO2)膜が形成さ
れて実効的な誘電率は低下してしまう。シリコン上に金
属電極を形成する場合は,白金(Pt)/タンタル(Ta)の複
合電極が検討されているが,その上に酸化物誘電体膜を
形成した場合には,白金が酸素を透過するため,実際に
はタンタルが酸化されてしまい, シリコン基板とコンタ
クトできなくなってしまう。
When an oxide dielectric film is formed by using silicon as an electrode, a silicon dioxide (SiO 2 ) film is formed on the interface and the effective dielectric constant is lowered. When forming a metal electrode on silicon, a composite electrode of platinum (Pt) / tantalum (Ta) has been studied, but when an oxide dielectric film is formed on it, platinum permeates oxygen. As a result, tantalum is actually oxidized and it becomes impossible to make contact with the silicon substrate.

【0005】このために, 酸素のバリア性に優れた導電
性酸化物電極が検討されている。導電性酸化物電極とし
てのRuO2/Ru の2層構造の電極は,RuO2層が有効な酸素
バリアとなり,その下のRu層がRuO2層を形成する際の酸
素バリア層層として機能する。
For this reason, conductive oxide electrodes having excellent oxygen barrier properties have been investigated. The RuO 2 / Ru two-layer structure electrode as a conductive oxide electrode has the RuO 2 layer as an effective oxygen barrier, and the underlying Ru layer functions as an oxygen barrier layer layer when forming the RuO 2 layer. .

【0006】[0006]

【発明が解決しようとする課題】RuO2/Ru の2層構造の
電極をシリコン基板上に形成する場合,最初にシリコン
上に直接形成されるRuのシリサイド化によるRu層および
RuO2層の凹凸が問題となる。また,それぞれの層の膜厚
によっては応力による歪みからRuO2層にヒロック(突
起)を生じる。また,RuO2層の酸素にたいするバリア性
に臨界的な膜厚が存在することがわかった。
When an electrode having a two-layer structure of RuO 2 / Ru is formed on a silicon substrate, first, a Ru layer formed by silicidation of Ru formed directly on silicon and
The unevenness of the RuO 2 layer becomes a problem. Also, depending on the film thickness of each layer, hillocks (protrusions) are generated in the RuO 2 layer due to strain due to stress. It was also found that there is a critical film thickness for the barrier property against oxygen in the RuO 2 layer.

【0007】また,一般的に下部電極として用いられる
導電性酸化物は柱状結晶を形成しやすく,このため結晶
粒界を通じて酸素を通過させてしまうという問題があ
る。本発明は酸化物導電性電極,例えばRuO2/Ru の2層
構造の電極形成において,酸素のバリア性を損なわず,
且つ電極にヒロックの発生を防止することを目的とす
る。
In addition, the conductive oxide generally used as the lower electrode easily forms columnar crystals, which causes a problem that oxygen is allowed to pass through the crystal grain boundaries. The present invention does not impair the oxygen barrier property in forming an oxide conductive electrode, for example, an electrode having a two-layer structure of RuO 2 / Ru,
Moreover, the purpose is to prevent the generation of hillocks on the electrodes.

【0008】[0008]

【課題を解決するための手段】上記課題の解決は,1)
半導体基板上に酸化物誘電体膜を用いたキャパシタの下
部電極として酸化ルテニウム(RuO2)/ルテニウム(Ru)の
2層構造の電極を形成するに際し,第1層目のRu膜の成
長条件として, 膜厚dを 300Å<d< 500Åとし,基板
温度TS を 300℃<TS < 450℃とし,第2層目のRuO2
膜の成長条件として, 膜厚dを1000Å<d<3000Åと
し,基板温度TS を 350℃<TS < 700℃とする半導体
装置の製造方法,あるいは2)半導体基板上に酸化物誘
電体膜を用いたキャパシタの下部電極として導電性酸化
物を, 結晶成長が可能な最低温度または最高成長速度で
成長する半導体装置の製造方法により達成される。
[Means for Solving the Problems] 1)
When forming a ruthenium oxide (RuO 2 ) / ruthenium (Ru) two-layer structure electrode as the lower electrode of a capacitor using an oxide dielectric film on a semiconductor substrate, the growth conditions for the first Ru film are The film thickness d is 300Å <d <500Å, the substrate temperature T S is 300 ° C. <T S <450 ° C., and the second layer of RuO 2
As a film growth condition, a film thickness d is set to 1000Å <d <3000Å and a substrate temperature T S is set to 350 ° C. <T S <700 ° C., or 2) an oxide dielectric film on a semiconductor substrate. This can be achieved by a method of manufacturing a semiconductor device in which a conductive oxide is grown as the lower electrode of a capacitor using GaN at the lowest temperature or the highest growth rate that allows crystal growth.

【0009】[0009]

【作用】本発明者はRuO2/Ru の2層構造の電極形成にお
いて,酸素のバリア性を損なわず且つヒロックを生じな
いRuO2/Ru の成長条件として下記の範囲を実験的に確か
めた。 (1) 第1層目のRu層の成長条件として, 膜厚dを 300Å
<d< 500Åとし,成長温度 (基板温度) TS を 300℃
<TS < 450℃とする。 (2) 第2層目のRuO2層の成長条件として, 膜厚dを1000
Å<d<3000Åとし,成長温度 (基板温度) TS を 350
℃<TS < 700℃とする。
The present inventor has experimentally confirmed the following range as the growth conditions of RuO 2 / Ru that does not impair the oxygen barrier property and does not cause hillocks in the formation of a RuO 2 / Ru two-layer structure electrode. (1) As the growth condition of the first Ru layer, the film thickness d is 300Å
<D <500Å, growth temperature (substrate temperature) T S is 300 ° C
<T S <450 ° C. (2) As the growth condition of the second RuO 2 layer, the film thickness d is 1000
Å <d <3000Å, growth temperature (substrate temperature) T S of 350
℃ <T S <700 ℃.

【0010】この条件で成長したRuO2/Ru の2層構造の
電極はRuO2の表面にヒロックの形成及び表面のうねりを
抑えることができ,また酸素(O2)のバリア性の優れた電
極を形成できる(図2参照)。
The RuO 2 / Ru two-layer structure electrode grown under these conditions can suppress formation of hillocks on the surface of RuO 2 and undulation of the surface, and has excellent oxygen (O 2 ) barrier property. Can be formed (see FIG. 2).

【0011】また,一般的には酸化物導電性電極を成長
する際,前記柱状結晶の成長を抑えるため結晶成長の最
低温度で成長するか,あるいは高速成長を行う。次に,
上記の限界を越えるとどのように不都合を生じるかを実
験結果より説明する。 (1) に対して, 300Å>d:Ru膜の酸素バリア効果を示す限界値以下の
領域で, この場合はSi表面は酸化する。
Further, in general, when the oxide conductive electrode is grown, it is grown at the minimum crystal growth temperature or is grown at a high speed in order to suppress the growth of the columnar crystals. next,
Experimental results will explain how disadvantages occur when the above limit is exceeded. In contrast to (1), 300Å> d: In the region below the limit value indicating the oxygen barrier effect of the Ru film, the Si surface is oxidized in this case.

【0012】 d> 500Å:ストレスによるヒロックの形成が起こる。 300℃>TS :結晶性が悪くなる。 TS > 450℃:ヒロックが形成する。 (2) に対して, 1000Å>d:酸素に対するバリア性が十分でなく, 下層
のRu膜へ大量の酸素が漏れてしまう。
D> 500Å: hillock formation occurs due to stress. 300 ° C.> T S : Crystallinity deteriorates. T S > 450 ° C .: Hillock is formed. In contrast to (2), 1000Å> d: The barrier property against oxygen is not sufficient, and a large amount of oxygen leaks to the underlying Ru film.

【0013】 d>3000Å:ストレスによるヒロックの形成が起こる。 350℃>TS :結晶性が悪く, 上部に高誘電体膜を形成
した際に, これと反応してしまう。
D> 3000Å: hillock formation occurs due to stress. 350 ° C.> T S : The crystallinity is poor, and when a high dielectric film is formed on top, it reacts with it.

【0014】 TS > 700℃:RuO2の分解が起きる。また, 柱状結晶を
形成する。
T S > 700 ° C .: RuO 2 decomposition occurs. In addition, columnar crystals are formed.

【0015】[0015]

【実施例】図1(A) 〜(D) は本発明の実施例を説明する
断面図である。図1(A) において,基板 1上に層間絶縁
膜として二酸化シリコン(SiO2)膜 2を形成し,下部電極
形成部のSiO2膜 2を開口し,ここに堆積とエッチバック
を用いてポリシリコン膜 3を埋め込む。
1 (A) to 1 (D) are sectional views for explaining an embodiment of the present invention. In FIG. 1 (A), the substrate 1 a silicon dioxide (SiO 2) as an interlayer insulating film on the film 2 is formed, opening in the SiO 2 film 2 of the lower electrode forming portions, here with a deposition and etchback poly Embed the silicon film 3.

【0016】次いで, ポリシリコン膜 3上に反応性スパ
ッタ法により, Ru層 4を基板温度400℃で,厚さ 300Å
成長し, 引き続いてRuO2層 5を基板温度 500℃で1500Å
成長した。その後,RuO2/Ru 膜をパターニングして下部
電極とする。
Then, the Ru layer 4 is formed on the polysilicon film 3 by the reactive sputtering method at a substrate temperature of 400 ° C. and a thickness of 300 Å.
Then, the RuO 2 layer 5 was grown to 1500 Å at a substrate temperature of 500 ° C.
grown. After that, the RuO 2 / Ru film is patterned to form the lower electrode.

【0017】ここで,Ru層 4はシリコン表面の酸化を防
ぐために形成され,RuO2層 5が電極として機能する。図
1(B) において,マグネトロンスパッタ法により, 下部
電極を覆って基板上に酸化物誘電体膜としてチタン酸ス
トロンチウム(SrTiO3)膜 6を成膜する。
Here, the Ru layer 4 is formed to prevent the oxidation of the silicon surface, and the RuO 2 layer 5 functions as an electrode. In FIG. 1 (B), a strontium titanate (SrTiO 3 ) film 6 is formed as an oxide dielectric film on the substrate by magnetron sputtering to cover the lower electrode.

【0018】図1(C) において,堆積と異方性エッチン
グを用いて,SrTiO3膜 6の側面に気相成長(CVD) 成長に
よるSiO2膜からなる側壁 7を形成する。図1(D) におい
て,SrTiO3膜 6上に上部電極として白金膜 8を成膜す
る。
In FIG. 1C, the side wall 7 made of a SiO 2 film by vapor phase growth (CVD) growth is formed on the side surface of the SrTiO 3 film 6 by using deposition and anisotropic etching. In FIG. 1 (D), a platinum film 8 is formed as an upper electrode on the SrTiO 3 film 6.

【0019】図2は本発明の効果を示す図(1) である。
図はオージェ電子分光による分析結果である。縦軸は原
子濃度AC (%) を示し, 横軸はRuO2/Ru の2層構造の表
面よりスパッタを行ったときの経過時間 (分)を示す。
用いた試料は前記の成長条件で作成したRuO2/Ru の2層
構造の電極を大気中 700℃でアニールしたものである。
FIG. 2 is a diagram (1) showing the effect of the present invention.
The figure shows the analysis results by Auger electron spectroscopy. The vertical axis represents the atomic concentration AC (%), and the horizontal axis represents the elapsed time (minutes) when sputtering was performed from the surface of the RuO 2 / Ru two-layer structure.
The sample used is the RuO 2 / Ru two-layer structure electrode prepared under the above-mentioned growth conditions, which is annealed at 700 ° C. in the atmosphere.

【0020】この結果より, 表面よりRuO2, Ru, Siが順
次形成されていることが示され, Si表面にはSiO2は形成
されていないことがわかる。従って酸素のバリア性が良
好であることを示している。
From these results, it is shown that RuO 2 , Ru and Si are sequentially formed on the surface, and that SiO 2 is not formed on the Si surface. Therefore, it shows that the oxygen barrier property is good.

【0021】次に,RuO2の成長温度 750℃で成長した結
晶粒径 500ÅのRuO2/Ru 膜とRuO2の成長温度 350℃で成
長した結晶粒径 100ÅのRuO2/Ru 膜のオージェ電子分光
の結果を図3に示す。
Next, Auger electrons RuO 2 / Ru film grain size 100Å grown in RuO 2 / Ru film and RuO 2 Growth temperature 350 ° C. the crystal grain size 500Å grown at a growth temperature 750 ° C. of RuO 2 The result of the spectroscopy is shown in FIG.

【0022】図3(A),(B) は本発明の効果を示す図(2)
である。結晶粒径 500Åの図3(A) では,酸化物電極Ru
O2膜の下部に形成されたバリア層の金属Ru膜を酸化して
いる。そのため,Ru膜の下のSiと反応してSiO2を形成し
てしまう。一方, 結晶粒径 100Åの図3(B) では,酸化
物電極RuO2膜の下部に形成されたバリア層の金属Ru膜は
酸化していないことがわかる。
FIGS. 3A and 3B are diagrams showing the effect of the present invention (2)
Is. In Fig. 3 (A) with a crystal grain size of 500Å, the oxide electrode Ru
The metal Ru film of the barrier layer formed under the O 2 film is oxidized. Therefore, it reacts with Si under the Ru film to form SiO 2 . On the other hand, in Fig. 3 (B) with a crystal grain size of 100Å, it can be seen that the metal Ru film of the barrier layer formed below the RuO 2 film of the oxide electrode is not oxidized.

【0023】酸化物導電性電極を成長する際,前記柱状
結晶の成長を抑えるため結晶成長可能なの最低温度,あ
るいは最高成長速度の一例は以下のようである。 導電性酸化物 最低成長温度 最高成長速度 (この時の成長温度) (℃) (Å/分) (℃) RuO2 350 1000 500 実施例では, 酸化物導電性電極としてRuO2膜を使用した
が,同類のReO2, IrO2, OsO2等についても, これらの結
晶に対して最低成長温度, あるいは最高成長速度で成長
することにより実施例と同等の効果を生じる。
An example of the minimum temperature or the maximum growth rate at which crystal growth is possible in order to suppress the growth of the columnar crystals when the oxide conductive electrode is grown is as follows. Conductive oxide minimum growth temperature Maximum growth rate (growth temperature at this time) (℃) (Å / min) (℃) RuO 2 350 1000 500 In the example, the RuO 2 film was used as the oxide conductive electrode. Also, with respect to ReO 2 , IrO 2 , OsO 2, etc. of the same kind, the same effect as that of the embodiment is obtained by growing these crystals at the minimum growth temperature or the maximum growth rate.

【0024】[0024]

【発明の効果】酸化物導電性電極,例えばRuO2/Ru の2
層構造の電極形成において,本発明によれば下地のシリ
コンを酸化させないため, 電極上に酸化物誘電体を形成
する際に生ずる酸素に対してバリア性を損なわない。従
って下地シリコンとのコンタクトが良くなった。且つ電
極のヒロックの発生を防止することができた。
EFFECTS OF THE INVENTION Oxide conductive electrodes such as RuO 2 / Ru 2
According to the present invention, in the formation of a layered electrode, the underlying silicon is not oxidized, so that the barrier property against oxygen generated when the oxide dielectric is formed on the electrode is not impaired. Therefore, the contact with the underlying silicon was improved. Moreover, it was possible to prevent the occurrence of hillocks on the electrodes.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例を説明する断面図FIG. 1 is a sectional view illustrating an embodiment of the present invention.

【図2】 本発明の効果を示す図(1)FIG. 2 is a diagram showing the effect of the present invention (1)

【図3】 本発明の効果を示す図(2)FIG. 3 is a diagram showing the effect of the present invention (2)

【符号の説明】[Explanation of symbols]

1 半導体基板でSi基板 2 SiO2膜 3 ポリシリコン膜 4 金属Ru膜 5 導電性酸化物膜でRuO2層 6 酸化物誘電体膜でSrTiO3膜 7 SiO2膜からなる側壁 8 上部電極でPt膜1 Si substrate as semiconductor substrate 2 SiO 2 film 3 Polysilicon film 4 Metal Ru film 5 RuO 2 layer as conductive oxide film 6 SrTiO 3 film as oxide dielectric film 7 Sidewall made of SiO 2 film 8 Pt as upper electrode film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/314 M 7352−4M 21/3205 21/8242 27/108 H01L 21/88 M 7210−4M 27/10 325 J ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H01L 21/314 M 7352-4M 21/3205 21/8242 27/108 H01L 21/88 M 7210-4M 27/10 325 J

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に酸化物誘電体膜を用いた
キャパシタの下部電極として酸化ルテニウム(RuO2)/ル
テニウム(Ru)の2層構造の電極を形成するに際し,第1
層目のRu膜の成長条件として, 膜厚dを 300Å<d< 5
00Åとし,基板温度TS を 300℃<TS < 450℃とし,
第2層目のRuO2膜の成長条件として,膜厚dを1000Å<
d<3000Åとし,基板温度TS を 350℃<TS < 700℃
とすることを特徴とする半導体装置の製造方法。
1. When forming an electrode having a two-layer structure of ruthenium oxide (RuO 2 ) / ruthenium (Ru) as a lower electrode of a capacitor using an oxide dielectric film on a semiconductor substrate,
The film thickness d is set to 300 Å <d <5 as the growth condition of the Ru film of the second layer.
And the substrate temperature T S is 300 ° C. <T S <450 ° C.
As the growth condition of the second layer of RuO 2 film, the film thickness d is 1000Å <
d <3000Å, substrate temperature T S is 350 ° C <T S <700 ° C
A method of manufacturing a semiconductor device, comprising:
【請求項2】 半導体基板上に酸化物誘電体膜を用いた
キャパシタの下部電極として導電性酸化物を, 結晶成長
が可能な最低温度または最高成長速度で成長することを
特徴とする半導体装置の製造方法。
2. A semiconductor device, wherein a conductive oxide is grown as a lower electrode of a capacitor using an oxide dielectric film on a semiconductor substrate at a minimum temperature or a maximum growth rate capable of crystal growth. Production method.
JP5236136A 1993-09-22 1993-09-22 Fabrication of semiconductor device Withdrawn JPH0794680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5236136A JPH0794680A (en) 1993-09-22 1993-09-22 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5236136A JPH0794680A (en) 1993-09-22 1993-09-22 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0794680A true JPH0794680A (en) 1995-04-07

Family

ID=16996297

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH0794680A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19633689A1 (en) * 1995-08-21 1997-02-27 Hyundai Electronics Ind Semiconductor device e.g. DRAM prodn.
JPH09116115A (en) * 1995-06-26 1997-05-02 Hyundai Electron Ind Co Ltd Manufacture of capacitor for semiconductor element
JPH09199687A (en) * 1995-11-30 1997-07-31 Hyundai Electron Ind Co Ltd Capacitor for semiconductor element and manufacture of the same
KR19980016024A (en) * 1996-08-26 1998-05-25 김주용 Method for forming capacitor of semiconductor device
US5852307A (en) * 1995-07-28 1998-12-22 Kabushiki Kaisha Toshiba Semiconductor device with capacitor
KR100228760B1 (en) * 1995-12-20 1999-11-01 김영환 Capacitor fabrication method of semiconductor device
US6046469A (en) * 1997-09-29 2000-04-04 Sharp Kabushiki Kaisha Semiconductor storage device having a capacitor and a MOS transistor
US6180974B1 (en) 1996-12-06 2001-01-30 Sharp Kabushiki Kaisha Semiconductor storage device having a capacitor electrode formed of at least a platinum-rhodium oxide
US6201271B1 (en) 1997-07-29 2001-03-13 Sharp Kabushiki Kaisha Semiconductor memory device prevented from deterioration due to activated hydrogen
KR100376263B1 (en) * 2000-10-09 2003-03-17 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
US6548404B2 (en) 2000-03-31 2003-04-15 Hitachi Kokusai Electric, Inc. Method and apparatus for manufacturing semiconductor devices
US6680251B2 (en) 2001-03-22 2004-01-20 Samsung Electronics Co., Ltd. Methods of chemical vapor depositing ruthenium by varying chemical vapor deposition parameters
KR100438781B1 (en) * 2001-12-05 2004-07-05 삼성전자주식회사 Metal - Insulator - Metal capacitor and Method for manufacturing the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09116115A (en) * 1995-06-26 1997-05-02 Hyundai Electron Ind Co Ltd Manufacture of capacitor for semiconductor element
US6156599A (en) * 1995-07-28 2000-12-05 Kabushiki Kaisha Toshiba Method of making a semiconductor device with capacitor
US5852307A (en) * 1995-07-28 1998-12-22 Kabushiki Kaisha Toshiba Semiconductor device with capacitor
KR100264429B1 (en) * 1995-07-28 2000-08-16 니시무로 타이죠 Semiconductor device
DE19633689A1 (en) * 1995-08-21 1997-02-27 Hyundai Electronics Ind Semiconductor device e.g. DRAM prodn.
DE19633689B4 (en) * 1995-08-21 2008-05-29 Hyundai Electronics Industries Co., Ltd., Ichon Method for producing capacitors for semiconductor devices
JPH09199687A (en) * 1995-11-30 1997-07-31 Hyundai Electron Ind Co Ltd Capacitor for semiconductor element and manufacture of the same
KR100228760B1 (en) * 1995-12-20 1999-11-01 김영환 Capacitor fabrication method of semiconductor device
KR19980016024A (en) * 1996-08-26 1998-05-25 김주용 Method for forming capacitor of semiconductor device
US6180974B1 (en) 1996-12-06 2001-01-30 Sharp Kabushiki Kaisha Semiconductor storage device having a capacitor electrode formed of at least a platinum-rhodium oxide
US6201271B1 (en) 1997-07-29 2001-03-13 Sharp Kabushiki Kaisha Semiconductor memory device prevented from deterioration due to activated hydrogen
US6046469A (en) * 1997-09-29 2000-04-04 Sharp Kabushiki Kaisha Semiconductor storage device having a capacitor and a MOS transistor
US6548404B2 (en) 2000-03-31 2003-04-15 Hitachi Kokusai Electric, Inc. Method and apparatus for manufacturing semiconductor devices
KR100376263B1 (en) * 2000-10-09 2003-03-17 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
US6680251B2 (en) 2001-03-22 2004-01-20 Samsung Electronics Co., Ltd. Methods of chemical vapor depositing ruthenium by varying chemical vapor deposition parameters
KR100438781B1 (en) * 2001-12-05 2004-07-05 삼성전자주식회사 Metal - Insulator - Metal capacitor and Method for manufacturing the same
US6946341B2 (en) 2001-12-05 2005-09-20 Samsung Electronics Co., Ltd. Methods for manufacturing storage nodes of stacked capacitors
DE10262115B4 (en) * 2001-12-05 2011-03-17 Samsung Electronics Co., Ltd., Suwon Integrated circuit device with a plurality of stacked capacitors, metal-insulator-metal capacitor and manufacturing method thereof

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