JPH0793369B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device, and in particular,
The present invention relates to a technique effective when applied to a semiconductor memory device that constitutes a memory cell using a MISFET.

[Background Art] Folded bit lin forming a memory cell using MISFET
The word lines of an e-type RAM (random access memory) or ROM (read only memory) are usually formed by using, for example, a polycrystalline silicon layer having excellent heat resistance. However, the polycrystalline silicon layer has a sheet resistance of 30 to 40 [Ω
/ □], which hinders the speeding up of the semiconductor memory device. On the other hand, an aluminum layer having a small sheet resistance of about 30 to 75 [mΩ / □] is difficult to withstand heat treatment, and thus it is difficult to use it as a gate electrode and a word line. Therefore, for example, a technique for dividing a word line made of a polycrystalline silicon layer into a plurality of lines and connecting each of the divided polycrystalline silicon layers with an aluminum layer to increase the speed of a semiconductor memory device is disclosed in, for example, Japanese Patent Application No. -135815.

The inventor of the present invention has found a problem in the above-described word line configuration method that, for example, when the integration degree of DRAM (dynamic RAM) becomes 1 megabit or more, the signal propagation speed decreases.

For a DRAM with a density of 1 megabit or less,
Since the resistance value of the aluminum layer for forming the word line is sufficiently smaller than the resistance value of the polycrystalline silicon layer,
Does not affect the signal propagation. Therefore, the resistance component of the polycrystalline silicon layer is the only resistance component that delays the propagating signal when each memory cell is driven. Therefore,
In order to make the signal propagation the same in each memory cell, the lengths of the polycrystalline silicon layers that are the word lines are the same.

However, as the degree of integration is improved, the aluminum layer is also miniaturized, so that its resistance value increases. For this reason,
The resistance value of the entire word line is the sum of the resistance value of the aluminum layer and the resistance value of the polycrystalline silicon layer. Therefore,
The resistance of the word line from the decoder to the memory cell at the far end is larger than the resistance of the word line to the memory cell at the near end. Since the operation speed of the semiconductor memory device is largely influenced by the delay of the operation of the memory cell at the far portion,
The operation speed of the semiconductor memory device decreases.

[Object of the Invention] An object of the present invention is to provide a technique capable of improving the operation speed of a semiconductor memory device.

Another object of the present invention is to provide a technique capable of improving electrical connection between a conductive layer used as a signal wiring and a semiconductor region.

Another object of the present invention is to provide a technique capable of preventing an increase in parasitic capacitance of a conductive layer used as a signal wiring.

Another object of the present invention is to provide a technique capable of improving the retention time of information written in a memory cell.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of first conductive layers arranged in a divided manner and a second conductive layer connected to each of the first conductive layers and having a sheet resistance smaller than that of the first conductive layer are formed. The first first conductive layer connected to one side is made shorter than the second first conductive layer connected to the other side. As a result, the delay time of the wiring to the far end of each of the first conductive layers can be made substantially the same, and in particular, the operating speed of the circuit at the far end of the second conductive layer can be improved. .

[Examples] Hereinafter, the configuration of the present invention will be described together with Examples.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

An embodiment in which the present invention is applied to a DRAM will be described.

FIG. 1 is a schematic diagram of a DRAM mainly showing word lines equivalently, FIG. 2 is an equivalent circuit diagram of a DRAM, and FIG. 3 is a diagram showing outline of propagation characteristics of electric signals propagating through word lines. is there.

In FIG. 1, reference numeral 1 is a DRAM chip (semiconductor substrate made of p ⁻ -type single crystal silicon), which is a circuit for selecting a word line WL in the peripheral portion, that is, an X decoder 2 and a data line DL. A circuit, that is, a Y decoder 3 and peripheral circuits 4 and 5 are provided. Peripheral circuits 4 and 5 are provided with peripheral circuits other than the decoder, such as an address buffer circuit, an input / output buffer, a main amplifier, and various clock generation circuits. The X-decoder 2, the Y-decoder 3, and the peripheral circuits 4 and 5 are an n-channel type MISFET and a p-channel type MISF.
It is configured using a complementary MISFET composed of ET and ET.

Reference numeral 6 is a conductive layer, which is used together with the conductive layer 7 to form a word line of the DRA. The conductive layer 6 is composed of a polycrystalline silicon layer (30 [Ω / □]) and a refractory metal silicide layer (4 [Ω / □]) thereon. The conductive layer 7 is made of an aluminum layer (30 to 75 [mΩ / □]).

As shown in FIG. 1, the conductive layer 6 has a memory cell array 26.
It is formed by being divided into a plurality of parts inside, and each conductive layer 6 is electrically connected to the conductive layer 7. One end of the conductive layer 7 is connected to the X decoder 2.

In this embodiment, the conductive layer 6 is divided into 12 parts. That is, the conductive layer 6 which is one divided unit is the conductive layer 7
From the connection with and to the end. The resistances of the respective divided conductive layers 6 from the connection point with the conductive layer 7 to the end thereof are shown as R _{601 to} R ₆₁₂ . Therefore,
R _{601 to} R ₆₁₂ represent the resistance of the conductive layer 6 up to the memory cell coupled to the far end of the divided conductive layer 6.

On the other hand, the resistance of the conductive layer 7 is distributed and shown by R _{71 to} R ₇₆ . R _{71 to} R ₇₆ represent the resistance between the connection point between the X decoder and the conductive layers 7 and 6, or the resistance between the connection point between the conductive layers 7 and 6.

The relationship between the word lines 6 and 7 and the memory cell is shown in FIG. As shown in FIG. 2, the memory cell M is composed of a switch MISFET Q and a capacitive element C.
The memory cell M is provided corresponding to each intersection of the conductive layer 6 and the conductive layer 8 used as a data line.

The conductive layer 8 is formed by using an aluminum layer. One end of the conductive layer 8 is connected to the Y decoder 3.

In FIG. 2, the memory cell M ₁ (M ₄ ) is a cell connected to the one of the divided conductive layers 6 closest to the X decoder 2 and from the connection point with the conductive layer 7. It is the cell at the end. The resistance of the word line from the X decoder 2 to the memory cell M ₁ is R ₇₁ + R ₆₀₁ . The memory cell M ₁ is located at the position where the resistance of the word line is the highest among the plurality of memory cells coupled to the conductive layer 6 closest to the X decoder 2.

The memory cell M ₃ (M ₆ ) is a cell that is connected to the farthest one of the divided conductive layers 6 from the X decoder 2 and is at the farthest end from the connection point with the conductive layer 7. It is a cell. The resistance of the word line from the X decoder 2 to the memory cell M ₃ is (R ₇₁ + R ₇₂ + ... + R ₇₆ ) + R ₆₁₂ . That is, the memory cell M ₃ is located at the position where the resistance of the word line becomes maximum. The memory cell M ₂ (M ₅ ) is at the position where the resistance of the word line is the smallest at R ₇₁ only.

In this way, for example, highly integrated over 1 megabit
In the DRAM, the resistance value of the conductive layer 7 also increases and is added as the resistance value of the word line. That is, when considering the resistance of the entire word line, the resistance of the conductive layer 7 becomes a value that cannot be ignored with respect to the resistance of the conductive layer 6. This becomes remarkable when the cell farthest from the X decoder 2 or the cell having the highest resistance of the word line from the X decoder 2 is selected.

In this embodiment, the conductive layer 6 provided closer to the X decoder 2 is formed longer and the conductive layer 6 provided further away is formed shorter. Thus, by forming the conductive layer 6 with different lengths, the resistance value of the conductive layer 6 can be reduced in the memory cell M far from the X decoder 2. The conductive layer 6 is shortened as the distance from the X decoder 2 increases. Therefore, the resistances R _{601 to} R ₆₁₂ become smaller as the distance from the X decoder 2 increases.

Therefore, the sum of the resistance values of the conductive layer 6 and the conductive layer 7 from the X decoder 2 to the distant memory cell M is calculated as the sum of the resistance values of the conductive layer 6 and the conductive layer 7 to the near memory cell M. Can be approximately equal to the sum. A resistor R ₇₁ + R ₆₀₁ to the memory cells M _1, the resistance to the memory cell _{M 3 (R 71 + R 72} + ... + R 76) + and R ₆₁₂ are substantially equal. In other words, the conductive layer 6 is divided so that the resistors R ₆₀₁ and R ₆₁₂ satisfy this condition. Also for the conductive layer 6 having the resistances R _{602 to} R ₆₁₁ , the conductive layer 6
The cell having the largest resistance of the word line (the cell at the farthest end from the connection point of the conductive layer 7 and the conductive layer 6) among the cells connected to is determined in length. That is, the resistance of the word line to these cells is made substantially equal to or smaller than the resistance of the word line to the memory cell M ₃ .

The outline of the delay of the electric signal propagating through the word line is as shown in the graph of FIG. In FIG. 3, the horizontal axis is the delay time of the electric signal, and the vertical axis is the MISFETQ of the memory cell.
Shows the potential of the gate electrode of.

Now, assume that the input signal IN is applied as a selection signal (high-level signal) to the word line selected at time t ₀ . At this time, as shown in FIG. 3, the delay characteristic A of the gate electrode of the memory cell M _{1 in} the vicinity of the X decoder 2 and the memory cell in the far portion
The delay characteristics B of the gate electrodes of M ₃ are substantially equal. However, X
When the lengths of the conductive layer 6 at the near portion and the far portion of the decoder 2 are made equal, a large difference is produced between the delay characteristic C of the memory cell M _{1 at} the near portion and the delay characteristic D of the memory cell M _{3 at} the far portion. Occurs.

However, in the present embodiment, in particular, the delay time up to the memory cell (for example, M ₃ ) at the distant portion can be shortened, so that the operation speed of writing and reading information in the DRAM can be improved.

A word line composed of a plurality of first conductive layers 6 arranged in a divided manner and a second conductive layer 7 connected to each of the first conductive layers 6 is connected to one of the conductive layers 7 By reducing the length of the conductive layer 6 connected to the other side of the conductive layer 6, the resistance values of the word lines from the X decoder 2 to the respective memory cells M can be made substantially equal. Further, this makes it possible to make the delay of the electric signal by the word line substantially equal in the far part and the near part.

In the present embodiment, the length of the conductive layer 6 is sequentially reduced from the near side to the far side of the X decoder 2, but the present invention is not limited to this.

It is important to select the length of the conductive layer 6 so that the delay time of the electric signal to the near memory cell M ₁ and the delay time of the electric signal to the far memory cell M ₃ are substantially equal. is there. Further, the length of the conductive layer 6 is determined so that the delay time to the other memory cells is substantially equal to or smaller than the delay time of the cell (M ₃ ) having the largest resistance of the word line from the X decoder 2. There is a need to.

For example, the conductive layer 6 (the conductive layer having the resistance components R _{601 to} R ₆₀₆ ) on the X decoder 2 side with respect to the intermediate portion between the X decoder 2 and the peripheral circuit 5 is made uniform in length, and the others are sequentially shortened. May be. The length of the conductive layer 6 depends on the mat structure of the memory cell,
Various changes are made depending on the arrangement of the X decoder 2 and the Y decoder 3.

In addition, the stray capacitance of the conductive layers 6 and 7 greatly affects the delay time. The stray capacitance per unit area of the conductive layer 6 is large, and that of the conductive layer 7 is small. In consideration of this point, the length of the conductive layer 6 is determined so as to satisfy the above delay time condition.

Next, a specific structure of the DRAM shown in FIGS. 2 and 3 will be described with reference to FIGS. 4 to 9.

FIG. 4 is a plan view of a portion surrounded by a chain double-dashed line IV in FIG.
FIG. 5 is a sectional view taken along the line VV of FIG. 4, and FIG.
FIG. 7 is a sectional view taken along the line VI-VI of FIG. 4, FIG. 7 is a plan view of a portion surrounded by a two-dot chain line VII of FIG.
The drawing is a plan view of a portion surrounded by a chain double-dashed line IX in FIG.

Note that, in all the plan views, the insulating film provided between the conductive layers is not shown in order to make the configuration of the DRAM easy to see.

As shown in FIGS. 4 to 6, the MISFETQ shown in FIG. 2 has a conductive layer 6 serving as a gate electrode, a gate insulating film 9, an n-type semiconductor region 10 serving as a source region or a drain region.
And 11 and. As described above, the conductive layer 6
Is a conductive layer 6A made of a polycrystalline silicon layer and Mo, W, T
Conductive layer 6B made of a refractory metal silicide layer such as i and Ta
However, the present invention is not limited to this. For example, only the conductive layer 6A or the conductive layer 6B may be directly formed on the insulating film 9. Further, the conductive layer 6B may be formed of a refractory metal layer. The shape of the conductive layer 6 which is a word line is easy to understand with reference to FIG. n ^- type semiconductor region
Reference numeral 10 is formed by introducing n-type impurities such as phosphorus by ion implantation using the gate electrode 6 as a mask. The insulating film 9 is a silicon oxide film formed by thermally oxidizing the surface of the semiconductor substrate 1. The n ⁺ type semiconductor region 11 is a side insulating film 12 made of SiO ₂ provided on the side of the conductive layer 6.
It is formed by ion-implanting an n-type impurity such as arsenic using the (side wall) and the gate electrode 6 as a mask.

The capacitive element C shown in FIG. 2 has an electrode (conductive plate) 1
3. An insulating film 14 used as a dielectric and an n ⁺ type semiconductor region 15 provided on the surface of the semiconductor substrate 1 below the insulating film 14. The insulating film 14 is a silicon oxide film formed by thermally oxidizing the surface of the semiconductor substrate 1. In addition,
The insulating film 14 can also be configured by forming a silicon oxide film by thermal oxidation, a silicon nitride film formed thereon by, for example, a CVD technique, and further oxidizing the silicon nitride film to form a silicon oxide film. . The semiconductor region 15 is formed by introducing an n-type impurity such as arsenic into the surface of the semiconductor substrate 1 by ion implantation. The conductive plate 13 is formed by using a polycrystalline silicon layer, and, for example, phosphorus is introduced to reduce the resistance value. The conductive plate 13 has a potential 1 that is half the power supply potential Vcc.
A fixed potential such as / 2Vcc (2.5 [V]) or a reference potential Vss (0 [V]) of the semiconductor memory device is applied. When connecting the conductive plate 13 to the power supply potential Vcc (5 [V]), the semiconductor region 15 is not necessarily provided. The conductive plate 13 is an electrode common to a plurality of memory cells in one memory cell array, and as shown in FIG. 4, is selectively removed in the region where the MISFETQ is provided.

Reference numeral 16 is a field insulating film, which electrically isolates the semiconductor elements together with the p ⁺ type channel stopper region 17 thereunder. The field insulating film 16 defines the shape of the semiconductor regions 10, 11, and 15.

Reference numeral 18 denotes an insulating film, which is made of a silicon oxide film formed by thermally oxidizing the conductive plate 13. The insulating film 19 is made of, for example, a silicon oxide film formed by CVD and a phosphosilicate glass (PSG) film, and has a film thickness of about 5000 Å (hereinafter, referred to as [A]).

The conductive layer 8 serving as the data line shown in FIG. 2 is provided so as to extend on the insulating film 19 and is connected to a predetermined semiconductor region 11 through a connection hole 20. The conductive layer 8 is made of, for example, aluminum formed by sputtering. The connection hole 20 is formed by removing the insulating film 19 by, for example, dry etching. After forming the connection hole 20, the n-type impurity is introduced again through the connection hole 20 to deepen the junction depth of the semiconductor region 11, as shown in FIG.

The insulating film 21 is made of, for example, a PSG film obtained by CVD and a silicon oxide film obtained by plasma CVD, and has a film thickness of about 8000 [A]. This insulating film 21
A conductive layer 7 to be the word line shown in FIG.

The conductive layer 7 to be the word line shown in FIG. 2 is formed so as to extend over the insulating film 21. The conductive layer 7 is made of, for example, an aluminum layer formed by sputtering. The conductive layer 7 is
For the conductive layer 6, a region 25 (25
Connected in A). For the shape of the conductive layer 7, refer to FIG.

Reference numeral 22 is a conductive layer, which electrically connects the conductive layer 6 and the conductive layer 7 through the connection hole 23 and the connection hole 24. Conductive layer 22
In the present embodiment, is formed in the same manufacturing process as the conductive layer 8 and is made of an aluminum layer.

In the DRAM of this embodiment, the conductive plate 13 is the first conductive layer in the manufacturing process, the conductive layers 6, that is, the conductive layers 6A and 6B are the second layers, and the conductive layer 8 is the third layer. The conductive layer 7 is the fourth conductive layer.

Since the third conductive layer 8 is used as the data line and the fourth conductive layer 7 is used to form the word line, the conductive layer 8 used as the data line and the semiconductor region to be the source region and the drain region are formed. The connection hole 20 for connecting with 15 can be formed to have a shallow depth. As a result, it is possible to prevent the adherence of the conductive layer 8 at the stepped portion of the connection hole 20 from deteriorating, so that the electrical connection between the conductive layer 8 and the semiconductor region 15 can be improved. Further, since it is possible to prevent an increase in parasitic capacitance associated with the word line, it is possible to prevent an increase in delay of the electric signal propagating through the word line.

As shown in FIG. 4 or FIG. 6, the conductive layer 7 is provided so as to be offset from the conductive layer 6 above the memory cell array. This is for the following reason. The insulating film 19 and the insulating film 21 on the conductive layer 6 become higher than the insulating films 19 and 21 provided between the conductive layers 6. On the other hand, the conductive layer 7
In the step of forming, the aluminum layer is provided on the entire surface of the insulating film 21 by sputtering. At this time, the aluminum layer tends to be thickly formed in a portion lower than the raised portion of the insulating film 21. Therefore, if the conductive layer 7 is formed right above the conductive layer 6, an unnecessary aluminum layer will remain between the conductive layers 7 during patterning. When the conductive layer 7 is formed by using the thick portion of the aluminum layer, the thin aluminum layer between the conductive layers 7 is completely removed.

On the other hand, at the connecting portion between the conductive layers 6 and 7, the conductive layer 7 is
Formed on. This is for the following reason. Insulating film 19
Tends to be thinly formed on the conductive layers 6 and thick between the conductive layers 6, and similarly, the insulating film 21 is thinly formed on the conductive layers 6 and thick between the conductive layers 6. Tend. Therefore, if the connection hole 24 is provided so as to be offset from directly above the conductive layer 6, the insulating film 21 remains at the bottom of the connection hole 24. In order to prevent the insulating film 21 from remaining inside the connection hole 24, the conductive layer 7 is provided on the conductive layer 6. Further, since the conductive layer 22 is provided so that the connection hole 24 is located above the conductive layer 6, the connection hole 24 is formed to be displaced from the conductive layer 22 due to the mask misalignment in the direction in which the conductive layer 7 extends. Can be prevented.

In this embodiment, the conductive layer 7 can be reliably connected to the conductive layer 6 by interposing the conductive layer 22 as described above.

As shown in FIG. 4, the connection portion between the conductive layer 6 and the conductive layer 7 is provided so as to be displaced from the extension line of the adjacent conductive layer 6 and conductive layer 7. Furthermore, the connecting portions are not aligned but are displaced. This is for the following reason.

Although not shown, in order to prevent the conductive layer 7 from being incompletely connected to the conductive layer 22 due to mask misalignment,
The portion of the connection hole 24 is formed thicker than the other portions of the conductive layer 7. Therefore, when the connecting portions of the conductive layers 6 and 7 are arranged on a straight line which is orthogonal to the conductive layers 7 and extends in the direction in which the conductive layers 8 extend, the connecting portions between the conductive layers 7 are located between the conductive layers 7. Becomes narrower. In the step of forming the conductive layers 7, it is necessary to make the intervals between the conductive layers 7 as uniform as possible in order to make the etching conditions similar. from these things,
In order to make the intervals of the conductive layers 7 uniform, as shown in FIG. 4, the connection portions are arranged in four places on a straight line and are repeated. The connecting portions may be arranged at five points or more on the straight line.

The division of the conductive layer 6 shown in FIG. 1 is performed on the semiconductor region 15 as shown in FIG.

Reference numeral 25 shown in FIG. 1, FIG. 4 to FIG. 6 and FIG. 8 denotes a semiconductor region, which is generated inside the semiconductor substrate 1 by operating peripheral circuits such as an alpha ray or X decoder 2 and Y decoder 3. It is formed in order to capture the minority carriers that generate. This semiconductor region 25 is the semiconductor region 15
It is formed in the same manufacturing process as. Further, the conductive plate 13 is provided above the semiconductor region 25, and
The insulating film 14 is interposed between the semiconductor region 25 and the semiconductor region 25. The semiconductor region 25 is arranged on the entire chip in the layout shown in FIG. 1, and includes a semiconductor region 25A provided between the memory cell arrays 26 and a semiconductor region 25B provided on the outer periphery of the memory cell array 26. Although not shown, the semiconductor region 25 includes, for example, the insulating film 14, the conductive plate 13, the insulating film 18, and the insulating film at the corners of the memory cell array 26.
It is connected to the power supply potential Vcc through an opening formed by removing 15.

As shown in FIGS. 1, 4, and 8, one of the features of this embodiment is that the semiconductor region 25A is provided below the connecting portion between the conductive layer 6 and the conductive layer 7. In this embodiment, the conductive layer 22 is provided between the conductive layer (polycide word line) 6 and the conductive layer (aluminum word line) 7 for the reason described above. Since the conductive layer 22 is formed in the same manufacturing process as the conductive layer (data line DL) 8, the memory cell cannot be formed below the connecting portion between the conductive layer 6 and the conductive layer 7. Therefore, in the present embodiment, as described above, the semiconductor region 25 for trapping minority carriers is provided below the connecting portion between the conductive layer 6 and the conductive layer 7.
A is provided. Semiconductor region 25A and memory cell M
It is important that the width of the field insulating film 16 located between the memory cells M and M is substantially uniform and equal to the width of the field insulating film 16 between the memory cells M. This is to equalize the influence of minority carriers in all memory cell arrays 26.
Since the semiconductor region 25A is provided below the connecting portion between the conductive layer 6 and the conductive layer 7, the distance between the semiconductor regions 25A is also X.
The shorter the distance from the decoder 2, the shorter the length.

The field insulating film 16 may be formed below the connection portion instead of the semiconductor region 25A.

When the field insulating film 16 is provided, the minority carriers generated inside the semiconductor substrate 1 below the field insulating film 16 are absorbed by the semiconductor regions 11 and 15 forming the peripheral memory cells. here,
If the amount of minority carriers generated under the field insulating film 16 is the same as the amount of minority carriers generated under the field insulating film 16 provided between the memory cells M, there is no problem. However, since the field insulating film 16 to be provided below the connection portion has a larger area than the field insulating film 16 provided between the memory cells M, the generation amount of minority carriers also increases. For this reason,
When the field insulating film 16 is formed below the connection portion, the information holding time of the memory cells M around the field insulating film 16 becomes shorter than the information holding time of other memory cells M. In this case, the information read from the memory cell array 26 becomes inaccurate and the reliability of the DRAM is significantly reduced. Therefore, when forming the field insulating film 16 instead of the semiconductor region 25A, it is important to consider the above points.

A semiconductor region 25A for trapping minority carriers is provided below the connecting portion between the conductive layer 6 and the conductive layer 7 so that the influence of minority carriers generated by alpha rays or the like is equalized in the entire memory cell array 26. Therefore, it is possible to equalize the retention time of information in each memory cell M. As a result, the reliability of the information read from the DRAM can be improved.

The semiconductor region 25 may not be provided when the conductive plate 13 is connected to the Vcc potential power source. In this case, a depletion layer or an inversion layer that captures minority carriers is formed on the surface of the semiconductor substrate 1 below the conductive plate 13. Further, since the semiconductor region 25 is provided, the minority carriers can be captured without providing the conductive plate 13 on the semiconductor region 25. Furthermore, the semiconductor region 25A is not always necessary because the semiconductor region 25B alone can sufficiently capture the minority carriers generated mainly from the MISFETs forming the peripheral circuits 2 to 5.

Although the capacitive element C of this embodiment is composed of the semiconductor region 15, the insulating film 14 and the conductive plate 13, the semiconductor region 15
It is also possible to form pores extending in the depth direction from the surface portion of the semiconductor substrate 1 in which the capacitor is provided, and to use the pores to configure the capacitive element C. The pores are formed by subjecting the semiconductor substrate 1 to 3 to 5 [μ
It may be formed by etching to a depth of about [m]. On the inner walls of the pores, an insulating film used as a dielectric is formed similarly to the insulating film 14. Further, a conductive member similar to the conductive plate 13 is provided so as to be embedded inside the pores.
This conductive member is electrically connected to the conductive plate 13 which is to be provided above the pores.

[Effect] According to the novel technique disclosed by the present application, the following effects can be obtained.

(1). A first divided and arranged on a semiconductor substrate
And a second conductive layer connected to each of the first conductive layers.
Of the conductive layer of the second conductive layer, the length of the first conductive layer connected to one of the second conductive layers is made shorter than that of the second conductive layer connected to the other of the second conductive layers, so that The resistance values of the word lines up to the memory cells can be made substantially equal.

(2). According to the above (1), the delay of the electric signal by the word line can be made substantially equal to the memory cell provided far from the decoder and the memory cell provided near.

(3). According to the above (2), the delay time of the memory cell located far from the decoder is shortened, so that the speed of writing and reading of information in the semiconductor memory device can be increased.

(4). Since the word line is formed by using the first conductive layer and the fourth conductive layer in the manufacturing process, and the data line is formed by using the third conductive layer in the manufacturing process, A connection hole for connecting the conductive layer used as a line and the source region or the drain region can be formed with a shallow depth.

(5). By the above (4), it is possible to prevent the adherence of the conductive layer at the stepped portion of the connection hole from being deteriorated, so that the electrical connection between the data line and the source region or the drain region can be improved.

(6). By the above (5), the electrical reliability of the semiconductor memory device can be improved.

(7). By forming the word line using the fourth conductive layer in the manufacturing process, it is possible to prevent an increase in parasitic capacitance associated with the word line, and thus increase the delay of the electric signal propagating through the word line. Can be prevented.

(8). In the first conductive layer that is divided into a plurality of parts and the second conductive layer that is connected to each of the first conductive layers and extends above the first conductive layer, 1
Since the workability of the second conductive layer can be improved by arranging the conductive layer so as to be offset from directly above the conductive layer, it is possible to prevent a short circuit between the second conductive layers.

(9). By providing the third conductive layer for connecting the first conductive layer and the second conductive layer directly above the first conductive layer,
Since it is possible to prevent an unnecessary insulating film from remaining at the bottom of the connection hole for connecting the second conductive layer and the third conductive layer, the connection between the second conductive layer and the third conductive layer can be well performed. Then, the connection between the second conductive layer and the first conductive layer can be surely performed.

(Ten). According to the above (9), the connection hole provided between the second conductive layer and the third conductive layer is formed deviating from the third conductive layer due to mask misalignment in the extending direction of the second conductive layer. Can be prevented.

(11). From the above (8) to (10), the electrical reliability of the semiconductor memory device can be improved.

(12). By connecting the first conductive layer and the second conductive layer via the third conductive layer, it is possible to prevent the connection hole required for connecting the first conductive layer and the second conductive layer from becoming deep. Therefore, the second conductive layer can be reliably connected to the first conductive layer.

(13). The second conductive layer extends from a connection portion between the first conductive layer and the second conductive layer, on a straight line that passes through the connection portion between the adjacent first conductive layer and the second conductive layer and is orthogonal to the second conductive layer. By arranging the first conductive layer and the second conductive layer so as to shift in the direction, the wiring interval between the first conductive layer and the second conductive layer can be made substantially uniform. Therefore, processing conditions such as etching for forming the first conductive layer or the second conductive layer can be made uniform throughout the first conductive layer or the second conductive layer.

(14). Due to the above (13), it is possible to prevent an unnecessary conductive layer (polycrystalline silicon layer or aluminum layer) from remaining between the first conductive layer or the second conductive layer. Also the first
It is possible to prevent the connecting portion between the conductive layer and the second conductive layer from being formed thinner than a predetermined line width.

(15). Since the minority carrier trapping region is provided below the connecting portion between the first conductive layer and the second conductive layer, the influence of minority carriers generated by alpha rays or the like can be made equal in the entire memory cell array. The retention time of the information in the memory cells M can be equalized.

(16). By the above (15), the reliability of the information read from the semiconductor memory device can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the division of word lines can be performed as shown in FIG. When divided in this manner, a region for connecting the conductive layers 6 and 7 can be small, which is effective for reducing the chip area in the word line direction.

Further, the number of divisions of the word line 6 is not limited to 12.

A plurality of decoders 2 may be provided, and the arrangement within the chip 1 is not particularly limited. The decoder 3 is also the same. The memory cell array may be divided into 2, 4 or 8 depending on the arrangement of the decoders in the chip 1. Even in this case, the present invention can be applied in a large memory cell array divided by the arrangement of the decoders. That is,
In one large memory cell array, word line 6
Are divided into a plurality of lines and connected to the decoder 2 by the word line 7. A semiconductor region is formed below the connecting portion between the conductive layers 6 and 7.
It is desirable to provide 25A. As a result, the large memory cell array is divided into a plurality of small memory cell arrays.

INDUSTRIAL APPLICABILITY The present invention is effective when applied to semiconductor memory devices such as mask ROMs, EPROMs, and static random access memories as well as DRAMs.

At least the present invention can be applied to a semiconductor memory device or a semiconductor integrated circuit device provided with a conductive layer connected to a semiconductor element arranged on a semiconductor substrate and used as a signal wiring.

Further, in the above-described embodiment, in order to capture minority carriers, the semiconductor region provided in the connection portion between the first conductive layer that is divided and arranged and the second conductive layer that connects the first conductive layer to the decoder is used. Although used, this semiconductor region can also be used to stabilize the potential of the semiconductor substrate. For example, by applying a negative potential to the semiconductor substrate using the semiconductor region, the depletion layer between the source and drain regions of the MISFET and the semiconductor substrate can be deeply extended into the semiconductor substrate. As a result, the parasitic capacitance of the source region and the drain region is reduced, so that the parasitic capacitance of the data line connected to the drain region or the source region is reduced, and the speed of the semiconductor memory device can be increased.

[Brief description of drawings]

1 is a schematic plan view of a DRAM mainly showing word lines equivalently, FIG. 2 is an equivalent circuit diagram of the DRAM, FIG. 3 is a propagation characteristic view of an electric signal propagating through a word line, and FIG. The figure is a plan view of the main part IV surrounded by the chain double-dashed line in FIG. 1, FIG. 5 is a cross-sectional view taken along the line VV in FIG. 4, and FIG. 6 is VI-VI in FIG. FIG. 7 is a plan view of a main part VII surrounded by a two-dot chain line in FIG. 1, FIG. 8 is a plan view of a main part X surrounded by a two-dot chain line in FIG. 1, FIG. 9 is a plan view showing another embodiment of the present invention. 1 ... Semiconductor substrate, 2 ... X decoder, 3 ... Y decoder, 4, 5 ... Peripheral circuit, 6, 6A, 6B, 7, 8, 22 ...
Conductive layer, 9, 12, 14, 18, 19, 21 ... Insulating film, 10, 11,
15, 17, 25, 25A, 25B ... Semiconductor region, 13 ... Conductive plate, 16 ... Field insulating film, 20, 23, 24 ... Connection hole, 26 ... Memory cell array, M ... Memory cell, Q …
… MISFET, C… Capacitive element.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-206164 (JP, A) JP-A-60-28261 (JP, A)

Claims (5)

[Claims] 1. A first direction and a second direction intersecting the first direction.
A plurality of memory cell arrays in which a plurality of memory cells are arranged in one direction toward the first direction from one side of the decoder circuit, and a word line extending in the first direction has one end side in the decoder circuit. Electrically connected, and the other end side is electrically connected to each of the plurality of memory cells arranged in the first direction of each of the plurality of memory cell arrays,
In the semiconductor memory device, the data line extending in the second direction is electrically connected to each of the plurality of memory cells arranged in the second direction of each of the plurality of memory cell arrays. In each of the memory cell arrays, a plurality of first word lines, which are divided for each memory cell array and extend in the first direction, are provided with respect to the first word line arranged in a position closest to the decoder circuit. The first word line arranged at the farthest position from the decoder circuit is configured to be short, and the first word line is separated from the first word line through an insulating film above the plurality of divided first word lines. A second word line having a low resistance and continuously extending in the first direction, and the second word line is formed by the conductive layer penetrating the insulating film.
A semiconductor memory device in which a word line and each of the plurality of first word lines are electrically connected individually. 2. The plurality of divided first word lines are:
Each of the plurality of memory cell arrays is arranged at a predetermined interval in the second direction, and in each of the plurality of memory cell arrays, the first word line and the first word line adjacent to the first word line in the second direction are connected to each other. The semiconductor memory device according to claim 1, wherein a second word line is arranged. 3. A connection between each of the plurality of divided first word lines and the second word line is made between each of the plurality of arranged memory cell arrays, and the first word line and the first word line are connected to each other. The connection position with the second word line is deviated from the connection position in the first direction with respect to the connection position between another first word line and another second word line adjacent in the second direction. The semiconductor memory device according to claim 2. 4. The conductive layer, which connects each of the plurality of divided first word lines to the second word line,
4. The semiconductor memory according to claim 1, wherein the semiconductor memory is formed in the same process as a data line formed between a first word line and the second word line. apparatus. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a DRAM.