JPH0793245A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate necessity for exchanging an already mounted software in the case of exchange from an interface board only corresponding to 16 bits to an interface board corresponding to 32 bits. CONSTITUTION:The software mounted at a main body can be used for both 32 bits and 16 bits and an interface board 58 which data bus width can be used for both 16 bits and 32 bits is mounted, a CPU 34 transmits a bus width set signal to a bus width register 60, this bus width register 60 transmits a set signal to a memory sequencer 62 and a data buffer 65, and the data bus width can be set corresponding to both 16 bits and 32 bits. When the software mounted at the processor can be used for both 32 bits and 16 bits and the interface board 58 with the data bus width for 16 bits is mounted, processing is executed corresponding to the software for 16 bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which an option board such as a communication interface is set and data is transferred via a bus by the option board and the DMA transfer function.

[0002]

2. Description of the Related Art In recent years, an image such as a large amount of documents is read by a scanner (two-dimensional scanning device), the read image is stored in an optical disk, and any stored image is searched and read out. Output it to an output device, eg C
An information processing device such as an image filing device that outputs an image in a state that can be visually recognized by an RT display device or a recording device has been put into practical use.

Such an information processing apparatus has an expansion slot and can be equipped with option boards such as a communication interface, a scanner interface, and a printer interface. Data is exchanged between the option board and the memory of the main body of the information processing apparatus via a bus. A DMA controller is used to transfer this data.

The data bus width at the time of the DMA transfer is currently 16 bits, but in the future, a higher version of 32 bits wide will be used. Therefore, when the option board was changed to a 32-bit width in anticipation of the future, the software (control program) on the main body side had to be changed (version up). However, not only the software for the option board was changed, but the software for other functions had to be changed at the same time.

Therefore, while the software on the main body side remains 16 bits, the option board has a 16 bit width and 32 bits.
What can be used for both bit width can be set, and when the software on the main unit side is changed to 32 bit width in the future,
There is a demand for an option board that can be used as it is. Further, even if the software on the main body side is for 32 bits, there is a demand for the one that can use the 16-bit width option board.

[0006]

As described above, the software on the main body side remains 16-bit, and the option board that can be used for both 16-bit width and 32-bit width can be set. When the software is for 16-bit, the option board is used as 16-bit width, and when the software on the main unit side is changed to 32-bit width in the future, it can be used as it is by making the option board correspond to 32-bit. Further, there is a demand for a 16-bit width option board that can be used even if the main body software is for 32-bit software.

Therefore, according to the present invention, the software on the main body side can be set to 16 bits and the option board which can be used for both the 16-bit width and the 32-bit width can be set. Information that the option board can be used as it is when it is changed to a 32-bit width, and even if the software on the main body side is for a 32-bit width, a 16-bit width option board can be used. An object is to provide a processing device.

[0008]

An information processing apparatus according to the present invention is an information processing apparatus in which an option board is set, and data is transferred between the option board and the bus via the bus. According to the determination means for determining whether the board is for 16-bit width or 16 / 32-bit width and the determination result of this determination means, 16
Execution means for executing processing according to software for bit width or for 32-bit width, transmission means for transmitting designated data of bus width to the option board according to the judgment result of the judgment means, and the option The board is directly connected to the above bus and is for 16-bit width or 16/32
Identification means indicating whether the bit width is also used, receiving means for receiving the bus width designation data from the information processing apparatus main body, and data transfer with the bus width according to the bus width designation data received by the receiving means. And a transfer means.

Further, the information processing apparatus of the present invention is an information processing apparatus comprising an option board and an information processing apparatus main body in which the option board is set and data is transmitted and received via a bus using a DMA control means. First output means for outputting a status signal corresponding to a DMA response signal supplied in response to a DMA request signal for the DMA control means of the information processing apparatus main body, and bus width designation data supplied from the information processing apparatus main body A second output means for outputting a 16-bit width or 32-bit width bus width setting signal, a bus width setting signal from the second output means, and a status signal from the first output means. Accordingly, the third output means for outputting the memory control signal, the storage means for storing the data in units of 32 bits, and the storage means The stored 32-bit unit data is output as the 32-bit unit data as it is according to the memory control signal from the third output means, or is converted into 16-bit unit data and output. In accordance with the processing means and the memory control signal from the third output means, the 32-bit unit data supplied from the information processing apparatus main body is stored in the storage means as it is,
Alternatively, it is provided with a second processing means for converting 16-bit unit data supplied from the information processing apparatus main body into 32-bit unit data and storing it in the storage means.

[0010]

The data bus width of the option board can support either 16-bit or 32-bit word length. When this option board is installed, if the already installed software supports 16-bit, Since the initial state is 16-bit compatible, use it as it is. If the already installed software is also used for 32 bits / 16 bits, use the option board with 32 bits.
By setting either bit or 16 bit, it is possible to easily replace the option board supporting only 16 bits with the option board supporting 32 bits without exchanging software.

Further, since the software is also used for 32 bits / 16 bits, when an option board compatible only with 16 bits is mounted, the processing is executed by the software for 16 bits to transfer the 16 bits data. Can be done.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows the configuration of an image filing apparatus as an information processing apparatus according to an embodiment of the present invention.
16 with only 6-bit software installed
Some have software for both bits and 32 bits.

This image filing apparatus includes a control module 10, a memory module 12, an image processing module 14, a communication control module 16, a scanner device 18, an optical disk 20, an optical disk device 22, and a keyboard 2.
3, CRT display device 24, printer device 25,
It is composed of a magnetic disk 26, a magnetic disk device 27, a mouse 29, and a system bus 30.

The control module 10 uses the CPU 34 for controlling the overall operation and data flow such as image storage, retrieval and edit processing, and the optical disk device 22, magnetic disk device 27, keyboard 23 and mouse 29 as the main device. An interface unit 36 for connection, and a DM for transferring data between the main memory 38 and the communication interface board 58 regardless of the operation of the CPU 34.
It is composed of AC32.

The memory module 12 is a main memory 38 for storing various control programs for image storage, retrieval, editing, etc., and management information, and an image memory having a storage capacity corresponding to images of several pages of A4 size document. Page memory 40, a display memory 42 as a display interface, and a display controller 44. A buffer memory area 40a is provided in a part of the page memory 40. The page memory 40 is a memory that temporarily stores, for example, an image stored in the optical disc 20 or an image read from the optical disc 20.

The display memory 42 is for temporarily storing an image displayed by the CRT display device 24. In the display memory 42, an image actually displayed in the display window of the CRT display device 24, for example, an image from the page memory 40 or an image from the buffer memory 40a is enlarged, reduced, rotated, inserted or inserted. An image subjected to black-and-white reversal or the like is stored. The display control unit 44 controls the display processing of the CRT display device 24 and the like.

The image processing module 14 includes an enlarging / reducing circuit 46 for enlarging and reducing an image, a vertical / horizontal converting circuit 48 for rotating an image, and an encoding process for compressing an image (reducing redundancy). A compression / decompression circuit (CODEC) 50 for performing a decoding process for applying and decompressing (reducing the reduced redundancy), a scanner interface 52 for the scanner device 18, a printer interface 54 for the printer device 25, and The internal bus 56 connects the enlarging / reducing circuit 46 and the vertical / horizontal converting circuit 48, the compression / expansion circuit 50, the scanner interface 52, and the printer interface 54.

The compression / decompression circuit 50 is a MH (Modified Huff).
Band compression or band expansion is performed using a man (man) method, an MR (Modified Read) method, or the like. The communication control module 16 starts from a communication interface board 58, which is an option board for adjusting electrical, mechanical and logical boundary conditions between devices in order to connect an external device such as a LAN or a personal computer to the device. Composed. The communication interface board 58 and the external device are connected by a cable or a communication line.

The system bus 30 is a bus for control signals and data of various devices, and connects the control module 10 with the memory module 12, the image processing module 14, and the communication control module 16.

The scanner device 18 is, for example, a two-dimensional scanning device, which obtains an electric signal corresponding to an image on the original by scanning the original (document) two-dimensionally with a laser beam.

The optical disk device 22 is a scanner device 18.
The images read by the method are sequentially stored in the optical disc 20. The optical disc 20 is searched for an image corresponding to the search title designated by the keyboard 23 or the like. The optical disc 20 may be a write-once type or a rewritable type.

The keyboard 23 is used to input a unique search title corresponding to an image stored on the optical disk 20 and various operation commands for storage, search, edit processing and the like. Further, the mouse 29 moves the cursor (not shown) displayed on the display window of the CRT display device 24, for example, vertically and horizontally to give an instruction at a desired position so that the cursor is positioned. The display contents (various operation modes, area designation or icon for image editing, etc.) are selected or designated.

The CRT display device (cathode ray tube display device) 24 displays an image read by the scanner device 18 and an image retrieved from the optical disk 20. Icons and the like are displayed at the upper end, the lower end, and the right end on the display window of the CRT display device 24.

The printer device 25 prints out (hard copy) the image read by the scanner device 18, the image retrieved from the optical disk 20, or the image displayed on the CRT display device 24.

The magnetic disk device 27 stores various control programs on the magnetic disk 26 mounted on the magnetic disk device 27, and also stores a search title input from the keyboard 23 and an image corresponding to the search title. The search data (search information) including the storage address on the optical disk 20 and the image size is stored.

The search data is managed by a document management table, and the document management table includes a title management table 26a, as shown in FIG.
Page management table 26b and record management table 2
6c.

The title management table 26a stores one document number corresponding to each search title (image name) consisting of a plurality of search keys. In the page management table 26b, record numbers are stored page by page of one document, and one record number is stored corresponding to each page. In the record management table 26c, the optical disc 1 of the image is recorded for each record number.
The storage address (storage start position) in 9, the document size (image size), and the image attributes such as the compression method and resolution are stored.

The above-mentioned storage address is a logical address, and the physical track address and physical sector address are calculated from this at the time of access.
FIG. 1 schematically shows an interface section for connecting the present apparatus and an external apparatus such as a personal computer in the communication interface board 58 of the above-mentioned image filing apparatus. The same parts as those in FIG. 2 will be described with the same reference numerals.

In the figure, the bus width register 60 is a CP
System bus 30 by the bus width setting signal from U34
The number of data lines (data bus 67) (hereinafter, referred to as the data bus width) connected to each other to transmit / receive data is 16
A setting signal for setting either bit correspondence or 32-bit correspondence is generated, and this setting signal is transmitted to the memory sequencer 62 and the data buffer 65.

When a DMA transfer instruction signal requesting data transmission from the local memory 64 to the page memory 40 by DMA transfer is sent from the CPU 34 via the system bus 30 to the DMA controller 61, the DMA controller 61 makes a DMA transfer to the DMAC 32. Generate a DMAREQ signal to request
This is transmitted to the DMAC 32. Upon receiving the DMAREQ signal, the DMAC 32 confirms that the CPU 34 has relinquished the right to use the system bus, and transmits a DMAACK signal to the DMA control unit 61 to approve the DMA transfer. Then, the local memory 6 for reading or writing
4 and the status signal indicating the status associated with each operation of the DMA control unit 61.
Send to.

The memory sequencer 62 includes a DMA controller 6
From the status signal from No. 1 and the setting signal from the bus width register 60, a memory control signal for controlling writing or reading of data corresponding to the data bus width and timing, address, etc. of the data is generated, and the local memory 64 Send to. In the initial state, a memory control signal for controlling writing or reading of data, timings thereof, etc., corresponding to a 16-bit data bus width, is generated and transmitted to the local memory 64.

Local memory 64, local CPU 6
8, the external interface 63, the ID register 69, and the data buffer 65 are connected by a local bus 70.

The external interface unit 63 adjusts the data input from an external device (not shown) via a communication line such as a cable so that this device can process the adjusted data, and transmits the adjusted data via the local bus 70. Send to local memory 64. The transmission data sent from the local memory 64 to the external device via the local bus 70 is adjusted so as to be transmitted to the external device, and is sent to the external device (not shown) via a communication line or the like.

The local memory 64 temporarily stores the adjusted data sent from the external interface unit 63, reads the data into the data buffer 65 in accordance with the memory control signal from the memory sequencer 62, and
The data from the data buffer 65 is written according to the memory control signal from the memory sequencer 62.

The data buffer 65 is the bus width register 6
According to the setting signal from 0, the data bus width of the data bus 67 is set to be 16-bit compatible or 32-bit compatible so that the data sent from the local memory 64 is transmitted via the data bus 67 at a constant timing. To the system bus 30, and also receives data sent via the system bus 30 and the data bus 67, and sends it to the local memory 64 via the local bus 70 at a fixed timing. In the initial state, data is transmitted / received with a data bus width corresponding to 16 bits.

The local CPU 68 controls the interface board 58 as a whole. The ID register 69 is
A recognition number (hereinafter referred to as a board ID) indicating whether the communication interface board has a data bus width of 16 bits or a 16/32 bits combination is used as a DIP switch or jumper. It is set by hardware such as the above, and if there is a board ID transmission request from the CPU 34 via the system bus 30, this board ID is transmitted to the CPU 34 via the system bus 30.

Next, a method of DMA transfer between the communication interface board and the main unit with the above-mentioned configuration will be described with reference to the flow charts shown in FIGS. 4, 5 and 6.

When software having a word length of data of 32 bits / 16 bits is installed in this apparatus, description will be made with reference to the flowchart shown in FIG. First, when the device is activated, the process proceeds to step S0,
The CPU 34 reads the board ID set in the ID register 69, and proceeds to step S1. Step S1
Then, it was checked whether it was a communication interface board capable of setting the data bus width to either 16 bits or 32 bits, and it was confirmed that it was a communication interface board capable of setting the data bus width to either. In this case, the process proceeds to step S2. When it is confirmed in step S1 that the communication interface board corresponding to the data bus width of only 16 bits is mounted, the process proceeds to step S16, and the software installed in the device is switched to 16 bits. , Step S9
Then, the process proceeds to and the DMA transfer is performed.

In step S2, 32-bit DMA transfer is performed with the communication interface board, or 16
Select whether to perform DMA transfer by bit. In other words, if the software installed in this device is performing 32-bit processing, D-bit
If MA transfer is selected and the process proceeds to step S3, or if the software installed in this apparatus is executing 16-bit processing, 16-bit DMA is performed.
Transfer is selected, and the process proceeds to step S6.

In step S3, the CPU 34 sends a bus width setting signal for setting the data bus width to correspond to 32 bits to the bus width register 60, and proceeds to step S4. In step S4, when the bus width register 60 receives the bus width setting signal, the bus width register 60 generates a setting signal for setting the data bus width to correspond to 32 bits, sends the setting signal to the memory sequencer 62 and the data buffer 65, and proceeds to step S5.

In step S5, a 32-bit DM
In order to perform the A transfer, the memory sequencer 62 and the data buffer 65 are set when the data bus width corresponds to 32 bits. That is, the memory sequencer 62
Prepare to generate a memory control signal that controls data writing and reading corresponding to a 2-bit data bus width, and the data buffer 65 transmits and receives data with a 32-bit data bus width. Prepare to do so, and go to step S9.

When the 16-bit DMA transfer is selected, first, in step S6, the CPU 34 sends a bus width setting signal for setting the data bus width to 16 bits to the bus width register 60, and proceeds to step S7.

In step S7, the bus width register 60
Receives the bus width setting signal, generates a setting signal for setting the data bus width corresponding to 16 bits and sends the setting signal to the memory sequencer 62 and the data buffer 65.
Proceed to.

In step S8, DM corresponding to 16 bits is used.
In order to perform A transfer, the memory sequencer 62 and the data buffer 65 are set when the data bus width corresponds to 16 bits. That is, the memory sequencer 62
Prepare to generate a memory control signal for controlling writing or reading of data, which corresponds to the data bus width corresponding to 6 bits.
Preparations are made for transmitting and receiving data with a data bus width corresponding to bits, and the process proceeds to step S9. The above step S1
S8 are processed by the software initialization routine.

In step S9, DMA transfer processing is performed. The DMA transfer process will be described with reference to the flowchart shown in FIG.

In the DMA transfer process, first, step S10
Then, the CPU 34 sends the DMA transfer instruction signal to the DMA control unit 61 to request the data transfer from the local memory 64 to the page memory 40 by the DMA transfer, and the process proceeds to step S11.

In step S11, the DMA control unit 61 that has received the DMA transfer instruction signal sends the DMAREQ signal to D
It is sent to the MAC 32, and the process proceeds to step S12. Step S
In 12, the DMAC 32, which has received the DMAREQ signal, confirms that the CPU 34 has abandoned the use of the system bus, and DMs the DMAACK signal to approve the DMA transfer.
It transmits to the A control part 61, and progresses to step S13.

In step S13, when the DMA controller 61 receives the DMAACK signal, the memory sequencer 62
To the step S14. In step S14, the memory sequencer 62 generates a memory control signal, transmits it to the local memory 64, and proceeds to step S15.

In step S15, the memory sequencer 6
2 according to the memory control signal from the local memory 64
The data is read from and the data is transferred to the main memory 38.

Next, when the software corresponding to the word length of data of 16 bits is installed in this device, since the word length of the data that can be processed by this device is 16 bits, the data bus width corresponds to 16 bits. All you have to do is do it.
That is, since the initial states of the data buffer 65 and the memory sequencer 62 correspond to the case where the data bus width is 16 bits, this communication interface board functions as a board corresponding to the data bus width of 16 bits. Therefore, the processing by the software initialization routine of steps S0 to S8 as shown in the flowchart of FIG. 6 is not performed, and the 16-bit DMA is executed in step S17.
The transfer is performed according to steps S10 to S15.

As described above, according to the above embodiment, the software installed in the main body is 32 bits /
In the case of 16-bit dual use, when the interface board 58 capable of supporting either the 16-bit or 32-bit word length of the data bus is mounted, the CPU 34 transmits a bus width setting signal to the bus width register 60, and this The bus width register 60 transmits a setting signal to the memory sequencer 62 and the data buffer 65 so that the data bus width becomes 16
It can be set to support bits or support 32 bits.

Further, when the software installed in the main body is 16-bit compatible, if the interface board 58 capable of supporting both the data bus width of 16 bits and the word length of 32 bits is installed, the data bus width Since the initial state corresponds to 16 bits, it can be used as it is. Therefore, it is not necessary to replace the software when the interface board supporting only 16 bits is replaced with the interface board supporting 32 bits.

Further, when the software installed in the main body is also used for 32 bits / 16 bits, if the interface board corresponding to the data bus width of only 16 bits is installed, the software is switched to 16 bits. , 16-bit data bus can be executed.

Although the board ID is set by hardware in the above embodiment, the board ID can be set by software from the local CPU 68.
In the DMA transfer processing in the above embodiment, the DMA transfer instruction signal sent from the CPU 34 to the DMA control unit 61 is
Although requesting the transmission of data from the local memory 64 to the page memory 40, a DMA transfer instruction signal for instructing the transmission of data from the page memory 40 to the local memory 64 is also sent. In this case, step S1
The processes of 1 to 14 are similar, and data transfer is performed from the page memory 40 to the local memory 64 in step S15.

[0055]

As described above in detail, according to the present invention, 1
When replacing an option board that supports only 6 bits with an option board that supports 32 bits, it is not necessary to replace the software installed in the main body. Further, when the software installed in the main body is exchanged for 32 bits, it is possible to provide an information processing apparatus capable of 16-bit DMA transfer as needed.

[Brief description of drawings]

FIG. 1 is a configuration diagram schematically showing an interface unit with an external device of an image filing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of an image filing device according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining a storage example of a document management table.

FIG. 4 is a flowchart illustrating a DMA transfer method of an interface unit.

FIG. 5 is a flowchart illustrating a DMA transfer method of an interface unit.

FIG. 6 is a flowchart illustrating a DMA transfer method of an interface unit.

[Explanation of symbols]

30 ... System bus, 32 ... DMAC, 34 ... CPU,
40 ... Page memory, 58 ... Communication interface board, 60 ... Bus width register, 61 ... DMA control unit, 62
… Memory sequencer, 63… External interface, 64
... local memory, 65 ... data buffer, 67 ... data bus, 68 ... local CPU, 69 ... ID register,
70 ... Local bus

Claims (2)

[Claims] 1. An information processing apparatus in which an option board is set and data is exchanged with the option board via a bus, wherein the information processing apparatus main body uses the option board for 16-bit width or 16 / 32-bit width dual use. Depending on the determination result of this determination means, execution means for executing processing according to the software for 16-bit width or for 32-bit width, and the determination result of the above-mentioned determination means. , The transmission means for transmitting the specified data of the bus width to the option board, and the option board are directly connected to the bus, for 16-bit width or 16/3
Identification means indicating whether it is also used for 2-bit width, receiving means for receiving the bus width designation data from the information processing apparatus main body, and data transfer with a bus width according to the bus width designation data received by the receiving means. An information processing device, comprising: 2. An information processing apparatus comprising an option board and an information processing apparatus main body in which the option board is set and exchanges data via a bus by using a DMA control means. DMA for control means
First output means for outputting a status signal in response to a DMA response signal supplied in response to a request signal, and a bus having a 16-bit width or a 32-bit width depending on bus width designation data supplied from the main body of the information processing apparatus. Second output means for outputting the width setting signal, and third memory means for outputting the memory control signal in response to the bus width setting signal from the second output means and the status signal from the first output means. Output means, storage means for storing data in 32-bit units, and data in 32-bit units stored in the storage means in accordance with a memory control signal from the third output means.
Output as 2-bit unit data, or 1
According to the memory control signal from the first processing means for changing the data into 6-bit unit data and outputting the data, the 32-bit unit data supplied from the information processing apparatus body is directly processed as described above. Second processing means for storing in the storage means or converting 16-bit unit data supplied from the information processing apparatus main body into 32-bit unit data and storing in the storage means. A featured option board.