JPH0787563B2 - Electronic imager - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic image pickup device, and more particularly, to improvement of power supply voltage dependency of continuous shooting intervals in a continuous shooting device of a camera.

[Prior Art] Conventionally, in a continuous shooting device for a camera, continuous shooting is performed by using a motor that operates on a power supply battery built in the camera as a drive source, so that the continuous shooting interval is set as the power supply voltage of the continuous shooting device decreases. Become longer. For example, in a motor drive camera, when the power supply voltage of the motor drive device drops, the time for film winding increases, and in the case of an electronic camera, the recording head finishes one recording and then the next recording track. The time for head access to the head becomes longer as the power supply voltage for head access decreases.

[Problems to be Solved by the Invention] Therefore, in the conventional continuous shooting apparatus, as shown in FIG. 5, when the power supply voltage E is high, the shooting interval T is short and a large number of frames are shot within a fixed time. However, if the power supply voltage E decreases with time, the shooting interval T
Will gradually become longer, and the number of frames that can be shot within a certain period of time will decrease. That is, since the shooting interval T changes during continuous shooting, it is not possible to shoot at accurate timing when it is necessary to observe the movement of the subject at regular intervals.

For this reason, when the power supply voltage drops below a predetermined value, while maintaining the uniformity of the shooting time intervals in continuous shooting operation (continuous shooting), the time can be extended and the frames that can be recorded within a unit time can be recorded. It is conceivable to limit the continuous shooting speed so that the number is reduced, or to prohibit the continuous shooting operation itself. However, if the above-mentioned restrictions or prohibitions relating to continuous shooting are automatically applied as the power supply voltage decreases, continuous shooting at a relatively low speed is not always required under conditions where uniform shooting time intervals are not required. Even if you want to do so, if the power supply voltage drops, you will not be able to perform such continuous shooting evenly, which is inconvenient and the operability in practical use will be impaired. .

The present invention has been made in view of such a problem. Even if the power supply voltage is lowered, the photographing interval is fixed to a constant value in a voltage region having the same power supply voltage. Even if the voltage is lower than a predetermined value, the electronic image pickup apparatus of this type is designed to allow continuous shooting recording at a relatively low speed without maintaining the uniformity of shooting time intervals. The purpose is to provide.

[Means and Actions for Solving Problems] The electronic image pickup apparatus of the present invention handles rotation of an applied disc-shaped information recording medium while a command signal for instructing continuous shooting operation is input. In the electronic image pickup device in which the head repeatedly and successively records the recorded image information on the information recording medium at the timing synchronized with the rotation detection pulse generated by the Voltage identifying means for identifying which one of the voltage areas it corresponds to and issuing an identification signal, and the power supply voltage corresponding to the relatively high voltage area of the plurality of voltage areas by this voltage identifying means. When the identification signal indicating that the recording time is issued, it is noted that the recording operation is repeated every time at the timing regulated by the predetermined time measured by the time measuring means. When the operation control is performed and the voltage identifying means issues an identification signal indicating that the power supply voltage corresponds to a relatively low voltage area among the plurality of voltage areas, a predetermined time counting by the time counting means is performed. A recording timing control unit configured to control the recording operation so that the recording operation is repeated every time the rotation detection pulse arrives immediately after the head access operation is completed, without depending on time. , Is provided.

[Examples] Hereinafter, the present invention will be described with reference to illustrated examples.

FIG. 2 is a block diagram showing an image pickup recording section of an electronic still camera which is an electronic image pickup apparatus to which the present invention is applied. An optical image of a subject incident from the image pickup lens 1 is formed on the photoelectric conversion surface of the solid-state image pickup element 2 installed on the focal plane of the lens 1. The solid-state image sensor 2 converts the image formation light of the subject into an electric signal and sends the output Vout to the color separation circuit 3. The color separation circuit 3 converts the sent electrical signal into a luminance signal Y and a color difference signal R.
Separated into -Y and BY, and supplied to the FM modulator 4. The FM modulator 4 FM-modulates the luminance signal Y and the color difference signals RY and BY in their respective frequency bands, and supplies them to the recording amplifier 5.
The recording amplifier 5 amplifies each FM-modulated signal and gives it to the magnetic head 6. The magnetic head 6 FM-records the supplied signal on the recording track of the magnetic disk 7.

The synchronizing pulse generator 8 supplies the image pickup device 2 with a vertical transfer clock φV, a horizontal transfer clock φH, and a charge read pulse SG.
And a sample and hold pulse to the color separation circuit 3. The sync pulse generator 8 applies a horizontal sync pulse Hsy and a vertical sync pulse Vsy to the FM modulator 4 and further synchronizes the vertical sync pulse Vsy with the sync detector 9 in order to match the operation timing and phase of the imaging system and the recording system. As one input to.

The sync detector 9 compares the PG pulse from the rotary phase detecting pulse generator 10 attached to the magnetic disk 7 provided as the other input with the vertical sync pulse Vsy from the sync pulse generator 8 to compare A signal is supplied to the motor drive circuit 11 so that the rotation speed and the phase always match the operation timing of the image pickup system. The motor drive circuit 11 drives and controls the disk drive motor 12 based on the signal given from the synchronization detector 9. As a result, the magnetic disk 7 rotates at a constant speed of 3600 RPM in the steady state,
Image recording of one field is performed during rotation.

The recording timing circuit 13 uses the release signal S ₀ generated when the recording specifying switch 14 linked with the release button of the electronic still camera is turned on, and thus the vertical synchronizing pulse is generated.
Vsy is guided. The vertical synchronizing pulse Vsy is also supplied to a power source voltage check circuit 16 for checking the voltage E of the power source battery 15, and the power source voltage check is made based on the vertical synchronizing pulse Vsy. Circuit 1
By supplying the timing signal C from 6 to the recording timing circuit 13, the recording signal of a predetermined recording timing is obtained.
REC is applied to the recording amplifier 5, and the recording amplifier 5 is activated only while the recording signal REC is at "H" level.
The timing of this recording is always synchronized with the PG pulse guided from the pulse generator 10. When recording is performed, the head access circuit 17 operates at the end of the recording signal REC to access the magnetic head to the next recording track. This head access is detected by the head access detection circuit 18, and the detection signal H _E is guided to the recording timing circuit 13.

In FIG. 2, reference numeral 19 denotes an encoder, which converts the luminance signal Y and the color difference signals RY and BY output from the color separation circuit 3 into, for example, NTSC signals and sends them to the viewfinder 20. . Thus, the viewfinder 20 can monitor the content of the image pickup.

Next, the recording timing circuit 13 and the power supply voltage check circuit 16 will be described in more detail. The recording timing circuit 13 and the power supply voltage check circuit 16 are configured, for example, as shown in FIG. That is, in FIG. 1, the recording timing circuit 13 inverts and outputs the vertical synchronizing pulse Vsy when the recording command switch 14 is on.
And the output of this NOR gate 31, head access detection circuit
18 (second reference drawing) of the output H _E, output C and D-type flip-flop of the NAND gate 56 to be described later timing signal generating circuit 16c (hereinafter referred to as D-FF) also 34 output level of any "H 4-input AND gate 32 which outputs an "H" level output at the time of ", and an RS flip-flop (hereinafter referred to as RS-FF) set by the output of the AND gate 32.
33) and the D-FF 34 which operates by the output of the RS-FF 33.

The power supply voltage check circuit 16 is composed of a voltage identification circuit 16a and a timing signal generation circuit 16c having a timer circuit 16b. The voltage identification circuit 16a determines the voltage E of the power battery 15.
And a reference voltage circuit 35 for producing a reference voltage V _REF, and two and comparators 36 and 37 the reference voltage V _REF is applied to an inverting input terminal, the divided voltage V power supply voltage E divide
Three resistors 38, 39, 40 connected in series for applying _A and V _B to the non-inverting input terminals of the comparators 36 and 37, respectively.
And a light-emitting diode 41, 42 connected to the output terminals of the comparators 36, 37, respectively, and a power supply voltage decrease warning circuit 43 having a warning light-emitting diode 44 connected to the output terminal of the comparator 36. . Light emitting diode 4
1,42,44 are provided in the viewfinder window of the electronic still camera.

The timing signal generation circuit 16c forms a timer circuit 16b so that clock pulses V _sy1 , V _sy2 , V _sy3 , and V _sy4 that are sequentially divided based on the vertical synchronization pulse Vsy can be obtained.
T-type flip-flops (hereinafter referred to as T-FF) 46-
49, an AND gate 51 that passes the output pulse V _sy3 of the T-FF 48 when the output B of the comparator 37 is at "H" level, an inverter 53 that closes the AND gate 52 at this time, and an Other than the comparator 37
AND gate 52 for passing the output pulse V _sy4 of the T-FF 49 when the output B of the AND gate is at the “L” level, and the AND gate 5
An OR gate 54 that allows one of the outputs of 1, 52 and the output of this OR gate 54 to be reset, and the vertical synchronizing pulse Vsy is applied to the CK input terminal,
The recording signal REC which is the output of the D-FF 34 is applied to the J input terminal to operate the JK type flip-flop (hereinafter referred to as JK-FF) 55 and the output A of the comparator 36 is "H". When it is at a level, it is composed of a NAND gate 56 for sending to the 4-input AND gate 32 of the recording timing circuit 13 as a timing signal C obtained by inverting the signal level at the Q output end of the JK-FF 55. The timing signal generating circuit 16c forms a timing regulating means together with the recording timing circuit 13.

Next, the operation of the circuit shown in FIG. 1 will be described. First,
In the voltage identification circuit 16a, the voltage of the power battery 15 (hereinafter,
When the power supply voltage E is sufficiently high, the voltages V _A and V _B and the reference voltage V _REF have a relationship of V _A > V _B > V _REF , and the comparator 3
The output A of 6,37, B is two light emitting diodes 41 and 42 become both "H" level is lit, and as shown in Figure 4, the voltage E _A down the power supply voltage E When it becomes below V _A ＞ V
_In the relation of _REF > V _B , the output A of the comparator 36 is “H”
Level, the output B of the comparator 37 becomes "L" level,
Only the light emitting diode 41 lights up. In addition, the power supply voltage E
Becomes less than the voltage E _B , V _REF > V _A > V _B , so
At this time, the outputs A and B of the comparators 36 and 37 are both at the "L" level (see FIG. 4). When the outputs A and B are both at "L" level, the light emitting diodes 41 and 42 do not light up, but at this time, the power supply voltage decrease warning circuit 43 operates and the light emitting diode 44
Lights up to warn that the power supply voltage E has dropped abnormally.

As described above, in the voltage identification circuit 16a, the level of the power supply voltage E is identified into three areas by the levels of the outputs A and B of the comparators 36 and 37. After that, the output of the voltage identification circuit 16a is guided to the timing signal generation circuit 16c, and by the operation of the timing signal generation circuit 16c and the recording timing circuit 13, the relationship between the power supply voltage E and the photographing interval T is shown in FIG. It is controlled as shown in. That is, as shown in FIG. 4, when the power supply voltage E is higher than the voltage E _{A and} the outputs A and B of the comparators 36 and 37 are both at the “H” level, the shooting interval T is fixed to the shortest interval T _A. , The power supply voltage E becomes lower than the voltage E _A and becomes higher than the voltage E _B.
When the output A of 36 is "H" level and the output B of the comparator 37 is "L" level, the shooting interval T is fixed to the interval T _B which is slightly longer than the interval T _A. Then, the power supply voltage E is the voltage E _B
When the outputs A and B of the comparators 36 and 37 both become "L" level, the shooting interval T becomes longer as the power supply voltage E decreases. As described above, the power supply voltage decrease warning circuit 43 gives a warning for this lowest power supply voltage region.

Here, the power supply voltage E is sufficiently high, and the comparator 3
The circuit operation when the outputs A and B of 6,37 are both at the H level will be described with reference to the time chart of the signals of the respective parts shown in FIG.

A PG pulse is generated by the pulse generator 10 (see FIG. 2) each time the magnetic disk 7 is rotated, and the second PG pulse is generated so as to have a predetermined phase delay with this PG pulse.
In the figure, the vertical synchronization pulse Vsy is phase-locked by the synchronization pulse generator 8, the synchronization detector 9, the motor drive circuit 11, and the like.

Even if the vertical synchronizing pulse Vsy is input to the timer circuit 16b, the "H" level recording signal REC is not applied to the J input terminal of the JK-FF55. Therefore, the Q output terminal is "L"
Since the level and the output terminal are at the "H" level, the T-FFs 46 to 49 of the timer circuit 16b have the "H" level applied to the reset terminal R, and all the Q output terminals are at the "L" level. ing. Therefore, at this time, the timing signal generation circuit 16c
An "H" level timing signal C is introduced from the NAND gate 56 of the NAND gate 56 to the 4-input AND gate 32 of the recording timing circuit 13.

Here, from a state in which the voltage E is applied to one input end of the NOR gate 31 by the resistor 57, the recording command switch 14 linked with the release button is turned on and the release signal S ₀ of “L” level is also input. When applied to the edge, the NOR gate
31 sends a signal S ₁ obtained by inverting the vertical synchronizing pulse Vsy to the AND gate 32. Incidentally, the AND gates 32, In addition, the output H _E of the head access detection circuit 18 (see FIG. 2)
And since D-FF 34 at the output end of the signal ▲ ▼ is applied, the output signals S ₁ of the AND gate 31, the other the signal of the C, H _E and ▲ ▼ become both "H" level RS-FF through AND gate 32
It is sent to the S input terminal of 33. That is, the release operation is now performed and the signal S ₁ is sent from the NOR gate 31.
The output H _E is "H" level of the head access detection circuit 18, not in the head access. Recording signal REC is “L”
Level (The signal RESET is applied to the reset end R of the D-FF34 by the power-on reset circuit (not shown) when the power switch (not shown) is turned on, and the signal at the output end
▼ is “H” level) and recording operation is not in progress. The timing signal C is at "H" level and is not during the time counting operation period (during the prohibition period) by the timer circuit 16b. 4 conditions are satisfied, and at this time, the output S _{1 of the} NOR gate 31 is guided to the RS-FF 33 as the output S ₂ of the AND gate 32 and is set. Then, the signal S ₃ at the Q output end of RS-FF33 becomes H
It goes to the D input terminal of the D-FF34, and after that, when the D-FF34 coincides with the rising edge of the PG pulse applied to the CK input terminal and the recording signal REC at the Q output terminal goes to the H level. , RS-FF 33 is a signal S ₃ is reset to the "L" level. At the same time, the recording signal REC becomes "H" level, the signal ▲ ▼ since become inverted and the "L" level, the AND gate 32 is the signal S ₂ prohibits passage of the signals S ₁ that follow
To “L” level.

When the recording signal REC becomes "H" level, the recording signal REC of the same "H" level is sent to the recording amplifier 5 (see FIG. 2) to activate the recording amplifier 5 to perform the first recording of continuous shooting. When started, it is applied to the J input terminal of JK-FF55.
After the J input terminal of JK-FF55 becomes "H" level, JK-FF
At the first falling edge of the vertical sync pulse Vsy applied to the CK input terminal of 55, the Q output terminal of JK-FF55 becomes "H" level,
Output terminal goes to "L" level. When the Q output terminal becomes "H" level, the timing signal C which is the output of the NAND gate 56 becomes "L" level. When the output terminal falls to "L" level,
At this time point t ₀ , each of the T-FFs 46 to 49 of the timer circuit 16b is released from the reset state and starts counting and dividing the vertical synchronizing pulse Vsy. Incidentally, the recording signal REC at the Q output end of the D-FF 34 becomes "L" level at the next rising edge of the PG pulse, and the recording of one field on the magnetic disk 7 (see FIG. 2) is completed.

While the recording signal REC is at "H" level, the signal ▲ ▼ is at "L"
Since it is at the level, the output signal of the AND gate 32 S ₂ during recording
Needless to say, is at "L" level. When the recording is completed and the trailing edge of the recording signal REC is detected by the head access circuit 17 (see FIG. 2), the head access circuit
The head 17 accesses the magnetic head 6 to the next track. Head access detection circuit determines whether or not the head is being accessed
Detected in 18, signal H _E is “L” during head access
It becomes a level. Note that the signal H _E also, the signal H _E
Is at "L" level, the timing signal C is "H".
Even if it is at the level, the signal S ₂ is kept at the “L” level. When the head access is completed outputs H _E of the head access detection circuit 18 becomes "H" level.

Further, the timer circuit 16b is the reset-released from the time t ₀ (from time t ₀ to the timing signal C becomes "L" level) by performing counting, the output V _sy3 the T-FF 48 is "H" level in time t ₁ it becomes, i.e., at time t ₁ that from the time count start by counting the falling pulse of the 4 th vertical sync pulses Vsy, the aND gate 51, a reset pulse is applied to the JK-FF 55 through oR gate 54 Therefore, at this time t ₁ , the JK-FF 55 has the Q output terminal at the “L” level and the output terminal at the “H” level. When the output terminal of this JK-FF55 becomes "H" level, the timer circuit 16b is reset and the above-mentioned T-F
The output V _sy3 of F48 becomes “L” level. Therefore, this output V
_sy3 results in very short duration pulses. When the Q output terminal of the JK-FF 55 becomes "L" level, the timing signal C of the output of the NAND gate 56 becomes "H" level again. The time period in which the timing signal C is at the “L” level corresponds to the period for prohibiting shooting.
When the timing signal C becomes "H" level, this time, other signals H _E to AND gate 32, ▲ ▼ also already "H"
Since it is at the level, the AND gate 32 will be the NOR gate as long as the recording command switch 14 is ON.
The output S ₁ of 31 is passed and the first “H” level is sent to RS-FF33 as output S ₂ . Thereafter, as described above, after which the signal S ₃ by a signal S ₂ becomes "H" level, the second recording of the record signal REC is "H" level to become continuous shooting at the rise of the PG pulse is initiated It

While the recording command switch 14 is on, the above operation is repeated. Then, the outputs A, B of the comparators 36, 37
When both are "H" level, the timing signal C is "L"
The vertical sync pulse Vs
y is a period in which four pulses are generated, and the recording interval, that is, the shooting interval T at which the recording signal REC becomes the “H” level
In this case, imaging is performed at 5 pulse intervals of the PG pulse, that is, once every 5 rotations of the magnetic disk 7.

Next, the case where the power supply voltage E is slightly lowered to E _A >E> E _B , the output A of the comparator 36 becomes “H” level, and the output B of the comparator 37 becomes “L” level will be described. In this case, after the first recording is started, as described above, the timer circuit 16b is reset and released by the JK-FF55 to start counting, and at the same time, the timing signal C becomes "L" level. After that, the "L" level of the timing signal C is maintained until the output V _sy4 of the T-FF49 of the timer circuit 16b becomes the "H" level. That, JK-FF55 "H" level of the output V _SY4 counting start time T-FF 49 at the time t ₂ which counts 8th falling pulse of the vertical synchronizing pulses Vsy than t ₀ the AND gate 52 through the OR gate 54
Because it is applied as a reset pulse, the timing signal C at this time t ₂ becomes "H" level. After that, the same operation as described above is performed, and the second recording of continuous shooting is started. Therefore, in this case, the vertical synchronizing pulse Vs is supplied during the prohibition period during which the timing signal C becomes the “L” level.
The y corresponds to a period in which eight pulses are generated, and the photographing interval is such that the photographing is performed once every nine rotations of the magnetic disk 7.

Further, when the power supply voltage E further decreases and becomes lower than the voltage E _B , and the outputs A and B of the comparators 36 and 37 both become the “L” level, the timing signal is always output regardless of the output of the timer circuit 16. since C becomes "H" level, except during recording or head access, as long as the pressing operation of the release button is being performed, the output S ₁ is the aND gate 32 of the NOR gate 31
PG immediately after the first recording is completed and the head access operation to the next track is completed.
The second recording is started at the rising edge of the pulse. In this case, the power supply battery 15 is extremely exhausted, and although the shooting is performed in synchronization with the PG pulse, the operation may become unstable. This condition is detected and a warning is issued to replace the power battery 15 with a new one.

Although the above-described embodiment is applied to an electronic still camera, it can also be applied to a motor drive camera that continuously shoots a camera using a silver salt film by driving a normal motor.

[Effect of the Invention] As described above, according to the present invention, even if the power supply voltage decreases, the shooting interval during continuous shooting depends on the power supply voltage value when the same voltage value is within a specific voltage range. It is fixed to a fixed value without any interruption, and even when the power supply voltage is below a predetermined value, continuous shooting recording at a relatively low speed is allowed without necessarily maintaining the uniformity of shooting time intervals. Because
It is possible to realize this kind of electronic image pickup device having good operability in practical use.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a main part of the electronic still camera shown in FIG. 2, FIG. 2 is a block diagram of an electric circuit showing a photographing / recording part of an electronic still camera to which the present invention is applied, and FIG. , A time chart of signals in each part of the electric circuit shown in FIG. 1, FIG. 4 is a diagram showing an example of the relationship between the change of the power supply voltage and the photographing interval in the device of the present invention, and FIG. FIG. 6 is a diagram showing the relationship between changes in power supply voltage and shooting intervals. 13 …… Record timing circuit (timing regulation means) 16 …… Power supply voltage check circuit 16a …… Voltage identification circuit (voltage identification means) 16b …… Timer circuit 16c …… Timing signal generation circuit (timing regulation means)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 5/781

Claims (1)

[Claims] 1. While a command signal for instructing a continuous shooting operation is being input, the head records the information at a timing synchronized with a rotation detection pulse generated corresponding to the rotation of an applied disk-shaped information recording medium. In an electronic imaging device configured to repeatedly and successively record recorded image information on a medium, it is possible to identify which of a plurality of voltage regions the power supply voltage corresponds to is preset. When the voltage discriminating means for issuing the discriminating signal and the discriminating signal for indicating that the power supply voltage corresponds to a relatively high voltage region among the plurality of voltage regions are issued by the voltage discriminating device, the time measuring means The recording operation is controlled so that the recording operation is repeated each time at a timing regulated by a predetermined time count, and the power supply voltage is raised by the voltage identifying means. When the identification signal indicating that it is in a relatively low voltage region among the plurality of voltage regions is issued, the access operation of the head is completed without depending on the predetermined time count by the time count means. An electronic image pickup apparatus comprising: a recording timing control unit configured to control the recording operation such that the recording operation is repeated each time the rotation detection pulse immediately after arrives.