JPH0786963B2 - Disc device playback circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The peak shift and amplitude fluctuation of a head output signal are individually equalized and corrected using two equalization circuits including a delay line and an attenuator, and then converted into a rectangular wave read signal. Regarding the reproduction circuit of the disk device, the delay line of the equalization circuit that corrects the peak shift and the delay line of the equalization circuit that corrects the amplitude fluctuation are provided for the purpose of matching the delay characteristics between the two equalization circuits and simplifying the circuit configuration. Common,
The number of delay lines is reduced and the delay characteristics of the equalization circuits are prevented from varying.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproduction circuit of a disk device for converting a reproduction signal read from a head into a rectangular wave signal after performing peak shift and equalization correction of amplitude fluctuation.

In a reproducing circuit of a magnetic disk device, a peak position of a reproduction signal read from a head is detected, an amplitude width exceeding a predetermined slice level is detected, and an original signal is obtained based on the detected peak position and amplitude width. The square wave signal that faithfully represents

In the reproducing circuit of such a disk device, since the peak position of the reproduced signal shifts due to the correlation with other adjacent peak positions in the front and rear (size of time interval), equalization for correcting this peak shift A circuit is needed. Further, since the amplitude of the reproduced signal fluctuates when the reproduced frequencies differ, an equalization circuit for correcting the fluctuation in amplitude is required.

Furthermore, since the optimum values of the equalization circuit that corrects the peak shift and the equalization circuit that corrects the amplitude fluctuation do not match, it is necessary to provide a circuit for each equalization correction individually, and two equalization circuits are required. When provided, it is desired to match the delay characteristics of the equalization circuits and to simplify the circuit configuration as much as possible.

"Prior Art" FIG. 5 is a block diagram of a reproducing circuit provided with the equalizer circuit, which has been already proposed by the inventors of the present application, for separately performing peak shift and amplitude fluctuation correction.

In FIG. 5, 10 is a head, and the reproduction signal read from the head 10 is amplified by the preamplifier 34 having a constant gain. The output of the preamplifier 34 is branched into two, and then the resistor 3
The voltage is pulled up to the power supply voltage Vcc via 6, 38 and input to the first equalization circuit 100 that corrects the peak shift and the second equalization circuit 200 that corrects the amplitude fluctuation.

The output of the first equalization circuit 100 is input to the peak position detection circuit 40, and the read signal is differentiated and then input to the zero-cross comparator to rise to the H level at the peak position of the read signal and remain at the H level for a predetermined time. A peak position detection signal (rectangular wave signal) to be maintained is generated.

The output of the second equalization circuit 200 is input to the amplitude detection circuit 42, and the amplitude detection circuit 42 outputs an amplitude detection signal (rectangular wave) having an amplitude width with the reference voltage ± Vr from the reference voltage generation circuit 44 as the slice level. Signal). Finally, in the classification circuit 46, a logical product (AND) of the output of the peak position detection circuit 40 and the output of the amplitude detection circuit 42, etc. is taken to produce a reproduced signal whose waveform is shaped into a rectangular wave signal.

The first equalization circuit 100 includes a delay line 12-1 having a delay time τ1, a delay line 14-1 having a delay time τ2, attenuators 22 and 26, and an adder / subtractor amplifier 30, and the second equalization circuit 200 is also the same. In addition, delay lines 12-2 and 14-2 having different delay times τ1 and τ2, attenuators 24 and 28, and an adder / subtractor amplifier 32 are provided.

In this way, the output of the head 10 is branched into two and two equalization circuits are provided.
The reason why the circuit configuration is input individually to 100 and 200 is that the optimum value of the attenuator that corrects peak shift and amplitude fluctuation is different, and the optimum value of the attenuator is set individually for each equalization circuit 100 and 200. I am able to do it.

Here, the reproduction signal from the head 10 is, as shown in FIG.
Before and after the main signal waveform 48, there are negative edges 50 which are amplitude components with opposite polarities. Therefore, in the equalization circuits 100 and 200 of FIG. 5, attenuation amounts are set by the attenuators 22 and 24 mainly for correcting the peak shift and amplitude fluctuation of the main signal waveform 48, and the attenuators 26 and 28 are used. Negative edge 5
The amount of attenuation is set to correct the peak shift and amplitude fluctuation due to 0.

[Problems to be Solved by the Invention] However, in such a reproducing circuit, two delay lines having delay times τ1 and τ2 are provided in each of the equalizing circuits 100 and 200, and the delay lines 12-1 and 12 are provided.
-2 and between the delay lines 14-1 and 14-2 are difficult to exactly match, equalization correction cannot be performed accurately due to variations in delay time, and the number of delay lines However, there is a problem in that the circuit configuration becomes complicated and the cost increases because there are many cases.

The present invention has been made in view of such problems,
It is an object of the present invention to provide a reproducing circuit for a disk device in which the delay characteristics of two equalizing circuits are made to coincide with each other and the circuit structure is simplified.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

Referring to FIG. 1, the present invention is directed to a reproducing circuit of a disk device for converting a reproduced signal read from the head 10 into a rectangular wave read signal after performing peak shift and equalization correction of amplitude fluctuation.

Regarding such a reproducing circuit, in the present invention, the head
A first delay line 12 for delaying the reproduction signal from 10 by a predetermined time τ1; a second delay line 14 for further delaying the output of the first delay line 12 for a predetermined time τ2; and a high level inputting the output of the second delay line 14 A first buffer amplifier 16 having an input impedance; a second buffer amplifier 18 having a high input impedance to which the output of the first delay line 12 is input; and a high input impedance to which a reproduction signal from the head 10 is directly input A third buffer amplifier 20 and a first buffer amplifier 20 to which the output of the second buffer amplifier 18 is input
And second attenuators 22 and 24; and third and fourth attenuators 26 and 28 to which the output of the third buffer amplifier 20 is input.

Finally, the output of the first attenuator 22 is subtracted from the output of the first buffer amplifier 16 by the first adder / subtractor amplifier 30 and the output of the third attenuator 26 is added, so that the peak shift is performed. Output the reproduction signal that has been subjected to the digitalization correction, subtracts the output of the second attenuator 24 from the output of the first buffer amplifier 16 by the second adder / subtractor amplifier 32, and outputs the output of the fourth attenuator 28. It is configured to output a reproduction signal subjected to equalization correction of amplitude variation by adding.

[Operation] In the reproducing circuit of the disk device according to the present invention having such a configuration, the delay line provided in the equalizing circuit for peak shift correction and the equalizing circuit for amplitude fluctuation correction should be shared. Therefore, the circuit configuration can be simplified by reducing the number of delay lines from four to two.
Since the same delay line is used for two equalization circuits, there is no variation in delay characteristics, and equalization correction can be accurately performed on the head signal, and the reliability during signal reproduction can be greatly improved.

[Embodiment] FIG. 2 is a configuration diagram of an embodiment showing one embodiment of the present invention.

In FIG. 2, reference numeral 10 is a head, and a reproduction signal from the magnetic disk read by the head 10 is amplified by a preamplifier 34 having a constant gain. Following the preamplifier 34, an equalization circuit for performing equalization correction of peak shift and amplitude fluctuation on the reproduction signal read from the head 10 is provided.

This equalizer circuit pulls up the output line of the preamplifier 34 to the power supply voltage Vcc via the resistor 36, and outputs the reproduction signal from the preamplifier 34 to the first delay line 12 having a delay time τ1.
To enter. Following the first delay line 12, a second delay line 14 having a delay time τ2 is provided, and a second delay line 14 is provided.
The output of the delay line 14 is input to the first buffer amplifier 16 having a high input impedance.

The output of the first delay line 12 is further branched and input to the second buffer amplifier 18, and the second buffer amplifier 18 also has a high input impedance like the first buffer amplifier 16.

Further, the reproduction signal from the preamplifier 34 is directly input to the third buffer amplifier 20 having a high input impedance.

The output of the second buffer amplifier 18 to which the output of the first delay line 12 is input is branched into two and is divided into first attenuators 22 respectively.
And to the second attenuator 24. The first attenuator 22 is provided for peak shift correction, and the attenuator 22 mainly performs peak shift on the main portion of the reproduced signal waveform. The second attenuator 24 is provided to correct the amplitude fluctuation, and is provided to correct the main portion of the reproduced signal waveform.

The output of the third buffer amplifier 20 to which the output of the preamplifier 34 is directly input is also branched into two and input to the third attenuator 26 and the fourth attenuator 28, respectively. The third attenuator 26 is provided to correct the peak shift, and corrects the peak shift due to the influence of the negative edge of the reproduced signal waveform. The fourth attenuator 28 is provided to correct the amplitude fluctuation and corrects the effect of the amplitude fluctuation due to the negative edge of the reproduced signal waveform.

At the final stage of the equalization circuit, a first addition / subtraction amplifier 30 for performing addition / subtraction for correcting peak shift and a second addition / subtraction amplifier 32 for performing addition / subtraction for correcting amplitude fluctuation are provided.

That is, the first addition / subtraction amplifier 30 is the first buffer amplifier 16
Subtracts the output of the first subtractor 22 from the output of
The outputs of the attenuation values 26 are added, and as a result of the addition and subtraction, a reproduction signal whose peak shift is equalized and corrected is output.

In addition, the second addition / subtraction amplifier 32 is the first buffer amplifier 16
The output of the second attenuator 24 is subtracted from the output of
The output of the attenuator 28 is added, and a reproduction signal in which the amplitude fluctuation is equalized and corrected by the addition and subtraction of these is output.

In such an equalizing circuit of the present invention, the delay lines 12 and 14 are commonly used for the equalizing circuit for correcting the peak shift and the equalizing circuit for correcting the amplitude variation, and four delay lines are conventionally required. According to the present invention,
Since only one delay line is required, the circuit structure can be simplified, and at the same time, the delay characteristics of the two equalization circuits can be completely matched by using the common delay line.

Also, the reproduction signal that has passed through the delay lines 12 and 14 is input to the buffer amplifier 16, but since the input impedance of the buffer amplifier 16 is sufficiently high, the reproduction signal from the delay line 14 is reflected at the input of the buffer amplifier 16 and After returning to 14, the reflected signal is added to the input of the buffer amplifier 18, and further returns to the delay line in 12 and returns to the buffer amplifier.
Reflected signal is added to 20 inputs.

That is, the buffer amplifier 18 receives a composite signal of the reproduction signal that has passed through the delay line 12 and the reflected signal that has returned from the delay line 14.

In addition, the buffer amplifier 20 reflects the reproduction signal from the preamplifier 34 and the input of the buffer amplifier 16 and delays the delay line.
The combined signal with the reflected signal that has returned through 14 and 12 is input.

Here, an attenuator for peak shift correction provided in the equalization circuit
The method of determining the attenuation amounts of 22 and 26 is such that the time width of the rising edge of the output signal of the zero-cross comparator 54 provided in the peak position detection circuit 40 becomes a predetermined value.

In addition, the attenuators 24 and 28 for compensating for amplitude fluctuations provided in the equalization circuit
As a method of determining the amount of attenuation, the amplitude of the maximum frequency fmax signal of the read signal from the head 10 and the amplitude of the reproduction signal of the minimum frequency fmin are set to be equal at the output of the adder / subtractor amplifier 32.

Next, the operation of the embodiment of FIG. 2 will be described with reference to the signal waveform diagrams of FIGS.

FIG. 3 (A) shows an output signal waveform from the head 10 which is the output of the preamplifier 34. The head output signal has peak positions P1 to P6, and is located after the peak position P1 and at the peak positions P3 and P4. A continuous reproduction signal waveform having a negative edge 50 before and after, and further before the peak position P5 is shown.

The reproduced signal from the head 10 shown in FIG. 3 (A) includes delay lines 12 and 14, buffer amplifiers 16 to 20, attenuators 22 to 28,
It is input to the equalization circuit consisting of adder / subtractor amplifiers 30 and 32, and equalization correction for peak shift and amplitude fluctuation is performed individually,
The outputs of the addition / subtraction amplifiers 30 and 32 shown in FIG. 3 (B) are obtained. That is, from the output waveforms of the adder / subtractor amplifiers 30 and 32, the reproduced signal waveform in which the negative edge 50 of the head output waveform shown in FIG. 9A is removed and the peak position is delayed by (τ1 + τ2) is obtained.

In FIG. 3, the attenuator is shown in order to simplify the explanation.
22 and 26 and 24 and 28 are shown to have the same attenuation amount. Therefore, the addition / subtraction amplifier 30 for peak shift correction is shown.
2 and the output waveform of the addition / subtraction amplifier 32 that corrects the amplitude fluctuation are shown as the same waveform. Of course, in the actual equalization circuit, the attenuators 22 and 26 are set to the optimum values specific to the peak shift, and the attenuators 24 and 28 are set to the optimum value specific to the amplitude variation, and the time delays are the same. However, the waveform itself does not always match.

The output of the adder / subtractor amplifier 30 is given to the peak position detection circuit 40 and differentiated by the differentiating circuit 52 to obtain a differential signal that has a zero cross at the peak position. The differentiated output of the integration circuit 52 is input to the zero-cross comparator 54, which rises to the H level at the zero-cross position and generates a peak position detection signal having a signal waveform shown in FIG. 3 (C) which maintains the H level for a predetermined time.

On the other hand, the output of the adder / subtractor amplifier 32 is given to the amplitude detection circuit 42 and compared with the reference voltages + Vr, -Vr from the reference voltage generation circuit 44 for the comparators 56, 58, and the time width in which this reference voltage is used as a slice level is represented. The amplitude detection signal shown in FIG. 3 (D) as a rectangular wave signal is generated.

The outputs of the peak position detection circuit 40 and the amplitude detection circuit 42 are given to the classification circuit 46, and the AND circuit 64 takes the logical product of both input signals to output the classification circuit shown in FIG. Generate PD.

FIG. 4 is an operation signal waveform diagram in the equalization circuit of FIG. 2 in which the signal waveform at the peak position P3 having the negative edge 50 in the output signal from the head 10 of FIG. 3 (A) is shown as an isolated waveform.

In FIG. 4, the output signal from the head 10 shown in FIG. 4A is first delayed by .tau.1 time in the delay line 12, and has a signal waveform shown in FIG. Further, the signal is delayed by .tau.2 time on the delay line 14 to form the signal waveform shown in FIG. 4 (C), which is given to the adder / subtractor amplifiers 30 and 32 via the buffer amplifier 16.

On the other hand, a combined signal of the signal of FIG. 4 (B) that has passed through the delay line 12 and the signal that has been reflected by the input of the buffer amplifier 16 and has returned through the delay line 14 is input to the buffer amplifier 18, As a result, the output waveforms shown in FIG. 4D are given to the adder / subtractor amplifiers 30 and 32 from the attenuators 22 and 24 that received the output of the buffer amplifier 18.

Further, the buffer amplifier 20 has a head shown in FIG.
An attenuator 26,2 receiving the output of the buffer amplifier 20 is provided with a composite signal of the output of 10 and the reflected signal reflected by the buffer amplifier 16 and returned through the delay lines 14,12.
From 8 the output shown in FIG. 4 (E) is given to the adder / subtractor amplifiers 30 and 32.

As a result, in the adder / subtractor amplifiers 30 and 32, the output of the attenuator 22 shown in FIG. 4D is subtracted from the output of the delay line 14 shown in FIG. The outputs of the attenuator 26 shown are added to produce the outputs shown in FIG.

By performing the same processing as the isolated waveform having the peak position P3 shown in FIG. 4 on the continuous reproduction signal waveform shown in FIG. 3A, the peak shift shown in FIG. It is possible to individually obtain the reproduction signals that have been equalized and corrected for each of the amplitude fluctuations.

[Effects of the Invention] As described above, according to the present invention, it is possible to separately provide an equalization circuit for performing equalization correction for peak shift and equalization correction for amplitude fluctuation on a head reproduction signal. Since the delay lines used for the two equalization circuits can be made common, the delay characteristics of the two equalization circuits can be completely matched by the common use of the delay lines, and accurate waveform equalization can be performed. Since the number can be reduced by half, the circuit configuration can be simplified and the cost can be reduced.

[Brief description of drawings]

1 is an explanatory view of the principle of the present invention; FIG. 2 is a configuration diagram of an embodiment of the present invention; FIGS. 3 and 4 are operation signal waveform diagrams of the present invention; FIG. 5 is a configuration diagram of prior art; FIG. 6 is a head reproduction waveform diagram having a negative edge. In the figure, 10: head 12: first delay line (τ1) 14: second delay line (τ2) 16: first buffer amplifier 18: second buffer amplifier 20: third buffer amplifier 22: first Attenuator (for peak shift correction) 24: Second attenuator (for amplitude fluctuation correction) 26: Third attenuator (for peak shift correction) 28: Fourth attenuator (for amplitude fluctuation correction) 30: No. 1 addition / subtraction amplifier (for peak shift correction) 32: second addition / subtraction amplifier (for amplitude fluctuation correction) 34: preamplifier 40: peak position detection circuit 42: amplitude detection circuit 44: reference voltage generation circuit 46: classification circuit 48: main Waveform 50: Negative edge 52: Differentiation circuit 54: Zero cross comparator 56,58: Comparator 60,62: Reference voltage source 64: AND gate

Claims (1)

[Claims] 1. A reproducing circuit of a disk device for converting a reproduction signal read from a head (10) into a rectangular wave signal after performing peak shift and equalization correction of amplitude fluctuation. A first delay line (12) for delaying the reproduced signal of the first delay line (12) by a predetermined time (τ1); and outputting the output of the first delay line (12) for a predetermined time (τ2).
A delayed second delay line (14); a first buffer bump (16) having a high input impedance to which the output of the second delay line (14) is input; and an output of the first delay line (12) Second buffer amplifier having high input impedance (18)
And a third buffer amplifier (20) having a high input impedance to which the reproduction signal from the head (10) is directly input.
A first and a second attenuator (22, 24) for inputting and attenuating the output of the second buffer amplifier (18); and an input for attenuating the output of the third buffer amplifier (20) A third and a fourth attenuator (26, 28); and a third attenuator (26) that subtracts the output of the first attenuator (22) from the output of the first buffer amplifier (16). A first adder / subtractor amplifier (30) that outputs a reproduction signal whose peak shift has been equalized by adding the outputs of (26); and the second attenuation from the output of the first buffer amplifier (16). Second adder / subtractor amplifier (32) for outputting a reproduction signal whose amplitude fluctuation is equalized and corrected by subtracting the output of the amplifier (24) and adding the output of the fourth attenuator (28).
And a reproducing circuit for a disk device, which is provided with;