JPH0786756B2 - Music signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention calculates a musical tone signal waveform based on a predetermined waveform calculation such as frequency modulation calculation and amplitude modulation calculation, and generates a musical tone signal according to the calculation result. The present invention relates to a musical tone signal generator for outputting.

[Prior Art] As a device of this type, a plurality of inputs are provided, and a modulation operation unit for performing a modulation operation based on input information applied to the inputs, and a plurality of operation waveforms stored in the modulation operation unit are stored. And storage means of
It is known in the related art to perform waveform calculation based on a predetermined algorithm by time-divisionally switching the connection mode between the modulation calculation unit and the plurality of storage means. (See Japanese Laid-Open Patent Publication No. 62-83795) In the same device, the output level of each modulation operation unit is changeable, and the input level in the subsequent modulation operation unit is adjusted.

Also, as the input information for each modulation operation unit,
Any one of the waveform information calculated in the modulation calculation unit in the preceding stage and stored in the storage means in various modes,
The waveform information from the preceding modulation operation unit that has passed through the feedback path can be used, and each modulation operation unit combines the two with other input position information, or selectively inputs only one of them. I was doing modulation calculations.

[Problems to be Solved by the Invention] In the above-described conventional tone signal generator, the output level of each modulation operation unit is changed to adjust the input level in the modulation operation unit in the subsequent stage. Although there is no problem when used in one place in the latter stage, when the calculation result is used as an input to a plurality of modulation calculation units in the latter stage, the input level cannot be adjusted individually.

Also, as the input information for each modulation operation unit,
The waveform information from the preceding-stage modulation calculation unit stored in various modes and the waveform information from the subsequent-stage modulation calculation unit that has passed through the feedback path, or either of them can be selectively obtained, but each is arbitrary. It was not possible to combine it with and use it as input information.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a musical tone signal generator capable of increasing the degree of freedom in creating a sound by making the connection mode of each modulation operation unit more flexible. And

[Means for Solving the Problems] In order to achieve the above object, the structural features of the present invention are as follows.
The modulation calculation unit includes a plurality of inputs and performs a modulation calculation based on input information applied to the inputs, and a plurality of storage means for storing the calculation waveform calculated by the modulation calculation unit. In a musical tone signal generator that performs waveform calculation based on a predetermined algorithm by time-divisionally switching a connection mode between a unit and the plurality of storage units, each calculation waveform stored in the plurality of storage units is included. A plurality of selection means for selecting one input information from the plurality of input information and supplying it to each input of the modulation operation unit, and a plurality of inputs of the modulation operation unit from the plurality of selection means. And a plurality of input information value changing means for changing the magnitude of the value of each input information supplied to each.

[Operation and Effect of the Invention] In the present invention configured as described above, a plurality of selection means are provided at the input of the modulation operation unit, and the selection means outputs the operation waveforms stored in the plurality of storage means. Since one input information is selected from each of a plurality of input information including and is supplied to each input of the modulation operation unit, various combinations can be given as input information to the modulation operation unit, and the operation waveform is repeatedly applied to the modulation operation unit. The algorithms realized by inputting become more diverse, and the degree of freedom in sound creation is improved. Further, due to the presence of the plurality of selection means, various waveform signals other than the operation waveform by the modulation operation unit are stored in the storage means, or before and after the operation waveform before and after the operation by the modulation operation unit, It is also possible to supply it to the modulation operation unit, and it is possible to perform the same sound production as that of the tone signal generator having a large-scale modulation operation unit while having a small-scale configuration.

Further, input information value changing means is provided between the plurality of selecting means and each input of the modulation operation unit, and the input information value changing means is a value of each input information selected by the plurality of selecting means. The input level can be adjusted individually even when the calculation result of each modulation calculation unit is used as input information by multiple modulation calculation units, and the obstacles associated with such input level adjustment can be prevented. The range of algorithms that can be prevented and implemented can be expanded.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 schematically shows the entire electronic musical instrument to which the present invention is applied. The electronic musical instrument uses a frequency modulation type sound source
The CPU 30, which has the 10 and which is connected to the bus 20, executes a predetermined process based on a predetermined program stored in the ROM 40 while using the work area provided in the RAM 50, and the keyboard 60 and the panel. The generation of a tone signal corresponding to the operation of the operator 70 is controlled. The output of the sound source unit 10 is connected to a sound system 90 via a digital / analog converter (hereinafter referred to as a D / A converter) 80. The sound system 90 is composed of an amplifier, a speaker, etc., and generates a musical tone corresponding to the musical tone signal converted into an analog signal by the D / A converter 80. The electronic musical instrument also includes a display unit 100 that visually displays a tone color setting state by the panel operator 70. In the following drawings, the unshaded arrow lines indicate single-bit signal lines, and the hatched arrow lines indicate multi-bit signal lines.

The sound source section 10 has a first sound source section 11 and a second sound source section 12, both of which are synchronized with a system clock timing and a channel clock timing by a synchronization signal output from a timing generation circuit 13. First sound source section 11 and second
A control signal from the CPU 30 is input to the tone generator 12 via the bus 20, and the tone generators 11 and 12 generate a predetermined tone signal based on the control signal. In addition, the tone signals generated by the tone generators 11 and 12 are input to the mixer 14 and synthesized, and
The tone signal generated by the tone generator 11 is also input to the second tone generator 12.

As shown in FIG. 3, the second sound source section 12 is composed of a tone signal waveform circuit 12a for performing waveform calculation.

The tone signal forming circuit 12a forms a tone signal according to an external waveform signal, various control signals for setting and controlling tone color, a phase data signal representing frequency information, an envelope signal, and the like. Except for the external waveform signal input from the first sound source unit 11, this signal group is directly input from the control signal generation circuit 12b, and the parameter generation circuit 12c and the frequency depending on the control signal of the circuit 12b. It is supplied from an information (hereinafter referred to as F number) generation circuit 12d, a phase data generation circuit 12e, and an envelope generation circuit 12f.

A detailed description of various signals output from these circuits will be given in parallel with the description of the more detailed circuit configuration of the tone signal forming circuit 12a with reference to FIG.

The tone signal forming circuit 12a has a modulation operation unit (hereinafter, referred to as an operation unit) that inputs a phase angle and performs a sine wave function operation, and performs repeated waveform operation by combining each input and output. As a result, an arithmetic system including the arithmetic units connected in a predetermined manner is realized. Further, the tone signal forming circuit 12a divides one operation cycle into a plurality of time slots to perform a waveform operation, and each waveform operation itself is further subdivided into a plurality of channels so that a compound sound can be output. There is.

The input phase angle of the sine wave function is obtained as the added value of the three pieces of input information in the adder 200. Among these, the first input information is phase information obtained by adding the phase angle obtained by the F number generating circuit 12d for each clock in the phase data generating circuit 12e, and the second and third input information are respectively the selectors. 20
One input information selected by the selector 201a, 201b from the plurality of input information input to the 1a, 201b is scaler 202a,
It was corrected in 202b. This selector 201
Each of a and 201b has 11 inputs, and one of them is selected according to the control signals ISEL1 and ISEL2 from the control signal generation circuit 12b. The level correction in the scalers 202a and 202b is controlled by the control signals IL1 and IL2 from the parameter generating circuit 12c.

The phase information obtained by the adder 200 is input as address data of the sine wave table 203, and the sine wave function value stored corresponding to each address is read from the table 203. At this time, in order to easily apply the envelope and change the modulation index, the sine wave table 203 stores a sine wave function value as a logarithmic value, and the adder 204 stores the function value and the envelope index EL. , And the modulation index LC, and the added data is input to the logarithmic / linear conversion circuit 205. At this time, the envelope index EL is input from the envelope generating circuit 12f, and the modulation index LC is input from the parameter generating circuit 12c.

The output of the logarithmic / linear conversion circuit 205 is input to a delay circuit 206 including a shift register having several stages of channels, delayed by one time slot, and then the selectors 201a, 201b,
Registers 207a-c (denoted as R1-R3 in the following schematic drawings),
Feedback registers (hereinafter, referred to as FB registers) 209a to 209 (FBR1 to FBR3 in the following schematic diagrams) via the adder 208.
Is written. ) And the selector 210, and is input to the adder 211.

Here, the registers 207a-c and the FB registers 209a-c are respectively composed of a selector 212 of two inputs and a shift register 213 of several stages of channels as shown in FIG. 4, and write signals WS (WS1 to WS3) When it changes from "0" to "1", the data input at that time is retained. For example, when the write signal WS is “0”, the selector 212 selects the output of the shift register 213 as the input of the shift register 213, so that a loop is formed and the data is circularly held. On the other hand, when the write signal WS becomes "1", the selector 212 selects the input data from the outside and fetches the same data in the shift register 213.

The write signals WS1 to WS3 are output from the control signal generation circuit 12b together with the selection control signal FBSEL for the selector 214,
Data write timings in the registers 207a to 207c and the FB registers 209a to 209c are synchronized, and write targets by the write signals WS1 to WS3 (targets to be "1").
And the selection target in the selector 214 match. For example, if the write signal WS1 becomes "1", the selection control signal FBSEL
Becomes "1" and the selector 214 selects the input 1, so that the data stored in the register 207a and the delay circuit 20
The data output from 6 is added by the adder 208, and the added data is stored in the FB register 209a. Such an operation leads to averaging of both data and is used to prevent a hunting phenomenon that occurs when feedback is performed in the arithmetic unit. The registers 207a to 207c and the FB registers 209a to 209c are paired to form a register pair.

The output of the delay circuit 206 is connected to one input of the selector 210, the output of the selector 210 is connected to one input of the adder 211, and the output of the gate 215 is connected to the other input of the adder 211. ing. Also, adder 2
The output of 11 is connected to the input of an accumulation register 216 composed of a shift register having several channels, and the output of the accumulation register 216 is connected to the input of a gate 215. That is, the adder 211, the accumulation register 216, and the gate 215 constitute an accumulator. Also, selector 21
An external input data register 218 to which data is externally input via the interface 217 is connected to the other input of 0.

In such a connection mode, selection of the selector 210 and conduction / non-conduction of the gate in the gate 215 are controlled by the control signals ACSEL and ACG from the control signal generation circuit 12b, and the control signal ACSEL indicates "1" and the selector When the input signal 210 is selected by the delay circuit 206, that is, when the control signal ACG indicates "1" and the gate 215 is conductive, the output data of the delay circuit 206 is the register 2 for accumulation.
The data in 16 is sequentially accumulated, and if the control signal ACG indicates "0" and the gate 215 is in the non-conducting state, the output data of the delay circuit 206 is newly input into the accumulation register 216. . If the control signal ACSEL indicates "2" and the selector 210 selects the output of the external input data register 218, the external input data is accumulated and stored.

Further, when the control signal ACSEL indicates "0", the selector 210 outputs data of "0" without selecting both inputs. At this time, therefore, the control signal ACG indicates "1" and the gate 215 is conductive. If so, the data of the accumulation register 216 is input again to the accumulation register 216 and is circularly held.

The external input data register 218 has a configuration shown in FIG. 5 in which two stages of registers each consisting of a selector and a shift register having several stages of channels are combined in series.
When the data change write signal DC input to 219 changes from "0" to "1", the external waveform data is shifted to the shift register 220.
When the control signal TS that is taken in by and is input to the selector 221 in the subsequent stage changes from “0” to “1”, the content of the shift register 222 is updated to new external waveform data at the changed timing.

The inputs of the selectors 201a and 201b are respectively "0" data, the output of the delay circuit 206 described above, and the FB registers 209a to 209c.
Output of the register 207a-c, output of the adder 211,
Output of external input data register 218 and noise generator 2
Noise data output from 23 is input, and one is selected for each of the values "0" to "10" of the control signals ISEL1, ISEL2.

The output of the tone signal forming circuit 12a uses the output of the accumulation register 216, and the mixer 14 is output via the output register 224.
Is output to.

Next, the operation of the electronic musical instrument having the above configuration will be described.

After turning on the power, the performer performs an operation for creating a sound before starting the performance.

Sound production is performed by operating the panel operator 70, and the specific operation status is displayed on the display unit 100. As for the content of sound creation, in addition to selecting a preset tone color by button operation, an operation of sending detailed sound creation information to the sound source unit 10 is possible. As such detailed sound production, each tone color in the first sound source section 11 and the second sound source section 12 is set to determine the degree of synthesis in the mixer 14, or in the tone signal forming circuit 12a in the second sound source section 12. There are operations such as setting the algorithm.

When the sound making operations are the same, start playing. When the performer presses the keyboard on the keyboard unit 60, the CPU 30 detects the pressed key according to the program stored in the ROM 40, and
The pressed state is also detected, and a key-on signal (KON), a key code signal (KC), a touch signal (IT) and the like representing the information thereof are sent to the sound source unit 10.

The tone generator section 10 has a tone color according to the operation of creating the sound, and
A musical tone signal corresponding to various input signals KON, KC, IT, etc. is formed. For example, frequency information is obtained from the key code signal, while envelope information is obtained from the touch signal and the key-on signal to generate a tone signal.

Here, referring to the configuration of the second sound source section 12, when the frequency information generation circuit 12d sends the F number to the phase data generation circuit 12e under the control of the control signal generation circuit 12b, the same phase data generation circuit 12e is generated. Is the phase data P for the tone signal forming circuit 12a.
In addition, the envelope generating circuit 12f sends the envelope index EL to the tone signal forming circuit 12a. Further, in parallel with this, the control signal generation circuit 12b and the parameter generation circuit 12c send control signals mainly related to tone color formation to the tone signal formation circuit 12a.

The tone signal forming circuit 12a forms a tone signal according to the set tone color information, and such signal formation is performed by waveform calculation based on a predetermined algorithm.

Here, the algorithm in the tone signal forming circuit 12a will be described. As an example, a timing chart is shown in FIG. 7 so as to realize the algorithm shown in FIG. 6, and the description will be made with reference to both figures.

A cycle for computing one sample data of a waveform is called one computation cycle. In this case, one sample data is computed by six computations, and each computation timing is specified as a time slot. Therefore, one operation cycle consists of 6 time slots. However, each time slot is subdivided into a plurality of channels in order to enable compound sound output, and in the following description, it is assumed that the number of channels is repeatedly calculated in each time slot.

In the tone signal forming circuit 12a, it is the adder 200 that forms a substantial arithmetic unit (in the figure, is referred to as "OP", and arithmetic units that sequentially perform operations in 6 time slots are referred to as "OP6" to "OP1". "). , The sine wave table 203, the adder 204, and the logarithmic / linear conversion circuit 205, and the other parts are used to set the connection mode of the arithmetic unit. Therefore,
Waveform calculation performed by one calculation unit OPx is performed by inputting phase data Px and waveform signal (hereinafter referred to as waveform data) ω1x, ω2x, modulation index LCx, envelope index
From ELx, OPx output = ELx ・ LCx ・ sin (Px ＋ ω1x ＋ ω2
x).

To achieve the algorithm shown in FIG. 6, the following steps may be taken.

Arithmetic unit 6 Performs waveform arithmetic and stores arithmetic data in the accumulation register.

The operation unit 5 performs a waveform operation and accumulates the operation data into the data in the accumulation register.

The calculation unit 4 performs waveform calculation.

Waveform calculation is performed by the arithmetic unit 3 as input of waveform data of the data of the accumulation register and the arithmetic data of the arithmetic unit 4, and the arithmetic data is stored in the accumulation register.

The calculation unit 2 performs waveform calculation.

The waveform data of the calculation unit 1 is calculated by using the calculation data by the calculation unit 2 as the input of the waveform data, and the calculation data is accumulated in the data of the accumulation register.

Output the data in the accumulation register and repeat the following.

Note that, in the above description, if the input of waveform data is omitted, data other than the calculation data of other calculation units can be input. For example, although external data or noise data is possible, if only the phase data P is to be input, "0" may be input.

The calculation procedure will be described below for each time slot.

Time slot 1 It is the operation unit 6 (OP6) that performs the waveform operation,
Input the waveform data to the selectors 201a and 201b except the operation data of other operation units.
ISEL1 and ISEL2 are “0” to “4”, “9”, and “10” (hereinafter, this is represented as “A”).

Here, the FB registers 209a to 209c including "1" to "3" can be input, but since the FB registers 209a to 209c are the operation data obtained through the averaging circuit,
It can be directly input without being output from other arithmetic units.

The level adjustment for the input information selected by the selectors 201a and 201b is performed by the control signals IL1 and IL2 and set to "IL1-6" and "IL2-6", respectively (only IL1 is shown in the figure). However, IL2 is omitted.) When the waveform data ω1 and ω2 output from the scalers 202a and 202b are added together with the phase data P by the adder 200, and the added data is input as the address of the sine wave table 203. , The logarithmic value of the sine wave function value corresponding to the phase angle is read, and the modulation index LC6 is added by the adder 204 to the logarithmic value.
And the envelope index EL6. When the output of the adder 204 is input to the logarithmic / linear conversion circuit 205,
A normal sine wave function value is obtained, and the same data is output to delay circuit 206
To enter.

Time slot 2 The operation data input to the delay circuit 206 is delayed by one time slot and is output in the time slot 2. In order to store this in the accumulation register 216, it is necessary to select the input 1 by the selector 210 and keep the gate 215 non-conductive to prevent accumulation of previous data.
Therefore, control signals ACSEL and ACG are set to "1" and "0", respectively.
Set to.

On the other hand, the input of the waveform data to the arithmetic unit 5 selected by the selectors 201a and 201b is other than the arithmetic data of the other arithmetic units as in the case of the time slot 1, and according to the above notation, the control signals ISEL1, ISEL2 Becomes "A". Further, the control signals IL1 and IL2 for level adjustment for the scalers 202a and 202b are set to "IL1-5" and "IL2-5", and the modulation index LC and the envelope index EL for the adder 204 are set to "LC.
Set to “5” and “EL5”.

When the waveform calculation is performed, the calculation data is input to the delay circuit 206 and delayed by one time slot.

Time slot 3 The operation data of the operation unit 5 in the time slot 2 is output from the delay circuit 206. In order to accumulate this data in the data in the accumulation register 216, the selector 1 selects input 1 and The control signals ACSEL and ACG are set to "1" and "1" so as to make the gate 215 conductive.

For the arithmetic unit 4, similarly to the above, the control signals ISEL1 and ISEL2 of the selectors 201a and 201b are set to "A", and the control signals IL1 and IL2 for level adjustment in the scalers 202a and 202b are set to "IL1-4". , “IL2-4” and modulation index LC and envelope index EL are set to “LC4” and “EL4”.

The input of the waveform data to the arithmetic unit 3 selected by the time slot 4 selectors 201a and 201b is the arithmetic data of the arithmetic unit 4 output from the delay circuit 206 and the data held in the accumulation register 216. Therefore, in the selector 201a, the delay circuit 20
The selector 201b selects the output of 6 and sets the output of the selector 210 to "0", makes the gate 215 conductive, and stores the data held in the accumulation register 216 from the adder 211 to the selector 201b.
You need to send it to and select the data. In order to realize this, the control signals ISEL1 and ISEL2 of the selectors 201a and 201b are set to "1" and "8", and the control signals ACSEL and ACG for the selector 210 and the gate 215 are set to "0" and "1". The data stored in the accumulation register 216 is also retained as a result.

Various control signals IL1, IL2, L for the scalers 202a, 202b, etc.
C and EL are “IL1-3”, “IL2-3”, and “LC”, respectively.
3 "and" EL3 ".

Since the arithmetic data of the arithmetic unit 3 is output from the time slot 5 delay circuit 206, the selector 210 selects the input 1 to store the arithmetic data in the accumulation register 216 and the control signal to make the gate 215 non-conductive. Set ACSEL and ACG to "1" and "0".

On the other hand, for the waveform calculation in the arithmetic unit 2, the various control signals IL1, IL2, LC, EL of the selectors 201a, 201b are changed to "IL1-2", "IL2-2", "LC2", "EL2", respectively. Set.

Time slot 6 Since one input of the waveform data for the arithmetic unit 1 selected by the selector 201a is the arithmetic data of the arithmetic unit 2 output from the delay circuit 206, the control signal ISEL1 is set to "1" and the selector 201b selects The control signal ISEL2 is set to "A" as the other input selection of the waveform data for the arithmetic unit 1 to be selected.

On the other hand, since the data of the accumulation register 216 must be held, the control signal ACSEL, A is set so that the input is set to "0" by the selector 210 and the gate 215 is made conductive.
Set CG to "0" and "1".

The operation output of the operation unit 1 is output in the time slot 1 in the next operation cycle delayed by 1 time slot,
In this time slot 1, the arithmetic data of the arithmetic unit 3 stored in the accumulation register 216 is accumulated. For this reason, the control signals ACSEL and ACG are set to “1”, so that the selector 210 selects the input 1 and the gate 215 is made conductive.
Set to "1".

As described above, desired operation waveform data is obtained in the accumulation register 216, and the output register 224 is output in the next time slot 2.
And output it.

When the control signals ISEL1 and ISEL2 of the selectors 201a and 201b are "A", the external input data can be used as the waveform data, but there are two methods for fetching the external input data. One is a method of selecting the output of the external input data register 218 by the selectors 201a and 201b, and the other is a method of selecting the accumulation register 2 through the selector 210.
This is a method to fetch external input data to 16. In this latter method, it is naturally possible to make the gate 215 conductive and accumulate the external input data with the data already stored in the accumulation register 216. It should be noted that this accumulation register 216 is originally used for adding a plurality of operation outputs, and at the time of such addition, the register 216 cannot be used for taking in an external input. Indicates whether or not external input data can be taken into the accumulation register 216. That is, if the control signal ACSEL of the selector 210 is set to "2" instead of "0", external input data can be fetched.

In the figure, "B" in the register pair indicates that data can be written at any timing.

In the above example, the feedback register is not used in the waveform calculation, but when the output of the calculation unit is used as its own input, it can be realized as follows.

In the algorithm shown in FIG. 8, the output of the arithmetic unit 3 is used as the input of the waveform data to the arithmetic unit 2 and is taken into the FB register (FBR1) and the register (R), and the output of this FB register (FBR1) is concerned. The waveform data is input to the arithmetic unit 3, and the output of the register (R) is used as the waveform data input to the arithmetic unit 1.

The calculation procedure in the algorithm is as follows.

The arithmetic unit 6 performs a waveform operation and stores the operation data in the accumulation register.

The calculation unit 5 performs waveform calculation.

The data of the accumulation register and the arithmetic data of the arithmetic unit 5 are used as the input of the waveform data to perform the waveform arithmetic in the arithmetic unit 4, and the arithmetic data is stored in the accumulation register.

The data of the FB register is used as the input of the waveform data to perform the waveform calculation in the arithmetic unit 3, and the arithmetic data is input to the FB register (FBR) and the register (R) and is output to the arithmetic unit 2.

The calculation data of the calculation unit 3 is used as the input of the waveform data to perform the waveform calculation in the calculation unit 2, and the calculation data is accumulated in the data in the accumulation register.

The waveform data is calculated by the calculation unit 1 using the calculation data of the calculation unit 3 (data stored in the register (R)) as input of the waveform data, and the calculation data is accumulated in the data in the accumulation register.

Output register data for accumulation and repeat the following.

By the above calculation, a desired calculation waveform can be obtained in the accumulation register.

Then, the calculation status in each time slot is as follows. Note that the time slots 1 to 3 are omitted because they are easy to understand from the above example.

Time slot 4 A selector for inputting the data held in the FB register 209a to one input of the waveform data for the arithmetic unit 3.
Set the control signal ISEL2 of 201b to "2". Data that does not affect the algorithm can be selected for the other input of the waveform data, and the control signal ISEL1 of the selector 201a is set to "A".
Set to.

The other control signals IL1, IL2, LC, EL are "IL1-3" and "IL
Set “2-3”, “LC3”, and “EL3”.

Since the operation data of the operation unit 3 is output from the time slot 5 delay circuit 206, the write signal WS1 is output to store this in the register 207a (becomes "1" from "0"). Also, the control signal FBSEL for the selector 214 is set to "1",
The selector 214 outputs the data held by the register 207a (the operation data of the operation unit 3 one operation cycle before) to the adder 208.

In the adder 208, the operation data of the operation unit 3 (data of the current operation cycle) output from the delay circuit 206 and the data held in the register 207a (data of one operation cycle before) are added, and the averaged operation data is added. Is FB register 209a ~
It is output to c. Note that it is necessary to halve for averaging, but this is performed in the scalers 202a and 202b.

At this point, only WS1 is output as the write signal, and thus the operation data of the adder 208 is taken into only the FB register 209a. Therefore, in the time slot 4 in which the data of the FB register 209a is input as the waveform data, the operation data of the operation unit 3 is fed back and input through the averaging circuit.

On the other hand, in the arithmetic unit 2, the control signal ISEL1 of the selector 201a is set to "1" so that one input of the waveform data is the arithmetic data of the arithmetic unit 3 and the selector 201
Waveform calculation is performed by setting the control signal ISEL2 of b to "A".

Time slot 6 The control signal ACSEL of the selector 210 is set to "1" and the control signal ACG of the gate 215 is set to "1" in order to accumulate the operation data of the operation unit 2 into the data in the accumulation register 216. Further, one input of the waveform data to the arithmetic unit 1 is the arithmetic data of the arithmetic unit 3, and the arithmetic data is held in the register 207a in the time slot 5. Therefore, the control signal ISEL1 is set to "5" so that the data held in the register 207a is input to the arithmetic unit 1 as waveform data.

The operation data of the operation unit 1 is obtained in the time slot 1 of the next operation cycle, accumulated in the data of the accumulation register 216 in the same manner as described above, and taken out from the output register 242 in the next time slot. .

Now, in this embodiment, the registers 207a to 207c and the FB register 209a are
It is also free to obtain the averaged data from the FB registers 209a to 209c and to separately take out the data of the registers 207a to 207c in the preceding stage. Therefore, the six outputs of these three register pairs can be selected as the input of the waveform data to each arithmetic unit, and the degree of freedom of the algorithm is improved.

FIGS. 10 and 11 show an example of an algorithm combining the outputs of three register pairs.

For example, the calculation data of the calculation unit 6
While inputting one of the waveform data for 4,
The calculation data of the calculation units 5 and 4 are added to be used as one input of the waveform data to the calculation unit 3. Here, the calculation data of the calculation units 5 and 4 are individually fed back as the input of the calculation unit 6. Toshi (first
(See FIG. 10), and the calculation data of the calculation unit 2 is used as one input of the waveform data to the calculation unit 1, and the calculation data of the calculation unit 1 is added to the calculation data of the calculation unit 3 and output. .

Due to the fact that the calculation data of the calculation units 5 and 4 are accumulated, the calculation data of the calculation unit 6 must be held in a register other than the accumulation register 216 when the calculation unit 5 is performing waveform calculation. Register 207a must be assigned to. Further, since the operation data of the operation units 5 and 4 are used for feedback, this is done using the FB registers 209b and 209c. Therefore, all three register pairs are used.

As another example, the operation data of the operation unit 6 is input to the waveform data for the operation units 5 and 3, the operation data of the operation unit 5 is input to the waveform data to the operation units 4 and 2, and the operation of the operation unit 3 is performed. When data is added to the waveform data input to the arithmetic units 2, 1 and the arithmetic data of the arithmetic units 4, 2, 1 are accumulated (first
(See FIG. 1) also uses the accumulation register 216 in the arithmetic unit 4 and later. Therefore, three register pairs are used because it is necessary to hold the operation data of the operation units 6, 5, and 3.
In this case, although the FB register is not used, it goes without saying that it is also possible to use it as the other input of the waveform data to the arithmetic units 6, 5, 4, 3, 1.

As described above, the desired operation waveform is output from the second sound source unit 12, and is synthesized by the mixer 14 together with the waveform data output from the first sound source unit 11. The combined data is converted into an analog signal by the D / A conversion circuit 80, and is output from the sound system 90 as a musical sound in the audible band.

As described above, according to this embodiment, the operation data of each operation unit is stored in various modes, and the selectors 201a and 201b are used as the input of the waveform data to each operation unit.
Therefore, it is possible to arbitrarily select them, and there is room for selection of external waveforms and the like. Therefore, there is a great deal of freedom in creating sounds. In addition, since the size of the input information value selected in the latter stage of the selectors 201a and 201b can be adjusted, even if the calculation data is input to multiple calculation units, it is adjusted to the appropriate input level according to each case. can do.

In addition, the operation data is transferred to a group of registers 207a to 207c, a selector 214, an adder 208, and a feedback register group of a subsequent stage.
A plurality of register pairs 209a-c are used for averaging, and each data stored in the feedback register group 209a-c is selectively added by the selectors 201a, 201b at different timings or the same timings.
Since it can be supplied to 200, it is possible to perform feedback calculation using different waveform data in a plurality of calculation units and also to perform feedback calculation using different calculation data in a single calculation unit at the same time. Further, since the operation data in the register groups 207a to 207c of the preceding stage can be used as the waveform data of another operation unit in addition to the feedback register groups 209a to 209c of the subsequent stage, the range of possible modes of the algorithm is expanded.

In the above embodiment, only the device for forming the tone signal by performing the frequency modulation operation by the operation unit including the adder 200, the sine wave table 203, the adder 204 and the logarithmic / linear conversion circuit 205 has been described. The present invention uses the circuit shown in FIG. 3 of Japanese Patent Application Laid-Open No. 62-83795 cited in the above [Prior Art] as the arithmetic unit, so that a tone signal is generated by using amplitude modulation arithmetic. It can also be applied to a device for forming a.

[Brief description of drawings]

1 is a block diagram showing a configuration of a tone signal forming circuit of the present invention, FIG. 2 is a block diagram of an electronic musical instrument to which the present invention is applied, and FIG. 3 is a configuration of a second sound source section shown in FIG. FIG. 4 is a block diagram showing the configuration of the register, FIG. 5 is a block diagram showing the configuration of the external input data register, FIG. 6 is a block diagram showing the configuration of the algorithm, and FIG. 7 is FIG. 8 is a timing chart for realizing the algorithm shown in FIG. 8, FIG. 8 is a block diagram showing the configuration of another algorithm, FIG. 9 is a timing chart for realizing the algorithm shown in FIG. 8, FIGS. FIG. 3 is a block diagram showing a configuration of an algorithm that uses three register pairs. Explanation of code 200 …… Adder, 201 …… Selector, 202 …… Scaler, 2
03 …… sine wave table, 207 …… register, 208 …… adder, 209 …… feedback register, 210 …… selector, 215 …… gate, 216 …… accumulation register, 218 ……
External input data register, 223 ... Noise generator, 224 ...
… Output registers

Claims (1)

[Claims] 1. A modulation operation unit having a plurality of inputs and performing a modulation operation based on input information applied to the inputs, and a plurality of storage means for storing operation waveforms operated by the modulation operation unit. However, in the tone signal generating apparatus for performing waveform calculation based on a predetermined algorithm by time-divisionally switching the connection mode between the modulation calculation unit and the plurality of storage means, the plurality of storage means are stored. A plurality of selecting means for selecting one input information from a plurality of input information including each of the operation waveforms to be supplied to each input of the modulation operation unit, and a plurality of selecting means from the plurality of selecting means. And a plurality of input information value changing means for changing the magnitude of the value of each input information supplied to each input of the modulation operation unit. Musical tone signal generating apparatus according to claim.