JPH0786590A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the leakage current of a semiconductor device having a diffused layer, whose conductivity type is opposite to that of a well, especially the leakage current at each corner part of a region surrounded with a selective oxide film, by providing diffused regions, which have the same conductivity type as the diffused layer and have the lower impurity concentration than the diffused layer, at the outside of the diffused layer in the vicinities of the corner parts of the well. CONSTITUTION:At the four corner parts of a well 2 having the rectangular planar shape, n<->-type diffused regions 5a are provided at the outer surface of a diffused layer 4 so as to contribute to the reduction in leakage current. Namely, in the conventional device, the n<->-type diffused regions are not provided at the outer surface of the diffused layer, and therefore the profile of the impurity-concentration distribution at the junction of the diffused layer 4 and the well becomes steep. In this semiconductor, however, the n<->-type diffused region 5a is present betwen the diffused layer 4 and the well 2. Therefore, the steepness of the profile of the impurity concentration at the junction between the diffused layer 4 and the well 2 is eliminated, and the concentration of the electric field at the corner part of the well 2 becomes weak. Furthermore, local avalanche breakdown is less. Therefore, the junction leakage becomes less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular, a well in which a selective oxide film is formed on the surface of a semiconductor substrate having wells and the inner surface of each well is surrounded by the selective oxide film. And a semiconductor device having a diffusion layer of opposite conductivity type and a method for manufacturing the same.

[0002]

2. Description of the Related Art Generally, a DRAM has a p-type well and / or an n-type well formed in a semiconductor substrate, an n-channel MOS transistor element in the p-type well, and a p-channel MOS transistor element in the n-type well. To form
The elements are separated by a selective oxide film formed on the surface of the semiconductor substrate.

[0003]

By the way, a smaller leak current is required in the DRAM. Therefore, the inventor of the present invention investigated in which portion the leak current in the well becomes larger, the planar portion, the side portion of the selective oxide film surrounding the rectangular region, and the corner portion of the selective oxide film. It was found that the leak current was the largest at the corners of the film.

Then, when the cause is investigated, the electric field due to the reverse bias voltage applied between the drain and the well is concentrated in the corner portion of the selective oxide film, which causes avalanche breakdown, which causes a large leak current. It turned out to be the cause of this. And, the leak current increases remarkably as the impurity concentration of the well increases,
It is thought that this is because the electric field becomes stronger and the local breakdown increases.

The present invention has been made to solve the above problems, and a selective oxide film is formed on the surface of a semiconductor substrate having wells, and the inner surface of each well is provided with a selective oxide film.
An object of the present invention is to reduce the leak current of a semiconductor device having a diffusion layer of the opposite conductivity type to that well surrounded by the selective oxide film, particularly the leak current in the corner portion of the region surrounded by the selective oxide film.

[0006]

A semiconductor device according to claim 1 is characterized in that a diffusion region having the same conductivity type as that of the diffusion layer and a lower impurity concentration is provided outside the diffusion layer in the vicinity of the corner of the well. And A method of manufacturing a semiconductor device according to claim 2,
The method of manufacturing a semiconductor device according to claim 1, wherein the surface of the well is lightly doped with an impurity having a conductivity type opposite to that of the well by using the selective oxide film as a mask, and thereafter,
It is characterized in that the surface portion of the well is doped with an impurity having a conductivity type opposite to that of the well in a state where at least a portion where a diffusion region having a low impurity concentration is to be formed is masked.

A method of manufacturing a semiconductor device according to a third aspect is the method of manufacturing a semiconductor device according to the second aspect, wherein light doping of impurities is performed in a lightly doped drain forming step,
It is characterized in that impurities are doped in the source and drain forming steps. A method for manufacturing a semiconductor device according to claim 4 is the method for manufacturing a semiconductor device according to claim 1, wherein a boundary between the selective oxide film and a portion where a diffusion layer is to be formed, which is at least near a corner of a well. Part, a mask film is formed, and the well and the mask film are used as a mask to lightly dope the surface part of the well with an impurity of a conductivity type opposite to that of the well, and then a sidewall is formed on the side surface of the mask film, and thereafter. , And the surface of the well is doped with an impurity having a conductivity type opposite to that of the well.
A method of manufacturing a semiconductor device according to a fifth aspect is the method of manufacturing a semiconductor device according to the fourth aspect, wherein the mask film is simultaneously formed of the same material as the gate electrode, and the sidewall of the mask film is the same material as the sidewall of the gate electrode. Is formed at the same time.

[0008]

According to the semiconductor device of the present invention, a diffusion region having the same conductivity type as that of the diffusion layer and a lower impurity concentration is provided outside the diffusion layer near the corner of the well. The low diffusion region weakens the electric field, which in turn reduces local avalanche breakdown. Therefore, it is possible to reduce the leak current, particularly, the leak current in the corner portion of the region surrounded by the selective oxide film.

According to the method of manufacturing a semiconductor device of the second aspect, the impurity is doped by masking at least the portion where the diffusion region having the low impurity concentration is to be formed after the light doping of the impurity using the selective oxide film as the mask. The leak current can be reduced by lowering the impurity concentration under the mask and weakening the electric field strength when a reverse bias voltage is applied between the well and the diffusion layer. According to the method of manufacturing a semiconductor device of claim 3, light doping of impurities is performed in the lightly doped drain forming step, and impurities are doped in the source and drain forming steps. Therefore, the manufacturing step of the MOS type semiconductor device having the LDD structure is performed. It is possible to reduce the leak current without increasing.

According to a fourth aspect of the method of manufacturing a semiconductor device, a mask film formed at a boundary between a selective oxide film and a portion where a diffusion layer is to be formed and at least near a corner of a well, and the selective oxidation. Lightly dope impurities with the film as a mask, and after forming sidewalls on the mask film and then dope impurities with the mask film having this sidewall as a mask, a diffusion region with a low impurity concentration is formed under the sidewalls. It can be formed as an intermediate between the diffusion layer and the well. According to the method of manufacturing a semiconductor device of claim 5, since the mask film is simultaneously formed of the same material as the gate electrode and the sidewall of the mask film is simultaneously formed of the same material as the sidewall of the gate electrode, the MOS having the LDD structure is formed. The leak current can be reduced without increasing the number of manufacturing steps of the semiconductor device.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention and its manufacturing method will be described in detail below with reference to the illustrated embodiments. 1 (A), (B)
Shows one embodiment of the semiconductor device of the present invention,
(A) is a plan view and (B) is an enlarged sectional view taken along the line BB of (A). In the drawings, 1 is an n-type semiconductor substrate, 2
Is a p-type well selectively formed on the surface of the semiconductor substrate 1, 3 is a selective oxide film formed by selective thermal oxidation of the surface of the semiconductor substrate 1, 3a is an inner surface of the selective oxide film 3, Reference numeral 4 is an n ⁺ type diffusion layer forming the source and drain of a MOS transistor, 5 is an n ⁻ type lightly doped region, 6 is a gate insulating film, 7 is a gate electrode made of polycide, 7a is a polycide wiring for cross check, and 8 Is a sidewall formed on the side surface of the gate electrode 7, 9 is an interlayer insulating film, and 10 is a contact region.

Reference numeral 5a denotes an n ⁻ -type diffusion region provided on the outer surface of the diffusion layer 4 at the four corners of the well 2 having a rectangular planar shape, which contributes to the reduction of leak current. That is, in the conventional case, since the n ⁻ -type diffusion region did not exist on the outer surface of the diffusion layer 4, the impurity concentration distribution profile of the junction between the diffusion layer 4 and the well 2 became steep. According to this, since the n ⁻ type diffusion region 5a is interposed between the diffusion layer 4 and the well 2, the diffusion layer 4
The steepness of the impurity concentration profile of the junction between the wells 2 disappears, the electric field concentration at the corners of the well 2 becomes weaker, and the local avalanche breakdown decreases, which reduces junction leakage, that is, leakage current. It gets smaller.

In the manufacture of such a semiconductor device (gate array), for example, the diffusion region 5a is formed by changing the mask pattern used in the ion implantation of n-type impurities for forming the source and the drain from the conventional one. The pattern should be such that the region to be masked can be masked. FIG. 2 is a plan view showing such a mask pattern, and 11 shows an impurity ion implantation mask (resist mask) for forming a source / drain. The masked area is the shaded area
Is. The element formation region not covered with the selective oxide film 3 (which substantially corresponds to the well) is rectangular, and the pattern of the mask 11 is basically formed so as not to cover the rectangular region. In order to form 5a near the corners of the well 2, the mask 11 is formed so as to cover the four corners of the rectangular region as shown in FIG.

FIGS. 3A and 3B are cross-sectional views showing, in the order of steps, an example of a semiconductor device manufacturing method for manufacturing the semiconductor device shown in FIG. 1 using such a mask. Figure 3 (A)
Shows the state when performing ion implantation to form a lightly doped drain. This ion implantation is performed in the same manner as the conventional one.

FIG. 3B shows a state when ion implantation for forming source / drain is performed. This ion implantation is performed by forming a resist mask 11 having a pattern covering a portion where the diffusion region 5a is to be formed. Then, impurities are ion-implanted in the step of forming the lightly doped drain, and the region covered with the resist mask 11 in this step becomes the n ⁻ type diffusion region 5a, which contributes to the reduction of the leak current. In FIG. 3B, the two-dot chain line shows the resist mask 11 in the conventional case. In this conventional case, the element forming region was not covered by the resist mask 11 at all, and therefore the outer surface of the diffusion layer 4 was formed. This means that the diffusion region 5a having a very low impurity concentration was not formed at all.

FIGS. 4A to 4C are cross-sectional views showing another example of the method of manufacturing a semiconductor device for manufacturing the semiconductor device shown in FIG. 1 in the order of steps. According to the method of manufacturing a semiconductor device of the present invention, the gate electrode 7 and the sidewalls 8 made of polycide as well as the dummy gate 7b and the sidewall 8b are made of the same material at an appropriate position (at least at the boundary between the selective oxide film 3 and the element formation region). It is formed in a corner portion and is used as a mask for forming the diffusion region 5a.

First, the dummy gate 7b is formed simultaneously with the gate electrode 7. FIG. 4A shows a state after the dummy gate 7b is formed. Then, as shown in FIG. 4B, ion implantation is performed to form a lightly doped drain using the gate electrode 7 as a mask. Reference numeral 5 is an n ⁻ -type diffusion region formed thereby. Then, the gate electrode 7
When the side wall 8 is formed on the side surface of, the side wall 8a is inevitably formed on the side surface of the dummy gate 7b. After that, in that state, as shown in FIG. 4C, ion implantation is performed to form a source and a drain. Then,
The n ⁻ type diffusion region 5a for reducing the leak current is formed in the portion of the dummy gate 7b masked by the sidewall 8a.

5A and 5B are plan views showing another example of the formation position of the dummy gate 7b (hatched portion) in the method of manufacturing the semiconductor device shown in FIG. Figure 5
In the example shown in (A), the dummy gates 7b are formed at the four corners of the well 2, and accordingly, the leak current reducing diffusion regions 5a are formed at those portions. In the example shown in FIG. 5B, the dummy gates 7b are formed on both side surfaces of the well 2, and accordingly, the leak current reducing diffusion region 5a is formed in that portion.

[0019]

The semiconductor device according to the present invention is characterized in that a diffusion region having the same conductivity type as that of the diffusion layer and a lower impurity concentration is provided outside the diffusion layer near the corner of the well. To do. Therefore, according to the semiconductor device of the first aspect, since the diffusion region having the same conductivity type as the diffusion layer and the impurity concentration lower than that of the diffusion layer is provided in the vicinity of the corner of the well, the impurity concentration is low. The diffusion region weakens the electric field, which in turn makes local avalanche breakdown less likely to occur. Therefore, it is possible to reduce the leak current, particularly, the leak current in the corner portion of the region surrounded by the selective oxide film.

According to a second aspect of the method of manufacturing a semiconductor device, the surface of the well is lightly doped with an impurity having a conductivity type opposite to that of the well by using the selective oxide film as a mask, and then a diffusion region having a low impurity concentration is to be formed. The surface of the well is doped with an impurity having a conductivity type opposite to that of the well in a state where at least is masked. Therefore, claim 2
According to the method of manufacturing a semiconductor device described above, after lightly doping the impurity with the selective oxide film as a mask, the impurity is doped by masking at least the portion where the diffusion region having a low impurity concentration is to be formed. It is possible to reduce the leak current by lowering the concentration and weakening the strength of the electric field when a reverse bias voltage is applied between the well and the diffusion layer.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises lightly doping impurities in a lightly doped drain forming step and doping impurities in a source and drain forming step. Therefore, according to the method of manufacturing a semiconductor device of claim 3, light doping of impurities is performed in the lightly doped drain forming step,
Since the impurities are doped in the source and drain forming steps, it is possible to reduce the leak current without increasing the number of manufacturing steps of the MOS semiconductor device having the LDD structure.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a mask film is formed at a boundary between a selective oxide film and a portion where a diffusion layer is to be formed, which is in the vicinity of at least a corner of a well.
Using the well and the mask film as a mask, the surface of the well is lightly doped with an impurity of the conductivity type opposite to that of the well, and then a sidewall is formed on the side surface of the mask film. The surface of the well is doped. Therefore, according to the method of manufacturing a semiconductor device of claim 4, the mask film formed at the boundary between the selective oxide film and the portion where the diffusion layer is to be formed and at least near the corner of the well and the selective oxide film are formed. Lightly doping an impurity as a mask, forming a sidewall on the mask film, and then doping the impurity with the mask film having this sidewall as a mask, a diffusion region having a low impurity concentration is formed under the sidewall as a diffusion layer. Can be formed as an intervening material between the well and the well.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, the mask film is formed simultaneously with the same material as the gate electrode, and the sidewall of the mask film is simultaneously formed with the same material as the side wall of the gate electrode. To do. Therefore, according to the semiconductor device manufacturing method of the fifth aspect, the mask film is simultaneously formed of the same material as the gate electrode, and the side wall of the mask film is simultaneously formed of the same material as the side wall of the gate electrode.
It is possible to reduce the leak current without increasing the number of manufacturing steps of the MOS semiconductor device having the D structure.

[Brief description of drawings]

1A and 1B show one embodiment of a semiconductor device of the present invention, FIG. 1A is a plan view, and FIG. 1B is an enlarged sectional view taken along line BB of FIG. is there.

FIG. 2 is a plan view showing a mask used for manufacturing the semiconductor device of FIG.

3A and 3B are cross-sectional views showing, in the order of steps, one embodiment of a method for manufacturing a semiconductor device of the present invention using the mask shown in FIG.

4A to 4C are cross-sectional views showing another embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps.

5A and 5B are plan views showing another example of dummy gate formation positions in the method of manufacturing the semiconductor device shown in FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 well 3 selective oxide film 4 diffusion layer 5a diffusion region with low impurity concentration

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 7514-4M H01L 29/78 301 L

Claims (5)

[Claims] 1. A selective oxide film is formed on a surface portion of a semiconductor substrate having a well, and a diffusion layer of a conductivity type opposite to that of the well is surrounded by the selective oxide film on a surface portion inside each well. In a semiconductor device, at least in the vicinity of a corner of a well, a diffusion region having the same conductivity type as that of the diffusion layer and a lower impurity concentration is provided outside the diffusion layer. 2. The surface of the well is lightly doped with an impurity having a conductivity type opposite to that of the well by using the selective oxide film as a mask, and thereafter, at least a portion where a diffusion region having a low impurity concentration is to be formed is masked. The method of manufacturing a semiconductor device according to claim 1, wherein the surface of the well is doped with a conductive impurity. 3. The method of manufacturing a semiconductor device according to claim 2, wherein light doping of impurities is performed in the lightly doped drain forming step, and impurities are doped in the source and drain forming steps. 4. A mask film is formed at a boundary between a selective oxide film and a portion where a diffusion layer is to be formed, which is near at least a corner of the well, and is opposite to the well using the selective oxide film and the mask film as a mask. Lightly doping a conductivity type impurity into the surface of the well, and then forming a sidewall on the side surface of the mask film, and then doping the surface of the well with a conductivity type opposite to that of the well. A method of manufacturing a semiconductor device for manufacturing the semiconductor device according to claim 1. 5. The semiconductor device according to claim 4, wherein the mask film is simultaneously formed of the same material as the gate electrode, and the sidewall of the mask film is simultaneously formed of the same material as the sidewall of the gate electrode. Production method