JPH0786456A - Semiconductor device and mounting board - Google Patents
Semiconductor device and mounting boardInfo
- Publication number
- JPH0786456A JPH0786456A JP5255178A JP25517893A JPH0786456A JP H0786456 A JPH0786456 A JP H0786456A JP 5255178 A JP5255178 A JP 5255178A JP 25517893 A JP25517893 A JP 25517893A JP H0786456 A JPH0786456 A JP H0786456A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- die stage
- recess
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、集積回路（ＩＣ）装
置等の半導体装置と、この装置を実装するための実装基
板とに関し、特に半導体装置のフラットパッケージの一
方の主表面にダイステージを露出させると共に実装基板
のパッケージ収納用凹部の底部に放熱板を設けたことに
より放熱性の向上を図ったものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an integrated circuit (IC) device and a mounting substrate for mounting the device, and more particularly to a die stage on one main surface of a flat package of the semiconductor device. It is intended to improve the heat dissipation by exposing the package and providing a heat dissipation plate on the bottom of the package housing recess of the mounting substrate.
【０００２】[0002]
【従来の技術】従来、表面実装型のＩＣ装置としては、
図５に示すようにフラットパッケージ１から導出したア
ウターリード２をＪ形に加工したもの、あるいは図６に
示すようにフラットパッケージ１から導出したアウター
リード２をガルウイング状に加工したものなどが知られ
ている。2. Description of the Related Art Conventionally, as a surface mount type IC device,
It is known that the outer lead 2 derived from the flat package 1 is processed into a J shape as shown in FIG. 5, or the outer lead 2 derived from the flat package 1 is processed into a gull wing shape as shown in FIG. ing.
【０００３】また、この種のＩＣ装置を実装するための
実装基板としては、図７に示すようにリードピッチに対
応して半田ランド３を設けたプリント配線基板４等が知
られている。As a mounting board for mounting this type of IC device, a printed wiring board 4 having solder lands 3 provided corresponding to the lead pitch as shown in FIG. 7 is known.
【０００４】図６のＩＣ装置を図７のプリント配線基板
４に実装する場合、チップマウンタによりＩＣ装置を基
板４上で半田ランド３に位置合せした後、接着剤５によ
り仮付けした状態で半田のリフロー処理を行なう。When the IC device of FIG. 6 is mounted on the printed wiring board 4 of FIG. 7, after the IC device is aligned with the solder land 3 on the substrate 4 by the chip mounter, the IC device of FIG. Reflow processing is performed.
【０００５】[0005]
【発明が解決しようとする課題】上記した従来技術によ
ると、リードをＪ形又はガルウイング状に加工する工程
が必要である。また、リードピッチが０．３［ｍｍ］以
下のＩＣ装置では、リード加工の後検査工程等でリード
変形が生ずるのを防ぐため、リードを保護する枠付けが
必要である。According to the above-mentioned prior art, it is necessary to process the leads into J-shape or gull-wing shape. Further, in an IC device having a lead pitch of 0.3 [mm] or less, it is necessary to provide a frame for protecting the leads in order to prevent deformation of the leads in an inspection process after the lead processing.
【０００６】リードピッチの小さいＩＣ装置では、リー
ド加工の際にリード先端の半田めっきが削られるため、
半田が供給不足になることがある。このための対策とし
て、リード加工後にリード先端に半田の厚めっきを施す
方法が提案されているが、この方法では、めっき処理に
伴ってリード変形が生ずることがある。In an IC device with a small lead pitch, the solder plating at the tip of the lead is scraped during lead processing,
The supply of solder may be insufficient. As a countermeasure for this, a method of applying thick solder plating to the tip of the lead after processing the lead has been proposed, but in this method, the lead may be deformed due to the plating treatment.
【０００７】その上、ＩＣチップを固着したダイステー
ジがパッケージ１の内部に封入されており、しかもパッ
ケージ１を基板４から離間した状態で実装するため、Ｉ
Ｃチップ内で発生した熱がパッケージ外に逃げにくく、
放熱性が良好でなかった。Moreover, since the die stage to which the IC chip is fixed is enclosed in the package 1, and the package 1 is mounted in a state of being separated from the substrate 4, I
The heat generated in the C chip does not easily escape to the outside of the package,
The heat dissipation was not good.
【０００８】この発明の目的は、リード加工を不要にす
ると共に放熱性の向上を図ることにある。An object of the present invention is to eliminate the need for lead processing and to improve heat dissipation.
【０００９】[0009]
【課題を解決するための手段】この発明に係る半導体装
置は、集積回路チップが一方の主表面に固着されたダイ
ステージと、このダイステージを前記集積回路チップと
共に収納するフラットパッケージと、前記集積回路チッ
プに接続されると共に前記フラットパッケージの側部か
ら外方に直線状に導出された多数のアウターリードとを
備えたものであって、前記ダイステージの他方の主表面
を前記フラットパッケージにおいて前記ＩＣチップ側と
は反対側の主表面に露出させたことを特徴とするもので
ある。A semiconductor device according to the present invention comprises a die stage having an integrated circuit chip fixed to one main surface thereof, a flat package for accommodating the die stage together with the integrated circuit chip, and the integrated package. A plurality of outer leads connected to a circuit chip and linearly extended outward from the side of the flat package, wherein the other main surface of the die stage is the flat package in the flat package. It is characterized in that it is exposed on the main surface opposite to the IC chip side.
【００１０】また、この発明に係る実装基板は、上記の
ような半導体装置を実装するためのものであって、前記
フラットパッケージを収納するための凹部を設けると共
に、この凹部の底部に前記ダイステージからの放熱を促
すための放熱板を設けたことを特徴とするものである。The mounting board according to the present invention is for mounting the semiconductor device as described above, and is provided with a recess for accommodating the flat package, and the die stage is provided at the bottom of the recess. It is characterized in that a heat dissipation plate is provided to promote heat dissipation from the.
【００１１】[0011]
【作用】この発明の半導体装置によれば、ＩＣチップの
内部で発生した熱は、ダイステージの露出部を介してパ
ッケージ外に放出される。According to the semiconductor device of the present invention, the heat generated inside the IC chip is radiated to the outside of the package through the exposed portion of the die stage.
【００１２】また、この発明の半導体装置をこの発明の
実装基板に実装するときは、ダイステージの露出部を放
熱板に重ねるようにしてパッケージを凹部に挿入すれば
よい。このようにすると、ダイステージの露出部からの
放熱が放熱板により促進される。また、凹部の深さを適
当に定めることによりリードを直線状にしたまま基板配
線に接続可能であるから、リード曲げ等の加工は不要と
なる。リード曲げが不要であるため、リード先端部に半
田の厚めっきを施すことが容易となる。When the semiconductor device of the present invention is mounted on the mounting board of the present invention, the package may be inserted into the recess so that the exposed portion of the die stage overlaps with the heat dissipation plate. With this configuration, the heat dissipation from the exposed portion of the die stage is promoted by the heat dissipation plate. Further, by appropriately setting the depth of the recess, it is possible to connect the leads to the wiring of the substrate while keeping the leads in a straight line, so that processing such as bending of the leads becomes unnecessary. Since lead bending is not necessary, it is easy to apply thick solder plating to the lead tips.
【００１３】[0013]
【実施例】図１，２は、この発明の一実施例に係る半導
体装置を示すものである。1 and 2 show a semiconductor device according to an embodiment of the present invention.
【００１４】図１，２において、方形状のダイステージ
１０の一方の主表面には、ＩＣチップ（半導体チップ）
１２が固着されている。ＩＣチップ１２の四辺に対応し
て多数のアウターリード１４が配置されており、各リー
ドはボンディングワイヤＷによりＩＣチップ１２上の電
極層に接続されている。ダイステージ１０の４つのコー
ナーからは、対角線に沿って位置決めピン１０Ａ〜１０
Ｄが突出している。In FIGS. 1 and 2, an IC chip (semiconductor chip) is provided on one main surface of the rectangular die stage 10.
12 is fixed. A large number of outer leads 14 are arranged corresponding to the four sides of the IC chip 12, and each lead is connected to an electrode layer on the IC chip 12 by a bonding wire W. From the four corners of the die stage 10, the positioning pins 10A to 10A are arranged along the diagonal line.
D is protruding.
【００１５】フラットパッケージ１６は、セラミック、
合成樹脂等の絶縁材からなる方形状のもので、ダイステ
ージ１０、ＩＣチップ１２、ボンディングワイヤＷ、リ
ード１４の接続部等を内蔵している。ダイステージ１０
の他方の主表面は、パッケージ１６の下側の主表面に露
出しており、それによって放熱性を高めるようになって
いる。The flat package 16 is made of ceramic,
It is a rectangular shape made of an insulating material such as a synthetic resin and has a built-in die stage 10, an IC chip 12, a bonding wire W, a connecting portion of the leads 14, and the like. Die stage 10
The other main surface of the is exposed at the lower main surface of the package 16, thereby enhancing heat dissipation.
【００１６】リード１４は、パッケージ１６の側部から
外方に直線状に導出され、位置決めピン１０Ａ〜１０Ｄ
は、パッケージ１６の４つのコーナーからそれぞれ導出
されている。位置決めピン１０Ａ〜１０Ｄをコーナーに
配置したので、検査や実装の際にリード１４の機能を妨
げることがない。The leads 14 are linearly led outward from the side portions of the package 16 and are positioned by the positioning pins 10A to 10D.
Are respectively derived from the four corners of the package 16. Since the positioning pins 10A to 10D are arranged at the corners, they do not interfere with the function of the lead 14 during inspection and mounting.
【００１７】位置決めピン１０Ａ〜１０Ｄを有するダイ
ステージ１０と、リード１４とは、リードフレームから
打抜加工により得られるもので、同一の材料からなって
いる。各リードには、図２に示すように直線状態にて半
田層Ｓを厚くめっきすることができる。The die stage 10 having the positioning pins 10A to 10D and the lead 14 are obtained by punching from a lead frame and are made of the same material. Each lead can be thickly plated with a solder layer S in a straight line as shown in FIG.
【００１８】図３，４は、上記した半導体装置を実装基
板に実装した状態を示すもので、図１，２と同様の部分
には同様の符号を付してある。FIGS. 3 and 4 show a state in which the above-described semiconductor device is mounted on a mounting board, and the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals.
【００１９】実装基板２０は、プリント配線基板又はマ
イクロモジュール基板等からなるもので、上記した半導
体装置のフラットパッケージ１６を収納するための方形
状の凹部２２が設けられると共に、凹部２２の４つのコ
ーナーにはパッケージ１６から突出した位置決めピン１
０Ａ〜１０Ｄをそれぞれ収納するための位置決め溝２２
Ａ〜２２Ｄが設けられている。The mounting board 20 is composed of a printed wiring board, a micromodule board, or the like, and is provided with rectangular recesses 22 for accommodating the flat package 16 of the semiconductor device, and four corners of the recesses 22. Positioning pin 1 protruding from the package 16
Positioning groove 22 for accommodating 0A to 10D, respectively
A to 22D are provided.
【００２０】凹部２２の底部には、Ｃｕ等からなる放熱
板２４が設けられており、それによって放熱性を高める
ようになっている。A heat radiating plate 24 made of Cu or the like is provided on the bottom of the recess 22 to enhance heat radiating property.
【００２１】半導体装置を実装基板に実装するときは、
位置決めピン１０Ａ〜１０Ｄを位置決め溝２２Ａ〜２２
Ｄに合わせるようにしてパッケージ１６を凹部に挿入す
る。そして、各リード１４を基板配線の半田ランドＳ1
に接続すると共に、ダイステージ１０の露出面を放熱板
２４の上面に半田層Ｓ2 で固着する。When mounting a semiconductor device on a mounting board,
The positioning pins 10A to 10D are positioned in the positioning grooves 22A to 22.
The package 16 is inserted into the recess so as to align with D. Then, each lead 14 is connected to the solder land S 1 of the board wiring.
And the exposed surface of the die stage 10 is fixed to the upper surface of the heat dissipation plate 24 with a solder layer S 2 .
【００２２】上記した実施例によれば、リード曲げ工程
が不要となり、検査等での取扱いも容易となり、リード
変形もなくなる。また、位置決めピンと位置決め溝との
嵌合により位置決めを行なうため、チップマウンタを用
いることなく簡単且つ正確に位置決めを行なうことがで
き、ランドずれの発生を防止することができる。さら
に、ダイステージ１０がパッケージ１６から露出してい
ると共に実装時には放熱板２４と熱的に結合させるよう
にしたので、放熱性が大幅に向上する。さらに、ダイス
テージ１０がパッケージ１６から露出していることは、
半田リフロー時のパッケージクラック防止にも有効であ
る。According to the above-described embodiment, the lead bending step is unnecessary, the handling for inspection and the like is easy, and the lead is not deformed. Further, since the positioning is performed by fitting the positioning pin and the positioning groove, it is possible to perform the positioning easily and accurately without using a chip mounter, and it is possible to prevent the land deviation. Further, since the die stage 10 is exposed from the package 16 and is thermally coupled to the heat dissipation plate 24 at the time of mounting, the heat dissipation is significantly improved. Furthermore, the fact that the die stage 10 is exposed from the package 16 means that
It is also effective in preventing package cracks during solder reflow.
【００２３】なお、この発明は、上記実施例に限定され
るものではなく、適宜の改変形態で実施可能なものであ
る。例えば、半田層Ｓ2 を省略し、ダイステージ１０を
直接的に放熱板２４に接触させるようにしてもよい。ま
た、位置決め用のピン又は溝の本数は、４本に限定され
ない。The present invention is not limited to the above-mentioned embodiments, but can be implemented in appropriate modified forms. For example, the solder layer S 2 may be omitted and the die stage 10 may be brought into direct contact with the heat dissipation plate 24. Further, the number of positioning pins or grooves is not limited to four.
【００２４】[0024]
【発明の効果】以上のように、この発明によれば、ダイ
ステージの一主表面をパッケージ外に露出したり、実装
基板のパッケージ収納用凹部の底部に放熱板を設けたり
して放熱性を高めるようにしたので、小型で電力性能の
高いＩＣ装置を実現可能となる効果が得られるものであ
る。As described above, according to the present invention, one main surface of the die stage is exposed to the outside of the package, and a heat radiating plate is provided at the bottom of the package accommodating recess of the mounting substrate to improve heat dissipation. Since the height is increased, it is possible to obtain the effect of realizing a small IC device having high power performance.
【図１】 この発明の一実施例に係る半導体装置を示す
上面図である。FIG. 1 is a top view showing a semiconductor device according to an embodiment of the present invention.
【図２】 図１のＡ−Ａ’線に沿う断面図である。FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG.
【図３】 図１の半導体装置を実装基板に実装した状態
を示す上面図である。FIG. 3 is a top view showing a state where the semiconductor device of FIG. 1 is mounted on a mounting board.
【図４】 図３のＢ−Ｂ’線に沿う断面図である。FIG. 4 is a cross-sectional view taken along the line B-B ′ of FIG.
【図５】 従来の半導体装置の一例を示す側面図であ
る。FIG. 5 is a side view showing an example of a conventional semiconductor device.
【図６】 従来の半導体装置の他の例を示す側面図であ
る。FIG. 6 is a side view showing another example of a conventional semiconductor device.
【図７】 図６の半導体装置を実装基板に実装した状態
を示す側面図である。FIG. 7 is a side view showing a state where the semiconductor device of FIG. 6 is mounted on a mounting board.
１０：ダイステージ、１０Ａ〜１０Ｄ：位置決めピン、
１２：ＩＣチップ、１４：アウターリード、１６：フラ
ットパッケージ、２０：実装基板、２２：パッケージ収
納用凹部、２２Ａ〜２２Ｄ：位置決め溝、２４：放熱
板。10: die stage, 10A to 10D: positioning pins,
12: IC chip, 14: outer lead, 16: flat package, 20: mounting substrate, 22: recess for storing package, 22A to 22D: positioning groove, 24: heat sink.
Claims (2)
れたダイステージと、このダイステージを前記集積回路
チップと共に収納するフラットパッケージと、前記集積
回路チップに接続されると共に前記フラットパッケージ
の側部から外方に直線状に導出された多数のアウターリ
ードとを備えた半導体装置であって、 前記ダイステージの他方の主表面を前記フラットパッケ
ージにおいて前記ＩＣチップ側とは反対側の主表面に露
出させたことを特徴とする半導体装置。1. A die stage having an integrated circuit chip fixed to one main surface, a flat package for accommodating the die stage together with the integrated circuit chip, and a side of the flat package connected to the integrated circuit chip. A semiconductor device having a plurality of outer leads linearly extended outward from the portion, wherein the other main surface of the die stage is provided on the main surface opposite to the IC chip side in the flat package. A semiconductor device characterized by being exposed.
めの実装基板であって、 前記フラットパッケージを収納するための凹部を設ける
と共に、この凹部の底部に前記ダイステージからの放熱
を促すための放熱板を設けたことを特徴とする実装基
板。2. A mounting board for mounting the semiconductor device according to claim 1, wherein a recess for accommodating the flat package is provided, and the bottom of the recess promotes heat dissipation from the die stage. A mounting board provided with the heat dissipation plate of.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25517893A JP3348485B2 (en) | 1993-09-17 | 1993-09-17 | Semiconductor devices and mounting boards |
| TW083108452A TW259892B (en) | 1993-09-17 | 1994-09-13 | |
| KR1019940023481A KR100200289B1 (en) | 1993-09-14 | 1994-09-16 | Self-positioning ic package and wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25517893A JP3348485B2 (en) | 1993-09-17 | 1993-09-17 | Semiconductor devices and mounting boards |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0786456A true JPH0786456A (en) | 1995-03-31 |
| JP3348485B2 JP3348485B2 (en) | 2002-11-20 |
Family
ID=17275127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25517893A Expired - Fee Related JP3348485B2 (en) | 1993-09-14 | 1993-09-17 | Semiconductor devices and mounting boards |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3348485B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0766506A2 (en) * | 1995-09-29 | 1997-04-02 | Allen-Bradley Company, Inc. | A multilayer circuit board having a window exposing an enhanced conductive layer for use as an insulated mounting area |
| WO2005083807A1 (en) * | 2004-02-27 | 2005-09-09 | Luxpia Co., Ltd. | A pcb-mounted radiator and an led package using the pcb, and the manufacturing method thereof |
| FR2959062A1 (en) * | 2010-04-15 | 2011-10-21 | Mitsubishi Electric Corp | SEMICONDUCTOR APPARATUS |
-
1993
- 1993-09-17 JP JP25517893A patent/JP3348485B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0766506A2 (en) * | 1995-09-29 | 1997-04-02 | Allen-Bradley Company, Inc. | A multilayer circuit board having a window exposing an enhanced conductive layer for use as an insulated mounting area |
| EP0766506A3 (en) * | 1995-09-29 | 1998-12-23 | Allen-Bradley Company, Inc. | A multilayer circuit board having a window exposing an enhanced conductive layer for use as an insulated mounting area |
| WO2005083807A1 (en) * | 2004-02-27 | 2005-09-09 | Luxpia Co., Ltd. | A pcb-mounted radiator and an led package using the pcb, and the manufacturing method thereof |
| FR2959062A1 (en) * | 2010-04-15 | 2011-10-21 | Mitsubishi Electric Corp | SEMICONDUCTOR APPARATUS |
| JP2011228335A (en) * | 2010-04-15 | 2011-11-10 | Mitsubishi Electric Corp | Semiconductor device |
| US9006879B2 (en) | 2010-04-15 | 2015-04-14 | Mitsubishi Electric Corporation | Semicondutor device package placed within fitting portion of wiring member and attached to heat sink |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3348485B2 (en) | 2002-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100246333B1 (en) | Ball grid array package and method for manufacturing thereof | |
| JPH04256343A (en) | Flip-chip package for integrated circuit use | |
| JPH0550134B2 (en) | ||
| JP2872825B2 (en) | Package for semiconductor device | |
| JPH07326644A (en) | Tape carrier and semiconductor device using the same | |
| JP3612155B2 (en) | Semiconductor device and lead frame for semiconductor device | |
| EP1460888A1 (en) | Low-profile electronic circuit module and method for manufacturing the same | |
| JPH0786456A (en) | Semiconductor device and mounting board | |
| US6444494B1 (en) | Process of packaging a semiconductor device with reinforced film substrate | |
| JPH0773122B2 (en) | Sealed semiconductor device | |
| JPH0786449A (en) | Semiconductor device and mount board | |
| JP2001237353A (en) | Heat radiating structure of electronic part and method of manufacturing electronic part | |
| JP2000164792A (en) | Semiconductor device and manufacture thereof | |
| JPS61137349A (en) | Semiconductor device | |
| JPH09312358A (en) | Ic package | |
| JPH11186479A (en) | Surface mounting parts with heat slinger | |
| JPH10154768A (en) | Semiconductor device and its manufacturing method | |
| JP3438125B2 (en) | BGA package mounting structure | |
| JP2004327912A (en) | Semiconductor package and semiconductor device | |
| JP2000031315A (en) | Bga package and its manufacture | |
| JPH10256421A (en) | Semiconductor device and mounting method thereof | |
| KR100200289B1 (en) | Self-positioning ic package and wiring board | |
| KR19980056452U (en) | Heat dissipation device for high micro integrated circuit | |
| JPS60138945A (en) | Sealed semiconductor device | |
| KR100209761B1 (en) | Ball grid array package and method for manufactring the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313532 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070913 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080913 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090913 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100913 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100913 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110913 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |