JPH0784917A - Method and circuit for final data supervisory control - Google Patents

Abstract

PURPOSE:To provide a method and circuit for final data supervisory control which can process codes corresponding to many kind of control data without increasing the device capacity or cost with regard to a method and a circuit for final data supervision for data transfer using a direct memory access controller. CONSTITUTION:The final data supervisory control method which outputs an interruption signal Sp for final processing to a CPU 1 and a DMAC 3 after receiving the specific number of control data added to the tail of transfer data stores a code showing the number of the control data to be received in a specific address of a data detection memory, and transfers this specific address in the control data at the time of transmission and also outputs the interruption signal Sp based on the code corresponding to an address read out of the data detection memory at the time of the reception.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a final data monitoring method and circuit for transfer data, and more particularly to a final data monitoring method and circuit for data transfer using a direct memory access controller.

[0002]

2. Description of the Related Art When transferring data from one device to another device, a communication modem is provided with a direct memory access controller (hereinafter referred to as a DMAC), and a CPU monitors only the start and end of communication. According to this method, the CPU is not blocked when transmitting / receiving data, and the load on the CPU is reduced.

FIG. 5 is a conceptual diagram of a conventional final data monitoring circuit using the above DMAC. The transferred data is input to the protocol controller 4, and the DMAC 3 is activated by the activation signal of the DMAC 3 mounted on the head of the transferred data. As a result, the DMAC 3 can access the memory 2 and the original transfer data extracted by the protocol controller 4 (the transfer data includes the original transfer data and data for defining the communication format). Is transferred to the memory 2 and written.

At the end of the transfer data, control data indicating the end of the transfer and, if necessary, some control data are added. Here, the control data means, in addition to the data indicating the end of the transfer as described above, data indicating the state (for example, normal or abnormal) of the transmission source device, or when there are a plurality of transmission source devices. Can be address data or the like that distinguishes the plurality of source devices. There are several possible combinations of the number and types of control data.
A final data processing circuit 10 corresponding to each of the plurality of combinations is provided, and each final data processing circuit 10 is provided.
Is assigned an address.

On the other hand, in each control data, an address designating each of the final data processing circuits 10 described above is provided.
When the same address as that of the control data is input to the final data processing circuit 10, an interrupt signal is generated at a predetermined timing as described below.

The final data processing circuit 10 comprises a data detection circuit 50 and a counter 60. The data detection circuit 50 further includes a monitor data setting device 59 and a comparator 5.
It consists of 8.

An address for specifying each final data processing circuit 10 is set in the monitor data setting unit 59 as described above, and the address is input to one terminal of the comparator 58.

On the other hand, transfer data is input to the other terminal of the comparator 58, and when an address matching the above address is included in the transfer data, the output becomes "1" and the counter 60 is operated. . The counter 60 counts the access timing signal St used when the DMAC 3 accesses the memory 2, and the count number corresponds to the number of the control data by the combination of the control data.

That is, when the transfer data includes only the control data C ₀ which means the end, the counter 60 is controlled by the access timing signal S as shown in FIG. 6I.
After counting t ₁₁ once, the interrupt signal Sp is immediately output.

Further, when the control data C ₀ indicating the end and the control data C ₁ indicating the normality or abnormality of the transmission source device are added, the counter 60 outputs the control data C ₀ as shown in FIG. 6 II. After the reception, the access timing signal is counted 2 times (S _t12 , S _t13 ) and then the interrupt signal Sp is generated. Further (not shown), if control data indicating normality / abnormality of the transmission source device and control data indicating the type of the transmission source device are added to the control data indicating termination, the counter 60 receives the final data. Then, the access timing signal generated later is counted to generate an interrupt signal.

As described above, transfer data between devices includes important data and much less important data. When there is an abnormality in the transfer source device, it is necessary for the important side of the transfer device to immediately deal with the abnormality. Therefore, it is necessary to transfer the control data indicating whether it is normal or abnormal after each transfer. There is.

However, for unimportant data, it suffices to perform termination processing after the data has been transferred a plurality of times. Therefore, the interrupt signal Sp can be generated after the control data indicating the end is input a specific number of times. That is, it is possible to specify the level of importance of data. For example, in FIG. 6 III, the interrupt signal Sp is output after the control data C ₀ indicating the end is input twice (after the access timing signal St is counted twice (S _t14, S _t15 )).

[0013]

When an abnormality occurs in the transfer source device in the conventional final data monitoring circuit 10 as described above, there is a demand for more accurately knowing which part of the transfer source device is abnormal. If so, it is necessary to have a large number of combinations of control data in order to distinguish the abnormal portion. Also, if the type of transfer source device increases, it is necessary to notify which part of which device is abnormal,
The number of combinations tends to increase. In addition, the number of combinations is further increased when it is desired to further level the importance of data.

However, since only one kind of combination can be set in the monitoring data setting means 59, the final data monitoring circuit 10 corresponding to each code is required when handling many kinds of combinations as described above, and the device The capacity or equipment cost will increase significantly.

The present invention has been proposed in view of the above conventional circumstances, and provides a final data monitoring control method and circuit capable of processing codes corresponding to various types of control data without increasing the device capacity or cost. That is the purpose.

[0016]

To achieve the above object, the present invention employs the following means. That is, in the final data monitoring control method of receiving the predetermined number of control data added to the end of the transfer data and then outputting the interrupt signal Sp for final processing to the CPU 1 and the DMAC 3, the control data to be received The code indicating the number of the data is stored in a predetermined address of the data detection memory 51, the predetermined address is transferred on the control data at the time of transmission, and the code corresponding to the address read from the data detection memory 51 at the time of reception. The interrupt signal Sp is output based on the above.

In order to realize the above method, the present invention is shown in FIG.
As shown in FIG. 5, the data detecting means 5 comprising a data detecting memory 51 containing a code representing the number of control data to be received corresponding to the address included in the control data.
When the control data is input, the interrupt signal generating means 6 for counting the number of control data represented by the code obtained from the data detection memory 51 and outputting the interrupt signal Sp at a necessary timing is provided. There is.

The above-mentioned control data number is the number of control data added to the end of each transfer of a plurality of data transfers, and may be a number for leveling the transfer data.

[0019]

Since the specific address of the data detection memory 51 is placed on the control data, when the control data is input, the code stored at the address can be read from the data detection memory 51. Since this code represents the timing (the number of access timing signals) from the input of the control data indicating the end to the generation of the interrupt signal, the interrupt signal generating means 6 reads the above code and accesses a predetermined number of times. After counting the number of timing signals, the interrupt signal Sp is created.
As a result, the DMAC 3 stops accessing the memory 2 and the CPU 1 recognizes that the data transfer is completed.

[0020]

FIG. 2 is a block diagram of an embodiment of the present invention.
The transmitted transfer data is the protocol controller 4
D that has been input to and is placed on the head of the transfer data.
The DMAC3 is activated by the activation signal of the MAC3. As a result, the DMAC 3 can access the memory 2 and the original transfer data extracted by the protocol controller 4 (the transfer data includes the original transfer data and data for defining the communication format). Is transferred to the memory 2 and written. The above basic points are the same as the conventional ones.

On the other hand, in the present invention, the transfer data is input to the data detection memory 51 provided in the data detection means 5. For example, as shown in FIG. 3, the data detection memory 51 is stored by being input from a setting means 52 such as a keyboard by coding the timing of generating an interrupt signal corresponding to each address A ₀ ... A ₇ .

Here, the codes stored in the addresses A _{0 to} A ₃ are used for leveling the importance of the data. For example, at address A ₀ = 2000, a code whose first bit is “1” is written. As a result, when the address "2000" is placed in the control data at the end of the transfer data, the code "00000001" is read from the data detection memory 51 and the counter CT ₀ constituting the interrupt signal generating means 6 is read. When the gate G ₀ provided on the input side of is turned on and the access timing signal St is input once from the DMAC 3, the counter C
The T ₀ (primary counter) immediately outputs the interrupt signal Sp (see FIG. 6I).

Address A₂= 2001 has the second bit
A code that is "1" is written. by this
The address "2001" is included in the control data.
Then, from the data detection memory 51,
Read out the counter CT₁(Binary counter)
Gate G provided on the input side₁Turns on. This game
G ₁Is turned on every time control data is input,
Data detection memory even if data other than control data is input
Since the code is not read from 51, it does not turn on.
Therefore, as shown in FIG.
Interrupt when access timing signal St is input
The signal Sp is generated. In this way, control data is sent n times
The configuration is such that the interrupt signal Sp is generated when input
The level of transfer data according to its importance.
You can

That is, since the example of the address A ₀ is very important data, the DMAC 3 and the CPU 1 perform the termination processing every time the control data indicating the termination is input.
If further necessary, control data indicating whether the transfer device is normal or not is added (this point will be described later), and it is checked whether or not the transfer source device is abnormal.

On the other hand, in the example in which the control data indicating the end is input a plurality of times n times and the interrupt signal is output, it can be applied to data transfer which is not so important as compared with the example of the address A _0. it can.

On the other hand, further to other control data, which means the completion to the end of the transfer data in the address A ₄ to A _7, houses a code when loaded with control data for the processing required CUP1 ing. For example, in FIG.
In this example, when the address A ₄ = 2004 is included in the control data, the code having the fifth bit “1” is read from the data detection memory 51, and the counter CT ₄ can be counted.

Here, the counter CT ₄ (binary counter)
Can output the interrupt signal Sp when the access timing signal St is input twice (see FIG. 6II). This not only causes the DMAC 3 and the CPU 1 to perform termination processing, but also stores control data for determining whether or not the source device is normal, or when there are a plurality of source devices, in the memory 2 You will be able to type in. Therefore, when the CPU 1 having received the interrupt signal Sp as described above subsequently issues a warning or the like when the control data indicating that the transmission source device has an abnormality is input to the memory 2.

Furthermore, the leveling of the transfer data and the interrupt control by continuous control data can be combined. That is, first the second bit is "1"
4 will be described by taking as an example the case of selecting a code having the following bits and then selecting a code having the fifth bit of "1".

Address A first₁= 2001 is entered,
Unta CT₁Can be counted. By doing this,
When the access timing signal St is input, the counter
CT ₁The interrupt signal is output from.

However, the second control data C₀₂For A
_Four= 2004 address is listed, so DMAC3?
From the second access timing signal St₂Is entered
Immediately before, the code whose fifth bit is "1" is the data detection
The counter CT read from the memory 51₁Counting
Disable and counter CT_FourCan be counted. This cow
Input CT_FourIs a binary counter, so access timing
Signal St₂, St ₃After counting, that is, the second time
Data Co that means the end of₂And indicates normal abnormality
Control data C₁Is input to memory 2 and then the interrupt
No. Sp will be generated.

A plurality of types of the code group shown in FIG. 3 can be prepared according to the originating system. For example, in the above example, the codes capable of leveling the data are stored in the addresses A _{0 to} A ₃ , but the leveling of the data is one type, and a plurality of pattern groups II, such as a code group in which many other control data are combined, III can also be prepared.

[0032]

As described above, the present invention is based on the DMAC and the CPU.
Since the generation timing of the interrupt signal when generating the interrupt signal for the end processing is patterned and stored in the memory, the address of the memory is placed in the control data of the transfer data. Since there is no need to provide a final data monitoring circuit, the volume and cost can be reduced, and various data can be monitored.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an example of the present invention.

FIG. 3 is a conceptual diagram showing a pattern stored in a data detection memory of the present invention.

FIG. 4 is a time chart showing an example of generating an interrupt signal according to the present invention.

FIG. 5 is a conceptual diagram of a conventional example.

FIG. 6 is a time chart of a conventional example.

[Explanation of symbols]

 1 CPU 3 Direct Memory Access Controller 5 Data Detecting Unit 6 Interrupt Signal Generating Unit 51 Data Detecting Memory Sp Interrupt Signal

Claims (3)

[Claims] 1. A CPU (1) and a direct memory access controller (hereinafter referred to as DMAC) (3) after receiving a predetermined number of control data added to the end of transfer data.
On the other hand, in the final data monitoring control method of outputting an interrupt signal (Sp) for final processing, a code representing the number of control data to be received is stored in a predetermined address of the data detection memory (51), At the time of transmission, the predetermined address is placed on control data and transferred, and at the time of reception, an interrupt signal (Sp) is output based on the code corresponding to the address read from the data detection memory (51). Data monitoring control method. 2. An interrupt signal for outputting an interrupt signal (Sp) for final processing to the CPU (1) and the DMA (3) after receiving a predetermined number of control data added to the end of transfer data. In the final data supervisory control circuit provided with the generation means (6), the data detection means provided with the data detection memory (51) storing the code representing the number of the control data to be received corresponding to the address carried in the control data. (5) When the above control data is input, the data detection memory (5
A final data monitoring control circuit comprising the interrupt signal generating means (6) for counting the number of control data represented by the code obtained from 1) and outputting an interrupt signal (Sp) at a necessary timing. 3. The final data according to claim 2, wherein the number of control data is the number of control data added to the end of each transfer of a plurality of data transfers, and is a number for leveling the transfer data. Supervisory control circuit.