JPH0783968A - Voltage detector - Google Patents

Abstract

PURPOSE:To provide a voltage detector in which a variation in a detected voltage is reduced in the detector which is used for a MOS semiconductor integrated circuit to detect a power source voltage and to output a detection signal responsive to the power source voltage. CONSTITUTION:The voltage detector generates a reference voltage (a) from a power source voltage Vdd by an N-channel MOSFETQN1 and a P-channel M0SFETQp1, detect a voltage (b) corresponding to the voltage Vdd by a P- channel MOSFETQP2 and an N-channel M0SFETQN2, and compares the voltage (a) with the voltage (b) by a comparator COMP1 to obtain a reset signal (c).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage detection circuit, and more particularly to a voltage detection circuit used in a MOS semiconductor integrated circuit for detecting a power supply voltage and outputting a detection signal according to the power supply voltage.

In a semiconductor integrated circuit or the like, the circuit generally malfunctions when the applied power supply voltage is lower than a predetermined level, so that it is configured to operate when the power supply voltage exceeds a predetermined level. Therefore, there is provided a voltage detection circuit that detects the power supply voltage, outputs a reset signal when the power supply voltage reaches a predetermined value, and resets the circuit to be operable.

However, in a MOS semiconductor integrated circuit or the like, the characteristics of the MOS transistors forming the integrated circuit fluctuate due to errors in manufacturing, the power supply voltage detection level fluctuates, and the power supply voltage detection level fluctuates. Therefore, it will not be reset at a predetermined voltage,
This has reduced the yield of MOS semiconductor integrated circuits.

Therefore, in order to improve the yield of the MOS semiconductor integrated circuit, it is necessary to reduce the fluctuation of the detection level.

[0005]

2. Description of the Related Art FIG. 6 is a circuit diagram showing an example of a conventional circuit.
In the figure, Q _N21 is an N-channel MOS transistor field effect transistor, Q _P21 is a P-channel MOS field effect transistor, R ₁ and R ₂ are resistors, and COMP ₂₁ is a comparator.

N-channel MOS field effect transistor Q
The gate and drain of _N21 are short-circuited, the power supply voltage Vdd is applied through the resistor R ₁ , and the source is at the low voltage level Vss.
(Ground level). The connection point between the N-channel MOS field effect transistor Q _N1 and the resistor R ₁ is a comparator C.
It is connected to the inverting input terminal of the OMP ₂₁ and supplies the reference voltage a.

P-channel MOS field effect transistor Q
_P21 gate - drain is shorted, the resistor R ₂
To the low voltage level Vss (ground level), and the power supply voltage Vdd is applied to the source. P channel MOS
Connection point of the field effect transistor Q _P21 and the resistor R ₂ is connected to the non-inverting input terminal of the comparator COMP _21, applies a detection voltage b to the comparator COMP _21.

The comparator COMP ₂₁ compares the reference voltage a with the detection voltage b, and outputs a reset signal c which becomes a high level when a <b and a low level when a> b.

FIG. 7 shows an operation explanatory view of a conventional example.

N-channel MOSFET Q _N21 and resistor R
_The signal a obtained by ₁ has a dependency on the power supply voltage as shown in FIG. That is, until the power supply voltage exceeds the threshold voltage of the N-channel MOSFET Q ₂₁ , the signal a
Is the same potential as the power supply voltage, and the power supply voltage is N-channel NO
When the threshold voltage of the SFETQ _N21 is exceeded, the signal a shows a change which is loosely dependent on the power supply voltage. P channel MOSFE
The signal b obtained by TQ _P21 and the resistor R ₂ has a dependency on the power supply voltage as shown in FIG. That is, the signal b is at the same potential as the ground voltage until the power supply voltage exceeds the threshold voltage of the P-type MOSFET Q _{P21, and} the signal b when the power supply voltage exceeds the threshold voltage of the P-channel MOSFET 4.
Indicates a change strongly dependent on the power supply voltage. Since the signals a and b have different dependences on the power supply voltage, the signals a and b have the same potential at a predetermined power supply voltage, and the output of the comparator COMP ₂₁ is different before and after this power supply voltage. That is, the reset signal is transmitted at this power supply voltage.

[0011]

However, in the conventional voltage detecting circuit of this type, if the characteristics of the MOS transistor fluctuate, the detected voltage fluctuates greatly. MO
The characteristic variation of the S transistor is caused by an error or the like in the manufacturing process. In the same manufacturing process, MOS transistors having the same conductivity type have substantially the same characteristics.
The MOS transistors of different conductivity types do not necessarily match. Therefore, for example, due to an error in the manufacturing process, N
If only the characteristics of the channel MOS field effect transistor Q _N21 change and the characteristics of the signal a change in the direction of arrow B, the detected voltage at the intersection of the signals a and b is indicated by arrow C.
There was a problem such as a large shift in the direction.

The present invention has been made in view of the above points, and an object of the present invention is to provide a voltage detection circuit in which fluctuations in the detection voltage are reduced.

[0013]

According to the present invention, in a voltage detection circuit for detecting a power supply voltage, comparing the detected power supply voltage level with a reference voltage by a comparator, and obtaining a detection signal, the power supply voltage is supplied to a plurality of MOS transistors. The MOS transistor includes a reference voltage generation unit that divides the power supply voltage by a transistor to generate the reference voltage, and a voltage detection unit that divides the power supply voltage by a plurality of MOS transistors to obtain a detection voltage according to the power supply voltage. Is arranged such that the difference between the reference voltage and the detected voltage is arranged irrespective of the variation of the characteristics of the MOS transistor.

[0014]

The reference voltage generating means and the voltage detecting means are composed of a plurality of Ms.
Since it is composed of OS transistors, these M
Due to the arrangement of the OS transistors, the difference between the reference voltage and the detection voltage can be made constant regardless of the mutual characteristic variations. Therefore, even if the characteristics of the MOS transistor change, it is possible to always detect with a constant power supply voltage.

[0015]

1 is a circuit diagram of a first embodiment of the present invention. In the figure, 1 is a reference voltage generation circuit and 2 is a voltage detection circuit. Further, Q _N1 and Q _N2 are N-channel MOS field effect transistors, Q _P1 and Q _P2 are P-channel MOS field effect transistors, and COMP ₁ is a comparator.

The reference voltage generation circuit 1 is an N-channel MOS transistor.
Field effect transistor Q_N1And P channel MOS field effect
Transistor Q_P1And obtain the reference voltage. N channel
MOS field effect transistor Q_N1Is the gate-drain
Is shorted and the source is at a low voltage level Vss (ground level)
It is said that N-channel MOS field effect transistor Q _N1
The gate-drain of is a P-channel MOS field effect transistor.
Dista Q_P1Connected to the drain of.

P-channel MOS field effect transistor Q
_The power supply voltage Vdd to be detected is applied to the drain of _P1 , and the gate has a constant low voltage level Vss (ground level).
It is said that N-channel MOS field effect transistor Q _N1
Functions as a constant voltage generating element, and the P-channel MOS field effect transistor Q _P1 operates linearly according to the applied voltage and functions as a resistance. The N-channel MOS field effect transistor Q _N1 and the P-channel MOS field effect transistor Q _P1 work as a reference voltage generating circuit.

The voltage detection circuit 2 comprises an N-channel MOS field effect transistor Q _N2 and a P-channel MOS field effect transistor Q _P2 , and obtains the voltage according to the power supply voltage Vdd. The source of the N-channel MOS field effect transistor Q _N2 is set to a constant low voltage level Vss (ground level),
The gate is set to the power supply voltage Vdd. The N-channel MOS field effect transistor Q _N2 operates linearly by the applied voltage and acts as a resistance.

P-channel MOS field effect transistor Q
_P2Drain-gate is short-circuited, drain-gate
Is an N-channel MOS field effect transistor Q_P2The dray
Power source voltage Vdd is applied to the source.
N-channel MOS field effect transistor Q_N2And P Cha
Channel MOS field effect transistor Q_P2By N channel
MOS field effect transistor Q_N2And P-channel MOS power
Field effect transistor Q _P2Depending on the power supply voltage Vdd
The same voltage is generated.

N-channel MOS field effect transistor Q
The connection point between _N1 and the P channel MOS field effect transistor Q _P1 is connected to the inverting input terminal of the comparator COMP ₁ , and the connection point between the N channel MOS field effect transistor Q _N2 and the P channel MOS field effect transistor Q _P2 is non-inverting. Connected to the input terminal.

FIG. 2 shows a circuit configuration diagram of the comparator of the first embodiment of the present invention. The comparator COMP ₁ is a current mirror circuit composed of P channel field effect transistors Q _P3 and Q _P4 , and an input N channel field effect transistor Q.
_{It comprises N3} , Q _N4 and an N-channel field effect transistor Q _N5 for supplying a constant current.

Comparator COMP₁Is N channel MO
S field effect transistor Q_N3The gate of the
P-channel MOS field effect transistor
Star Q_P1And N-channel MOS type field effect transistor Q
_N1And the signal a corresponding to the reference voltage is
N channel MOS field effect transistor Q supplied _N4
Gate becomes a non-inverting input terminal, and P gate is connected to this gate.
Channel MOS field effect transistor Q_P2And N channel MO
S field effect transistor Q_N2The connection point with
A signal b corresponding to the detection signal of the source voltage Vdd is supplied,
Depending on the difference between the signal d and the signal b, the high or low level is set.
Output signal c_OUTOutput more.

The signal c becomes low level when the level of the signal a is larger than the signal b (a> b), and becomes high level when the level of the signal a is smaller than the signal b (a <b).

In this embodiment, the N-channel MOSFET Q
_The signal a is connected to the gate of an N-channel MOSFET Q _N5 whose current source is _N5 . N-channel MOSFET Q _N5
By connecting the signal a to the gate of the N channel M
It is not necessary to add a bias voltage generating circuit for inputting to the gate of OSFETQ _N5 to this circuit.

FIG. 3 is a block diagram of a modification of the comparator according to the first embodiment of the present invention. In this modification, the comparator C
The OMP ₁ is composed of a P channel MOS field effect transistor Q _P5 for constant current supply, P channel MOS field effect transistors Q _P6 and Q _P7 for signal input, and N channel MOS field effect transistors Q _N6 and Q _N7 forming a current mirror circuit. I will do it.

In this modification, the gate of the P-channel MOS field effect transistor Q _P7 serves as an inverting input terminal to which the signal a is supplied, the gate of the P-channel MOS field effect transistor Q _{P6 serves as} a non-inverting input terminal, and the signal b corresponds to It is supplied, and the connection point between the P-channel MOS field effect transistor Q _P6 and the N-channel MOS field effect transistor Q _N6 becomes an output and the output terminal T _OUT is connected.

Therefore, the relationship of the output signal c with respect to the signals a and b is the same as that of FIG.

In this embodiment, P-channel MOSFET Q _P5
Is used as a current source, and the signal b is supplied to the gate of the P-channel MOSFET Q _P5 . P channel MOS
By connecting the signal b to the gate of FET Q _N5 , a stable voltage can be obtained and a P-channel MOSFET can be obtained.
It is not necessary to add a bias voltage generating circuit for inputting to the gate of _QP5 to this circuit.

FIG. 4 shows an operation explanatory diagram of the first embodiment of the present invention. In the figure, the solid line shows the standard time, and the broken line shows the variable time.

The dependence of the signals a and b on the power supply voltage is almost the same as in the conventional example.

When the characteristics of the N-channel MOSFETs Q _N1 and Q _N2 deviate from the standard in the arrow A direction, the signal a shifts as shown by the broken line and the signal b also shifts as shown by the broken line in the arrow c direction. Therefore, even if the characteristics of the N-channel MOSFETs Q _N1 and Q _N2 deviate from the standard, the change in the intersection of the signals a and b is small. That is, the change in the power supply voltage generated by the reset signal can be reduced. N-channel MOSFET Q _N1 , Q
_When the characteristics of _N2 are deviated in the opposite direction, and P-channel MOSF
The same applies when the characteristics of ETQ _P1 and Q _P2 deviate from the standard. The change in the power supply voltage generated by the reset signal with respect to the deviation of the characteristics of the MOSFET from the standard can be adjusted by adjusting the size of the MOSFET. Therefore, M
Even if the characteristics of the OSFET are changed for each chip or wafer, the reset can be applied with the same voltage.

FIG. 5 shows a circuit configuration diagram of the second embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the reference voltage circuit 3 in which the N-channel field effect transistor Q _N1 of the first embodiment is a P-channel CMOS field effect transistor Q _P11 and the P-channel field effect transistor Q _P1 is an N-channel MOS field effect transistor. It is composed of a voltage detection circuit 4 composed of Q _N11 .

P-channel MOS field effect transistor Q
_The gate and drain of _P11 are connected, the gate and drain are connected to the low voltage level Vss (ground level), and the source is connected to the drain of the P channel MOS field effect transistor _QP1 .

The gate-drain of the N-channel MOS field effect transistor Q _N11 is short-circuited, the gate-drain is connected to the power supply voltage Vdd side, and the source is connected to the drain of the N-channel MOS field effect transistor Q _N2 .

Therefore, the P-channel MOS field effect transistor Q _P11 operates similarly to the N-channel MOS field effect transistor Q _N1 of the first embodiment, and the P-channel MOS field effect transistor Q _P1 and the P-channel MOS field effect transistor Q _P11. Signal a which becomes the reference voltage from the connection point with
Is obtained.

Further, the N-channel MOS field effect transistor Q _N11 has the same function as the P-channel MOS field effect transistor Q _P2 of the first embodiment, and the N-channel MOS field effect transistor Q N2 has the same function.
A signal b for detecting the power supply voltage Vdd is obtained from the connection point between the field effect transistor Q _N2 and the N channel MOS field effect transistor Q _N2 .

In this embodiment, the dependence of the signals a and b on the power supply voltage is almost the same as in the conventional example. However, since the characteristic change of the P-type MOSFET Q _P11 suppresses the influence of the characteristic change of the P-channel MOSFET Q _{P1 on} the signal a, the change of the signal a due to the characteristic change of the P-channel MOSFET can be reduced. Similarly, N-channel MOSF
The effect on the signal b due to the characteristic change of ETQ _N2 is shown in N-type MOS.
Since the characteristic change of the FETs Q _N11 is suppressed, N-channel MO
The change in the signal b due to the change in the characteristics of the SFET can be reduced. Therefore, the power supply voltage generated by the reset signal does not greatly change due to the characteristic changes of the P-channel MOSFET and the N-channel MOSFET.

Therefore, the reset signal can be output with a constant power supply voltage without affecting the characteristic variation of the transistor that occurs for each chip or wafer. Therefore, it is not necessary to adjust the detection voltage of each chip.

[0040]

As described above, according to the present invention, variations in the detected voltage of the power source voltage can be reduced even if the characteristics of the transistors that are configured vary, so that it is not necessary to adjust the detection voltage for each chip and the yield is improved. It has the feature that it can be done.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a comparator according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a modification of the comparator according to the first embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional example.

FIG. 7 is a diagram illustrating an operation of a conventional example.

[Explanation of symbols]

Q _{P1 to} Q _P7 , Q _P11 P channel MOS field effect transistor Q _{N1 to} Q _N7 , Q _N11 N channel MOS field effect transistor COMP ₁ comparator

Claims (5)

[Claims] 1. A comparator (COM) for detecting a power supply voltage.
In the voltage detection circuit for comparing the difference between the detected power supply voltage and the reference voltage by P ₁ ) and obtaining an output according to the comparison result, a plurality of MOS transistors (Q _N1 , Q _P1 ; Q _P1 ,
Q _P11 ), and the power supply voltage (V _P ) by the plurality of MOS transistors (Q _N1 , Q _P1 ; Q _P1 , Q _P11 ).
dd) is divided to generate a reference voltage (a), and a plurality of MOS transistors (Q _N2 , Q _P2 ; Q _N2 , Q _N2 ,
Q _N11 ), and the power supply voltage (V) is _generated by the plurality of MOS transistors (Q _N2 , Q _P2 ; Q _N2 , Q _N11 ).
voltage detection means (2, 4) that obtains the detection voltage (b) by dividing dd), and constitutes the reference voltage generation means (1, 3) and the voltage detection means (2, 4). The plurality of MOS transistors (Q _N1 , Q _N2 , Q _P1 , Q _P2 ; Q _N2 , Q _P1 , Q _N11 , Q
_P11 ) has a difference between the reference voltage (a) and the detection voltage (b) from the plurality of MOS transistors (Q _N1 , Q _N2 ,
Q _P1 , Q _P2 ; Q _N2 , Q _P1 , Q _N11 , Q _P11 ) are arranged so as to be constant regardless of the characteristic variation. 2. The reference voltage generating means (1) is connected on a low voltage side, and is connected to a high voltage side with an N-channel MOS transistor (Q _N1 ) having a gate and a drain short-circuited.
P-channel M biased to operate in the linear region
And an OS transistor (Q _P1 ) connected in series,
Channel MOS transistor (Q _N1 ) and the P channel M
The reference voltage (a) is obtained from the connection point with the OS transistor (Q _P1 ), the voltage detecting means (2) is connected to the low voltage side, and the N channel is biased to operate in the linear region. A MOS transistor (Q _N2 ) and a P-channel MOS transistor (Q _P2 ) which is connected to the high voltage side and whose gate and drain are short-circuited are connected in series, and the N-channel MOS transistor (Q _N2 ) and the P-channel MOS transistor (Q _N2 ) are connected. 2. The voltage detection circuit according to claim 1, wherein the detection voltage (b) is obtained from a connection point with a channel MOS transistor (Q _P2 ). 3. The P-channel MOS transistor (Q _P1 ) connected to the low voltage side and having a shorted gate and drain, and the applied voltage connected to the high voltage side, said reference voltage generating means (3). P biased for linear operation
A channel MOS transistor (Q _P11 ) is connected in series, and the reference voltage (a) is obtained from a connection point between the P channel MOS transistor (Q _P1 ) and the P channel MOS transistor (Q _P11 ). The voltage detecting means (4) is connected to the N-channel MOS transistor (Q _N2 ) biased to the low voltage side so as to linearly operate with respect to the applied voltage, and connected to the high voltage side, and the gate and the drain are short-circuited. And an N channel MOS transistor (Q _N11 ) connected in series.
2. The voltage detection circuit according to claim 1, wherein the detection voltage (b) is obtained from a connection point between the transistor (Q _N2 ) and the N-channel MOS transistor (Q _N11 ). 4. The comparator (COMP ₁ ) has a current supply MOS transistor (Q _N5 ) for supplying an operating current, and the constant current supply MOS transistor (Q _N5 ) is the reference voltage generating means (1). 4. The voltage detection circuit according to claim 1, wherein the voltage detection circuit is biased by the reference voltage (a) generated in (3). 5. The comparator (COMP ₁ ) has a current supply MOS transistor (Q _P5 ) for supplying an operating current, and the current supply MOS transistor (Q _P5 ) is the voltage detection means (2, 4). 4. The voltage detection circuit according to claim 1, wherein the voltage detection circuit is biased by the detection voltage generated in the above item.