JPH0782998B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device. More particularly, it relates to improved photovoltaic junctions, rectifying junctions and image forming devices.

Hydrogenated amorphous silicon thin film (hereinafter a-
Si: H) is applied to semiconductor devices and has been manufactured by various techniques. Journal of Electrochemical Society (Jour
nal of Electro-chemical Society) 116th volume 1 (196
Chitick, Alexand in a paper entitled "Manufacturing and Properties of Amorphous Silicon" on pages 77-81 (Jan. 1997).
er and Sterling are able to dope both donor and acceptor impurities by inductively coupled RF glow discharge in silane (SiH ₄ ) gas, which results in a wide range of conductivity of a-Si: H. It has been reported that a low conductivity a-Si: H capable of changing the temperature was produced. Recently, a-
Si: H was produced by vapor deposition of silicon in a H ₂ + Ar atmosphere. This thin film exhibits semiconductor properties similar to a-Si: H made from silane in glow discharge.

Originally, a-Si: H was synthesized by glow discharge in SiF ₄ and H ₂ . This method was developed under the guidance of the present inventor and is described in British Patent No. 933,545 (issued August 8, 1936). The excellent dielectric properties and high resistance of a-Si: H are tabulated on page 4 of the above patent specification.
The high resistance a-Si: H is particularly suitable as a component of the connections described herein.

U.S. Pat. No. 4,064,521 describes a photovoltaic junction consisting of P-type, N-type and intrinsic a-Si: H deposited by glow discharge. In the patent, Chittick
The gaseous dopants, diboron and phosphine, mixed with silane, shown in the above-mentioned papers, have a volume ratio of 1/2 to
5% used.

Similarly, British Patent No. 2,018,446 (issued October 17, 1979) describes various image-forming devices having a joint consisting of two a-Si: H layers of different conductivity types. There is. Protective and blocking layers for a-Si: H are also described.

Also, Applied Physics Letters, Vol. 35, Vol. 4 (August 1979)
15th March), pages 349-351, entitled "Photoconductive Images Using Amorphous Silicon Thin Films," Y. Im.
A vidicon image forming apparatus made of sputtered a-Si: H is described by Amura et al.

Finally, in the field of semiconductors, it is well established to implant boron ions accelerated at high velocities into silicon wafers as dopants. The dopant ions are implanted in the crystal-silicon by a corona discharge. This method is described by Wichner and Charlson's Jou
Volume 5 of rnal of Electronic Materials (1976)
513-529, entitled "Silicon Solar Cells Made by Corona Discharge". What is important here is that, as described on page 518, the discharge must be kept in a corona state so that the voltage between the electrodes can be maintained at several kilovolts. Moreover, in order to obtain a sufficient implantation depth (range), a plurality of charged ionic species of high energy are required. Glow discharge is therefore specifically excluded because the voltage and boron ion energy are not sufficient to obtain a useful implant depth, and therefore the energy of the ions is too low.

That is, the present invention relates to a semiconductor device in which a semiconductor junction is provided between a substrate containing boron and a substrate of amorphous silicon, in which diffusion of boron is restricted. The electromagnetic wave referred to in the present invention is a wavelength that can normally operate this type of semiconductor device, and specifically includes sun rays, X-rays, and the like, and a wavelength longer than far infrared rays is usually used. Absent.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of a glow discharge device for producing an intrinsic semiconductor (I-type), P-type and N-type a-Si: H coating on a metal surface M. A typical PIN / M photovoltaic device made using the device of FIG. 1 is shown in FIG. Substrate 1 is 0.01 inch thick stainless steel 11 having a 3 inch by 4 inch square surface supported by electrodes 2. The resistance heater 3 is embedded in a ceramic block 3a for supporting and heating the electrode 2 and the substrate 11. The substrate 11 is mounted in a concave counter electrode 4 having a 4 inch by 5 inch square cross section defined by sidewalls 8 and top 9. The top 9 is located approximately 4 1/2 inches above the top surface of the substrate 11. Electrodes 1 and 4 are
It is installed inside an enclosure 6 sealed to a pedestal 12 by a gasket to form a gas seal. A vacuum pump 20 is connected to the pedestal 12 by a valve and nipple 13 to bring the enclosure 6 to a vacuum. Tanks 17a-17e
The gas G from 1 is directed to the enclosure 6 via the pedestal 12 by the control needle valves 16a-16e, the manifold 15 and the connector 14. Here, the gas G is guided by the insulator tube 5 and the diffuser 7 inside the electrode 4 . A gap 118 of, for example, 1/4 inch between the side wall 8 and the electrode 2 becomes an outlet of the gas G after passing through the glow discharge plasma P. Instrument
VG measures the pressure of the gas G in the enclosure 6, but
For use with corrosive and compressible gases in the range of 001-10 torr, the commercially available capacitance-manometer type is preferred. The signal from meter VG automatically adjusts valve 16 by a servo mechanism to maintain the desired pressure. A voltage V is applied between the electrodes 2 and 4 from a power supply 24 by means of conductors 21, 22 connected via insulated electrical bushings 18, 19 embedded in the pedestal 12. Protection resistor 23
Protects against damage from spark currents. Voltage V and current I are measured as shown. The resistance heater 3 is connected to a control power source (not shown) via a lead wire 45 and an insulating bushing 45 '.

In operation, the enclosure 6 is pumped down to a pressure below 0.02 torr and the heater 3 moves the substrate 11 to 18
Hold at 0-400 ° C. Then, by opening the valve 16a, the tank is filled with silane (SiH ₄ ).
The valve 16a is adjusted to maintain the desired pressure in the enclosure 6 (eg 0.5 torr). Then tank 1
The mixture of helium containing 1% of phosphine (PH ₃ ) from 7b enters the silane-mixed manifold 15 and raises the pressure PG of the device to about 1-2 torr and through the insulator tube 5 and the diffuser 7. Flowing. The electrodes 2 and 4 are the cathode and the anode, the potential difference V between the electrodes 2 and 4 is adjusted to about 200-500 volts which initiates the glow discharge, and the current I is the glow discharge on the substrate 11. Adjusted to about 5 mA to provide plasma P position. Substrate 11
A uniform, heavily doped N ohmic layer 32 is created on top. (Fig. 2) After maintaining the discharge for about 2 minutes, the valve 16b is closed to stop the flow of PH ₃ and helium, leaving only silane.

Since the uniformity and the impurity concentration of the N-type ohmic layer 32 are not as important as the uniformity and the impurity concentration of the intrinsic semiconductor (I) a-Si: H layer 10, the ohmic layer 32 is heated without glow discharge. It may be deposited by a physical treatment. For example, a conventional helium carrier gas PH ₃ / SiH ₄ filled chemical vapor deposition (CVD) apparatus was used to deposit the N-type layer 32 prior to loading the substrate into the apparatus of FIG. It doesn't matter. However, it is important to keep the CVD temperature low so that the polycrystals are formed on a macro scale and, due to their surface roughness, do not damage the next deposited a-Si: H layer.

Subsequently, the temperature of the substrate 11 is kept at 180-410 ° C. by the heater 3 in order to form the I-type a-Si: H layer 10 on the top surface of the N layer. And the pressure PG of only silane is 0.1 to 0.4 torr
Is adjusted to. If helium is used as the carrier gas, the pressure PG will be adjusted to about 2 torr. High voltage V is P
Depending on G, regulated to 500-1500 volts. Further, the current I is adjusted to about 5 mA, discharge is started in the strong electric field region Es of the gap G ′ between the electrodes 2 and 4, and the diffusion plasma P is generated in the weak electric field region Ew close to the substrate 11. It is placed, thereby minimizing the potential for sparking on substrate 11. The discharge is continued for about 40 minutes, producing an a-Si: H layer 10 of about 1 micron. Longer discharge times, higher currents or the use of disilane can increase the thickness of layer 10. Once layer 10 has the desired thickness, voltage V
, Valve 16a closed and residual gas pumped 2
Eliminate with 0.

In succession, a P-type layer 30 of hydrogenated amorphous boron (a-B: H) was formed on the top surface of the I-type a-Si: H layer 10 by diborane in order to complete the formation of the M / NIP junction. It is deposited by introducing (B ₂ H ₆ ) and helium into the plasma P. First, the valve 16c is opened, B ₂ H ₆ / He gas is introduced until the pressure PG reaches 1-2 torr, and the temperature of the substrate 11 is maintained at 180-410 ° C as in the formation of the layers 10 and 30. To be done. The voltage V is adjusted to 200-500 volts in order to place the glow discharge plasma P in the weak electric field Ew on the substrate 11. The current is maintained at about 5 mA for 2 minutes so that the thickness of the aB: H layer is 100Å. The temperature of the substrate 11 is maintained at 180 to 410 ° C., which is the same as the temperature at which the a-Si: H layer was deposited. Then, valve 16
c is closed and valve 16d is opened and nitrogen gas is introduced to remove residual diborane from enclosure 6. The current to the heater 3 is cut off, and after cooling for 1 hour, the enclosure 6 is returned to atmospheric pressure, and the substrate 11 is taken out.

To complete the formation of the M / NIP photovoltaic device, a semi-transparent metal layer 34, for example 100 liters of Pb, Cr-Cu or Ni-Cr alloy, is thermally deposited on the a-B: H layer. Contact fingers 35 are thermally vacuum deposited onto the semitransparent layer 34 for electrical contact. Ti for use as a photodiode or solar cell
Anti-reflection (AR) coating like O ₂ or SnO ₂ ,
A conducting metallization (CMO) such as indium and tin oxide (ITO) or zinc oxide is deposited on the metal layer 34.

After the deposition process described above was performed, the electrical properties of M / NIP cells were tested with various light sources. The result of measuring the short circuit current Isc of a typical battery by irradiation of AM1 sunlight is 4 mA / c
It was m ² . The open circuit voltage Voc was 0.45 V using the Cr / Ni forcing semi-transparent electrode 34. This electrode only passed about 30% of the incident photon flux, so if sufficient AM1
If irradiation was utilized without loss due to electrode absorption and reflection, the calculated value would be 4 / 0.3, or 13.3 mA / cm ² .

This current value is almost the same as the best value reported in the literature when a similar correction was made for the loss of the electrodes. Also, the measured Voc is equivalent to the value when the same low work function electrode is used.

A second M / NIP battery was then made in the same process using the apparatus of Figure 1 as described above. However, heater 3
Is a-B: H at a temperature lower than the deposition temperature of the a-Si: H layer 10.
After depositing the Type I a-Si: H layer 10 to deposit layer 30, it was turned off. The temperature of the electrode 11 and consequently the a-Si: H layer 10 decreases from 200-300 ° C to about 100 ° C in about 1 hour. Thereafter, the aB: H layer 30 is deposited on the layer 10 by glow discharge for about 2 minutes under the same conditions as the manufacturing conditions of the first battery described above except that the temperature is low. After removing the diborane gas, the substrate 11 was taken out from the enclosure 6 without further cooling, and as shown in FIG.
Test the photovoltaic properties after adding 34.

In addition, in order to form a photovoltaic solar cell, the semi-transparent metal coating 34 and the contact finger 35 are thermally treated on the aB; H layer 30 in the same vacuum deposition system as the first M / NIP cell. Vapor deposition. A second completed M / NIP cell was then tested under solar radiation both with and without the AR coating 36. AM1 using solar photon flux, A
In the test without R coating 36, Voc was 0.65 V and current was 4 mA / cm ² . Therefore, when the a-B: H layer 34 is deposited at a low temperature, Voc does not decrease the temperature of the substrate 11
An increase of about 0.2 volt compared to the first M / NIP cell with -B: H deposited.

The increase in the open-circuit voltage Voc obtained by the present invention cannot be theoretically explained at this point, but since the temperature of the substrate 11 is low,
It seems that the damage due to the impact when the a-B: H layer 30 is deposited on the surface of the I-type a-Si: H layer 10 is slight. The aB: H layer 30 appears to be a P-type semiconductor when deposited on a low temperature substrate. A P-N heterojunction is then formed for the undoped I-type a-Si: H layer 10, which is slightly N-type as deposited. I-type a-Si: H layer 10 and a-B: H layer 30
The top surface of the a-Si: H layer 10 is most important because a depletion region is formed from the boundary surface of the a-Si: H layer 10 toward the I-type a-Si: H layer 10.

To investigate the diffusion amount of boron in the first M / NIP battery,
The composition was analyzed by mass spectrometry.

FIG. 4 shows the commonly used second ion mass spectrometric analysis of the boron / silicon ratio at the interface between the a-B: H layer 30 and the a-Si: H layer 10 deposited by glow discharge at 300 ° C. The result of the analysis by the instrument is shown. As is clear from the figure, B
^{The 11} / Si ²⁸ isotope ratio drops sharply at about 100Å, then
It gradually decreases up to 500Å, and eventually becomes background noise. The first 100Å seems to represent a-B: H with interdiffusion of silicon, while up to 500Å seems to show the diffusion gradient of boron in silicon. However, this diffusion is greater than would be expected from previously published boron diffusion data in the absence of glow discharge. Some implantation of boron-containing ions in the glow discharge will also occur, and SiB ₆ alloys may also form.

However, the a-B: H layer 30 is deposited at low temperature and the a-Si: H
When the diffusion of boron into layer 10 is suppressed, Voc is predicted from the results of conventional semiconductor technologies, ie, PN junctions made by the diffusion of boron dopants by thermal treatment into crystalline silicon. It is inconsistent with things. a-B: H thin film 10 180
There appears to be no data relating to the semiconductor properties of a-B: H thin films deposited at low temperatures, since the a-B: H thin films damage other surfaces when deposited by thermal treatment below C.

In FIG. 3, an a-B: H layer 40 is first deposited on a 0.010 inch stainless steel substrate 11 and then an I-type a-S.
An i: H layer 43 and an N-type a-Si: H layer 42 are deposited to show the M / PIN photovoltaic connector device. The P-type, I-type and N-type layers 40, 43, 42 under the same process conditions used by the glow discharge deposition system described with reference to FIG. 1 to make M / NIP connections.
The glow discharge deposition system described with respect to FIG. 2 can also be used with the deposition order reversed. Upon cooling, the M / PIN cell is removed from the deposition system and tested in the imager described below with respect to FIG. 7 and as a photovoltaic device.

An electrode 44 may be added to provide electrical contact to the N-type layer 42 to form a photovoltaic device.

In the M / NIP battery of FIG. 2, a 100 Å Cr / Cu or Ni-Cr alloy semi-transparent layer 44 is thermally deposited on the N-type a-Si: H layer 42. The electrode 44 of the battery shown in FIG. 3 is an N-type aS
Cr: A to generate a very high Voc for the i: H layer 42
It is deposited similarly to the M / NIP battery of FIG. 2 except that it is preferably made of a low work function metal such as l, Ti.

An AR coating 46, preferably of a conductive metal oxide such as tin oxide or zinc oxide, is deposited on the electrode 44 by standard techniques and a Ti-Ag contact finger is added by conventional methods. .

In the test without the AR coating 46, the Isc of the M / PIN cell was 4 mA / cm ² when the aB: H layer 40 was deposited on the stainless steel substrate 11. The light transmission of the 100 Å Cr / Ni translucent top electrode is about 30%, so the internal Isc is about 13.3 mA / cm ² which is almost the same as that of the M / PIN battery shown in FIG. However, the measured Voc is 0.79 V, which is a large value even when the aB: H layer 30 is deposited at a low temperature like the M / PIN battery shown in FIG. Solar Energy Volume 23 145-147
Page (1979), "Amorphous Silicon Single Solar Panel", reported by Hanak that the Voc of the Pt electrode in contact with the P-type a-Si: H was 0.75 volts.
The Voc of the present invention is equal to or higher than the Voc 0.75 volts reported by Hanak. Pt is expensive and fairly inaccessible, but stainless steel is cheap and plentiful. Although expensive metals are a satisfactory material cost for small electronic devices, they are not suitable when used for large area solar energy conversion systems, as the cost is considerable.

The deposition conditions include raising the temperature of the substrate 11 to facilitate the deposition of the a-B: H layer 40, and then lowering the temperature to produce an I-type a-S.
The i: H layer 43 may be deposited at 180-410 ° C. For example, a
-The B: H layer 40 is deposited by a normal CVD apparatus while maintaining the temperature of the substrate at 300 to 600 ° C in the presence of B ₂ H ₆ / He, and after cooling, transferred to the glow discharge apparatus shown in Fig. 1. Good. Also, if the CVD temperature is below the temperature at which polycrystal formation and roughening of the surface occur, the mixture of B ₂ H ₆ / SiH ₄ is made of stainless steel.
It may be used to CVD process the layer 40 on the steel substrate 11 at temperatures of approximately 600 ° C. or higher. B / Si ratio is
It is preferably 0.01 or more.

Other suitable layer 40 on the substrate 11, butadiene and B ₂ hydrogenated amorphous carbon, boron deposited by glow discharge using a mixture has been doped H ₆ a-C in the apparatus of FIG. 1: H There are layers. In any case, the boron-doped layer 40 may be of any desired thickness from physical and electrical considerations as light will enter through the N-type layer 42. However, a-
When the B: H layer 40 is deposited by glow discharge, a thickness of 500 Å or more is not preferable because it adds series resistance and peels off from the stainless steel substrate 11. P, I in production
And the deposition of N-layers 40, 43, 42 is preferably performed in-line by moving substrate 11 through a series of deposition chambers with programmed temperature, pressure and gas composition.

In addition, the I-type a-Si: H layer 43 can be made from other silane compounds such as disilane, thermally cracks vapor phase SiH ₄ and uses an apparatus such as that shown in FIG. 1 below. It can also be made by other deposition techniques such as diffusing a silicon-containing material through a glow discharge in SiH ₄ or hydrogen. Other techniques for forming the a-Si: H layer 43 are described in the present inventor's earlier US application No. 857,690, one example of which is SiH ₄ or hydrogen-
The a-Si: H layer 43 is formed by sputtering silicon in the presence of argon.

The unexpectedly high Voc and Isc of the M / PIN battery described above cannot be explained based on the generally accepted theory. I-type a-Si: H layer 43 adjacent to the P-type layer 40
A small number of carriers that occur only in the depletion region (0.3 micron) are collected as useful current Isc. However, in the M / PIN battery of the present invention, the photon flux passing through the semitransparent electrode 44 is absorbed by the intervening N-type layer 42 and the non-depletion region of I-type a-Si: H. Outside the depletion region, the vacancy diffusion is 0.
Since it is well known to those skilled in the art that it is smaller than 1 micron, it is not possible to predict how much these regions contribute to the photocurrent. Unexpectedly, Isc does not decrease in the M / PIN battery of the present invention even if the thickness of the I-type a-Si: H layer 43 is increased to 2 microns. The thickness of the I-type a-Si: H layer is only 3 micron, which is only slightly reduced.

The second M / PIN battery contains 10% B ₂ H ₆ containing Si by opening valves 16a, 16c as described with reference to FIG.
A gas mixture of H ₄ was introduced with a helium carrier and layered on a stainless steel substrate 11 by glow discharge under a pressure of 2 torr.
It is made by first depositing boron-doped a-Si: H as 40. 2 micron a as layer 43 and layer 42 on layer 40 to complete the M / PIN battery of FIG.
-Si: H layer and 200-400Å N-type a-Si: H layer are deposited. After deposition of the semi-transparent electrode 44 and testing under AM1 sunlight, as with the first M / PIN cell with the aB: H layer 40,
High power Voc and Isc are measured. However, the Isc output in the red part of the spectrum is lower than the layer 40 deposited with aB: H only.
Higher for those co-deposited in B ₂ H ₆ / SiH ₄ . Similar high power Isc and Voc are obtained when the P-type layer 40 is B-doped a-
Si: H and hydrogenated amorphous carbon a-
When formed with C: H, it is measured under irradiation. a
Improved properties even when the Si: H layer 30 is deposited on the predeposition of the boron-containing P-type layer on stainless steel, despite the deepest light exposure area at the PN junction. Seems to make.

FIG. 5 is a tandem M / PIN / NIP in which the photovoltaic devices of FIGS. 2 and 3 are connected to a common semi-transparent electrode 53 and a balance.
The zygote is shown. First of all, the aB: H layer 50 is made of stainless steel using an apparatus as shown in FIG.
It is deposited on a steel substrate 11 to a thickness of 200Å. Then an intrinsic a-Si: H layer 51 with a thickness of 2 microns and an N-type layer 52 with a thickness of 200Å are deposited by glow discharge, resulting in a third
An M / PIN as shown is formed. A 100Å thick Ni / Cr alloy electrode 53 is vacuum deposited on the N-type layer 52 to complete the first M / PIN stage. Instead of a Ni / Cr alloy, the semi-transparent electrode 53 may be a conductive metal oxide such as tin oxide having a thickness of 0.1 micron or more.

Using the process conditions described with reference to FIG. 2, an N-type layer 54 of about 200Å thickness and then an I-type a-Si: H of 1 micron thickness.
Layer 55 is deposited by glow discharge to form M / NIP. The a-B: H P-type layer 56 is preferably deposited after cooling the substrate 11 to about 100 ° C., as was done for the second M / NIP cell described in FIG. The aB: H layer 50 on the substrate 11 is preferably deposited at a temperature of 180 ° C. or higher, while the top a
The -B: H layer 56 is preferably deposited below 180 ° C to maximize Voc. Layer 50 on stainless steel substrate 11 may be boron-doped a-Si: H,
At that time, as a-Si: H, one having a B / Si ratio of 0.1% or more is preferable.

The semi-transparent electrode 57, AR coating 58 and contact fingers 59 are then deposited on the aB: H layer 56 as before. It is also possible to connect the electrodes 11, 57 in parallel without adjusting the current of each battery in the series connection as required in conventional tandem device technology by means of suitable contact pads (not shown).

Under AM1 solar illumination, the output Isc is at least 20% higher when compared to either cell alone. The photon flux that is not absorbed by the first PIN junction passes through layer 52 and produces output minor power in the depletion region of a-Si: H layer 51 at the interface with a-B: H layer 50. And efficiency will be so low that it is ignored. However, the energy as if it had been irradiated at the beginning of the P-type layer was applied to the second M / PIN.
Connected body gets. This result on the opaque electrode 11 cannot be explained if the depletion region remains 0.3 micron thick as previously reported.

FIG. 6 shows a cross-sectional view of an image device 70 in which an aB: H layer 60 is deposited by glow discharge with a free surface 60 'that receives electrostatic charges. Here, a 0.20 inch thick aluminum substrate 61 is coated with a 0.25 micron Si ₃ N ₄ dielectric layer 66 by conventional plasma deposition or evaporation techniques. Then 10 micron a-Si: H layers 62 and 10
A 0Å a-B: H layer 60 is deposited on the dielectric layer 66 at a temperature of 180-410 ° C. using a glow discharge device as in FIG. a
-Si: H layer 62 is deposited at 30-100 ° C and 200-250 ° C.
May be annealed in. In any case, a-B: H
The temperature at which the layer 60 is deposited is preferably 180 ° C. or lower. Finally a protective organic coating such as polyparaxylene 67
Can also be deposited on layer 60.

The I-type a-Si: H layer is maintained at a temperature below the macrocrystal temperature and below the temperature at which dark resistance and photoconductivity decrease due to hydrogen desorption.
62 may be deposited by low temperature CVD in silane / helium. In order to form the I-type a-Si: H layer 62 if suitable photoconductivity, dark resistance and reverse bias charging are material specific, it was described in our US patent application No. 857,690. Other deposition techniques such as sputtering and evaporation may be used. The apparatus shown in FIG. 9 is particularly effective for image formation.

FIG. 7 schematically shows an electrophotographic apparatus that can be used to form an image on a connector such as the battery of FIG. Layer 66 by corona discharge wire 72 in housing 73
The cell 70 is placed on the conveyor of the dark chamber 76 where a high negative surface potential is induced on the surface 66 '(or the protective layer 63) of the. The battery 70 is then transported to the second dark chamber 77. There, light from a tungsten sphere 74 is focused on a test object 76 with a suitable lens system.
The battery 70 is then applied to toner (not shown) of the appropriate polarity (in liquid or powder form) and carried to the developer station 78 where it is heat deposited from the lamp 79. Both liquid and powder toners formed good transfer images corresponding to the contours of the test object. It was also found that a conventional developing electrode (not shown) inverts the image.

In FIG. 8 the image is formed on the surface 80 'of the cell 80 , such as the surface of the aB: H layer 30 of the M / NIP cell shown in FIG. 2 without the electrodes 34 and AR coating 35. An X-ray point discharge source that can be used for is shown. First, the aB: H surface 80 'is negatively charged by the high voltage corona wire 82 in the electrostatic shield 83 located in the dark chamber 86. Battery 80 after charging
Is conveyorized from chamber 86 to chamber 87, which is shielded, and exposed with x-rays from point source 84.
The X-rays cause the I-type a-Si: H layer 10 to become electrically conductive and discharge the electrostatic charge on the surface 80 '. The induced conductivity and the amount of discharged charge are a function of X-ray emissivity and exposure time. The dose of X-rays is reduced according to the subject 85 and accordingly a-B:
The discharge of charges on the H layer 30 is determined. The battery 80 is carried to a chamber 88 where commercial toner (powder or liquid) is applied and fixed with heat from a lamp 89. Of FIG.
The M / PIN battery was positively charged and formed a good image of subject 85 when the proper toner was used.

FIG. 9 shows a cylindrical substrate used as an image forming member.
A glow discharge deposition apparatus particularly suitable for coating 90 is shown. The substrate 90 is made of an aluminum cylinder 6 inches in diameter and 18 inches long supported by a rod 94 in an insulated bearing barrel 95 in a pedestal 93. Enclosure 100 is made of 12 inch diameter 28 inch long stainless steel tubing 91 with a top plate 97 and provides a vacuum tight seal when placed on a table with a suitable gasket. Has become. Cylindrical electrode 92
(Electrically coupled to the top plate 97) is placed coaxially to the surface 99 of the substrate 90 with a gap d from the top surface 99 as shown. Gas G passes through a plate 97 from a storage tank and a regulating valve (not shown) to a nozzle.
Easy to inject with 120. As discussed with respect to FIG. 1, suitable gases for forming a-Si: H include SiH ₄ or disilane, and silicon dopants include phosphine, arsine or diborane. Gas G is pumped through the gap and through a valved stainless steel conduit 98 vacuum pump 131
Exhausted through. The power supply 132 is the support rod 9 of the substrate 90.
4, a strong electric field region Es, which is connected between the grounded enclosure members 91, 92, 93 and 97, is induced in the gap d between the electrodes 92 and 99, and a weak electric field region Ew is formed on the surface of the substrate 90. Induced. A heater wire 96 with a suitable ceramic insulator is attached to the table 93, and a part of the gas G is thermally decomposed to form a silicon compound, which diffuses into the plasma part P and promotes glow discharge. The cylinder block 134 on the table 93 is shielded by the bearing cylinder 95 insulated from the silicon-containing compound.

The operation of the device is similar to that described in FIG.
A negative voltage of 0 to 1500 V is applied, and the strong electric field region Es
Inside, glow discharge is started through gas G at pressure PG.
The diffusive component of the glow discharge plasma P is then positioned in the weak electric field region Es above the active surface of the substrate 90 by adjusting the pressures PG and V. Furthermore, the SiH ₄ a-Si: Upon depositing H, power by passing a sufficient current (not shown) to the heater wire 96, some of the SiH ₄ is thermally decomposed, and the plasma is some of the silicon-containing fragment Diffuse into P and onto the surface of substrate 90, thereby forming coating 130. The deposition rate is enhanced by these pyrolyzed fragments and the electrical resistivity of the a-Si: H thin film 130 is increased to make the coating 130 particularly suitable for imaging devices. The coating 130 is a heater (not shown)
Deposited on a substrate 90 maintained at 180-410 ° C., or deposited on a substrate 90 maintained at 30-100 ° C.,
Then it is annealed to 200-300 ℃.

In order to complete the imaged PN junction, the aB: H layer 131
Is deposited on the surface of the a-Si: H layer 130 by glow discharge as described in FIG.

In testing an electrophotographic device such as that shown in FIG.
The aB; H top layer 131 was charged above 100 volts. Devices made with the device shown in FIG. 9 are shown in FIGS.
It has good imaging properties with any combination of P, I, N and blocking layers as described (without electrodes 34, 44 and AR coatings 36, 46). Also, the solar cells, rectifier diodes and planar transistors made with the device of Figure 9 exhibit improved characteristics.

a-C: H and a-Si: H to a-B: gas containing boron, such as BF ₃ may be used with hydrogen dilution when added H. 196
The inventors have previously used BF ₃ as a gas source for glow discharge coating thin films of borane, as described in paragraph 6 of U.S. Pat. No. 3,069,283, issued Dec. 18, 2012. I would like to mention the fact that I was doing. However, the present invention relies on a-Si and a-B contact and it is preferred to control each deposition temperature.

Further, the inventors have found that when the deposition temperature of the N-type layer 42 is lowered to 100 ° C., Voc increases by 50 mV in the M / PIN structure. I-type a-Si has maximum I when deposited at 180 ℃ or higher.
This is surprising because it expresses sc.

In fact, in the past, all a-Si thin films had to be deposited or annealed at 180 ° C or higher in order to be electrically active. This voltage increase occurs when silane is mixed with a phosphine or arsine dopant gas during the formation of layer 42 using an apparatus such as that shown in FIGS.

It is therefore clear that the concepts described thus far form the basis of solar energy conversion, rectifying junctions as circuit elements with opaque electrodes and improved photovoltaic devices useful in image devices. The semiconductor device of the present invention can be used to make an improved bipolar transistor. Other applications and combinations will be readily apparent to one of ordinary skill in the art.

[Brief description of drawings]

FIG. 1 is the first apparatus for glow discharge deposition and doping of amorphous boron, amorphous silicon and amorphous carbon. FIG. 2 is a sectional view of the M / N1P semiconductor showing the first embodiment of the present invention. Third
The figure is a cross-sectional view of an M / PIN semiconductor showing a second embodiment of the present invention. FIG. 4 is a graph showing a boron / silicon ratio in an amorphous boron / amorphous silicon connection body. FIG. 5 is a sectional view of a tandem semiconductor device showing a third embodiment of the present invention.
FIG. 6 is a sectional view of an image forming apparatus representing a fourth embodiment of the present invention. FIG. 7 is a schematic view of an electrophotographic developing device. FIG. 8 is a schematic diagram of an X-ray electrophotographic apparatus showing a fifth embodiment of the present invention. FIG. 9 is a schematic diagram of a second apparatus for thermal decomposition of a silicon-containing gas.

Continuation of front page (56) References JP-A-56-138970 (JP, A) JP-A-57-139972 (JP, A) Appl. Phys. Lett. , 42 (4), 15 February 1983, PP. 369-371

Claims (1)

[Claims] 1. A laminate having an N-type semiconductor layer, an I-type semiconductor layer adjacent to and in contact with the N-type semiconductor layer, and a P-type semiconductor layer provided adjacent to the I-type semiconductor layer. In the method of manufacturing a semiconductor device provided on a substrate, a deposited film made of amorphous silicon is used as the I-type semiconductor layer at a substrate temperature.
Forming a P-type semiconductor layer on the I-type semiconductor layer by holding the deposited film of hydrogen-containing amorphous boron at a substrate temperature of 180 C or lower. A method of manufacturing a semiconductor device, comprising: