JPH0782035B2 - Waveform storage - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform storage device that digitally processes an analog input signal and stores the digital input signal, and more particularly, to processing when an analog input signal suddenly changes. It is a thing.

(Prior Art) As a conventional waveform storage device, for example, as disclosed in Japanese Patent Publication No. 58-47661, digital conversion means for sampling an input signal with a sample clock having a first speed and converting it into a digital signal. Storage means for storing digital data at a recording clock having a second speed equal to or lower than the speed of the sample clock, and the storage means for detecting the minimum and maximum values of digital data from the digital conversion means during the storage cycle of the storage means. And a minimum and maximum value detecting means for supplying it as digital data to the digital camera.

With such a configuration, the maximum value and the minimum value of the waveform in many sample clock periods in the recording clock cycle are detected and accumulated, and the envelope of the waveform, that is, the maximum signal deviation can be detected and displayed.

(Problems to be Solved by the Invention) However, according to such a conventional configuration, even if significant amplitude fluctuations of a waveform exist between recording clocks as shown in FIG. If the maximum value max of the amplitude fluctuation is smaller than the maximum value MAX of the waveform amplitude between recording clocks and the minimum value min of the amplitude fluctuation is larger than the minimum value MIN of the waveform amplitude between recording clocks, it is not detected at all. This will interfere with the measurement.

The present invention focuses on such a point, and an object thereof is to provide a waveform storage device capable of accurately detecting and displaying an amplitude variation of a meaningful waveform generated between recording clocks.

(Means for Solving the Problems) The waveform storage device of the present invention includes an A / D converter that samples an analog input signal at a first cycle and converts the analog input signal into a digital signal, and the A / D converter performs conversion. The maximum value (maximum maximum value) of the average value and the plurality of local maximum values in the second cycle, which is longer than the first cycle, and the minimum one (the minimum value of the plurality of local minimum values), Minimum value), and when maximum maximum value and minimum minimum value are obtained, these are treated as a set of two representative value data, and when either maximum maximum value or minimum minimum value is obtained, the Either one and the average value is 2
A representative value calculation circuit that outputs one set of representative value data and outputs an average value as one set of representative value data when neither the maximum maximum value nor the minimum minimum value is obtained, and this representative value calculation circuit And a memory for storing the representative value data output from the.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
An example of channel input is shown. In addition, peripheral circuits such as a trigger circuit for capturing an analog input signal are omitted. In FIG. 1, 1 is an analog input signal S
It is an A / D converter that converts _A (y = f (t)) into a digital signal according to a predetermined sample clock, and its output signal S _D is added to the representative value calculation circuit 2. The representative value calculation circuit 2 obtains an average value, a maximum value and a minimum value of a plurality of digital signals converted by the A / D converter 1 within a recording clock having a second cycle longer than the first cycle, Representative value data S _D ′ is obtained from these average value, maximum value and minimum value. Reference numeral 3 denotes a memory, which stores the representative value data S _D ′ between the recording clocks output from the representative value calculation circuit 2. A display control circuit 4 reads the representative value data S _D ′ between consecutive recording clocks stored in the memory 3 and outputs a video signal S _V for displaying as a waveform by raster scanning. 5 is a video signal S _V output from the display control circuit 4.
It is a CRT that receives a raster scan and displays a waveform related to the analog input signal S _A. A timing control circuit 6 outputs various timing control signals for controlling the operation of each unit. That is, the timing control circuit 6 outputs the sample clock S ₁ for causing the A / D converter ₁ to perform A / D conversion, and the representative value calculation circuit 2 outputs the representative value data.
The recording clock S ₂ for calculating S _D ′ is output, the address and the write control signal S ₃ for storing the representative value data S _D ′ are output to the memory 3, and the memory 3 and the display control circuit 4 are further output. Reads the representative value data S _D ′ from the memory 3 and outputs an address and a display control signal S ₄ for adding to the display control circuit 4.

Next, the representative value calculation processing in the representative value calculation circuit 2 of the present invention will be described with reference to FIG.

That is, the present invention focuses on the extreme value of the waveform amplitude. In FIG. 2, there are four extreme values P _{1 to} P _{4 in} the recording clock section T between the time t _A and the time t _B , and the maximum values are P ₃ ,
The minimum value is P ₂ . On the other hand, the maximum value in this section T is B, and the minimum value is A. Here, the maximum value P ₃ and the minimum value P ₂ are both smaller than the maximum value B and larger than the minimum value A, and the maximum value in this section T,
Not the minimum value. However, as the value of information judged from the purpose of peak detection, the maximum value P ₃ and the minimum value P ₂ are larger than the maximum value B and the minimum value A. Therefore, in the present invention, the maximum value P ₃ and the minimum value P ₂ are adopted as the peak information in the section T.

When there is no extreme value in the section T, the waveform of the section T becomes a monotone increasing curve or a monotonous decreasing curve. In order to obtain the characteristic value as the sample data of such a waveform, it is conceivable to calculate the average value M of the section T by the following equation.

Practically, the average value M of n pieces of digital data extracted from the section T may be calculated as in the following equation.

M = (y ₁ + y ₂ + ... y ₂ n) / n: n ≧ 2 Here, n ≧ 2.

Summarizing these, the data required in the section T is the maximum value data Pmax, the minimum value data Pmin, and the average value data M. However, storing these three data in each recording section is uneconomical because the memory capacity increases. Therefore, the required memory capacity is reduced by selecting two pieces of data D ₁ and D ₂ as representative value data for each section according to the following conditions and storing them in the memory 3.

If Pmax and Pmin are obtained, M is ignored. If only Pmax and Pmin are obtained, then that value and M If neither Pmax and Pmin are obtained, let M be Pmax and Pm.
In place of in, the i-th representative value data set among the data sets of the continuous sections stored in the memory 3 in this way And Here, D ₁ and D ₂ correspond to any one of the above-mentioned conditions ( ₁₎ to (4), and for convenience, D ₁ ≦ D ₂ is set.

If D ₁ <D ₂ , it means that there was an amplitude fluctuation having an extreme value in the i section, and if D ₁ = D _2, it means that the i section was monotonically increasing or monotonically decreasing. If you summarize these relationships in a table,
It looks like this:

Specifically, if the value of T, which is the recording period, is set to 1 msec and the sample clock of the A / D converter 1 is set to 50 nsec, the representative value calculation circuit 2 starts from 1 msec / 50 nsec = 20000 (pieces) of sampling data. Table Execute the calculation process to determine the
_One set of data consisting of ₁ and D ₂ will be written.

FIG. 3 is a block diagram showing a specific example of such a representative value calculation circuit 2. In FIG. 3, A is an extreme value detection circuit, B is a maximum / minimum detection circuit, C is a representative value calculation circuit, and D
Is an output selection circuit.

FIG. 4 is a waveform diagram for explaining the operation of the extreme value detection circuit A. In FIG. 4, the j-th sample data of the waveform y = f (t) sampled at every minute time ΔT in the section T _i is defined as f _i (jΔT). Here, the extreme value is the sample data immediately before the sample data in which the sign of the difference value f _i (jΔT) −f _i {(j−1) ΔT} of the adjacent sample data is inverted, and the sign is A change from positive to negative is defined as a positive extreme value P _P , and a change from negative to positive is defined as a negative extreme value P _N. The inversion does not include a sign. In FIG. 4, j =
The sample data of 6 becomes the positive extreme value P _P , and the sample data of j = 13 becomes the negative extreme value P _N.

Such an extreme value detection circuit A includes a D-type flip-flop 7 to which the sample data f _i (jΔT) is applied to the data terminal and the clock φ _S having the period ΔT is applied to the clock terminal,
The sample data f _i (jΔT) was added to one input terminal and the output signal of the D-type flip-flop 7 was added to the other input terminal, and the output signal of the D-type flip-flop 7 was added to the data terminal. The D-type flip-flop 9 to which one output signal P _N D of the comparator 8 is added to the clock terminal and the output signal of the D-type flip-flop 7 to the data terminal and the other output signal P _P D of the comparator 8 to the clock terminal And a D-type flip-flop 10 to which is added.

The D-type flip-flop 7 latches the sample data f _i (jΔT) according to the clock φ _{S having the} period ΔT. As a result, the D-type flip-flop 7 holds the sample data f _i {(j−1) ΔT} one clock before. The comparator 8 outputs P ND = 1 when f _i (jΔT)> f _i {(j-1) ΔT}, and outputs P _N D = 1 when f _i (jΔT) <f _i {(j-1) ΔT} Outputs _P D = 1. These signals indicate that an extreme value has been detected. The D-type flip-flop 9 is f by the rising edge of P _P D from 0 to 1.
_i {(j-1) ΔT} is held as the extreme value P _P , and the D-type flip-flop 10 holds f _i {(j-1) ΔT} by the rising edge of P _N D from 0 to 1. The extreme value P _N.

The maximum / minimum detection circuit B detects the maximum value in the positive direction and the maximum value in the negative direction from the plurality of extreme values.

FIG. 5 is a waveform diagram for explaining the operation of the maximum / minimum detection circuit B. The In Figure 5, the interval T, there are three extreme value P _P1 to P _P3 to the maximum value of P _P3 in the positive direction, three extrema of the minimum value of P _N1 in the negative direction There are P _{N1 to} P _N3 . Therefore, maximum and minimum detection circuit B detects the _{Pmax = MAX of {P Pk}} = P P3 and _{Pmin = MIN of {P Nk}} = P N1.

This maximum / minimum detection circuit B has an extreme value signal P _{P at the} data terminal.
And a D-type flip-flop 11 to which the output signal of the comparator 12 is added to the clock terminal, and an output signal of the D-type flip-flop 11 to one input terminal and an output signal of the D-type flip-flop 9 to the other input terminal. And a D-type flip-flop 13 to which the output signal of the D-type flip-flop 10 is added to the data terminal and the output signal of the comparator 14 is added to the clock terminal.
And the output signal of the D-type flip-flop 13 is applied to one input terminal and the D-type flip-flop 10 is applied to the other input terminal.
And the comparator 14 to which the output signal of The D-type flip-flops 11 and 13 are preset to the minimum value and the maximum value that can be taken as the sample data f _i (jΔT) for each section T, but the circuit for that is omitted in the figure.

Due to the combined operation of the D-type flip-flop 11 and the comparator 12, the positive maximum value (maximum value) Pmax of the plurality of extreme values generated in one period T _i is held in the D-type flip-flop 11, Due to the combined operation of the flip-flop 13 and the comparator 14, the negative maximum value (minimum value) Pmin of a plurality of extreme values generated in one cycle T _i is held in the D-type flip-flop 13.

The representative value calculation circuit C calculates the arithmetic mean value M _i of the first sample data f _i (1ΔT) and the last sample data f _i (nΔT) according to the following equation, as a representative value of the plurality of sample data in the section T _i . Output.

M _i = INT [f _i (1ΔT) + f _i (nΔT)}] This representative value calculation circuit C has sample data at the data terminal.
f _i (iΔT) is added to the clock terminal and the operation clock φ
A D-type flip-flop _{15 M} is added, a D-type flip-flop 16 the operation clock phi _M output signal is applied to the clock terminal of the D-type flip-flop 15 to the data terminal is applied, D-type flip to one input terminal 15
Of the D-type flip-flop 16 is added to the other input terminal of the D-type flip-flop 16 to perform the above-mentioned arithmetic mean calculation.

As a result, the D-type flip-flop 15 holds the sample data f _i (1ΔT), the D-type flip-flop 16 holds the sample data f _i (nΔT), and the arithmetic circuit 17
Therefore, the arithmetic mean value M is output.

The output selection circuit D outputs the output data according to the above table. To decide.

The output selection circuit D includes a D-type flip-flop 18 to clear signal PCLR is applied to the clock terminal H level signal is applied to the data terminal in extreme detection signal P _P D is applied clear terminal, H-level to the data terminal A D-type flip-flop 19 to which a signal is applied, an extreme value detection signal P _N D is applied to the clock terminal, and a clear signal PCLR is applied to the clear terminal, and an arithmetic mean value M is applied to one input terminal A and the other input terminal is applied. A data selector in which the maximum value Pmax is added to B and the output signal of the D-type flip-flop 18 is added to the selector terminal S
20; a data selector 22 to which an arithmetic mean value M is added to one input terminal A, a minimum value Pmin is added to the other input terminal B, and an output signal of the D-type flip-flop 19 is added to a selector terminal S; To the D-type flip-flop 21 to which the output signal of the data selector 20 is added to the clock terminal and the selected clock φ _T to the clock terminal, and to which the output signal of the data selector 22 is added to the data terminal and the selected clock φ _T to the clock terminal. And a flip-flop 23.

D-type flip-flop 18 and 19 and outputs a selector signal applied to the data selector 20 and 22, the output signal of the D-type flip-flop 18 becomes H level by the rise of the extreme detection signal P _P D, D The output signal of the flip-flop 19 becomes H level at the rising edge of the extreme value detection signal P _N D. The output signals of these D-type flip-flops 18 and 19 are reset to the L level by the clear signal PCLR every period T. The data selectors 20 and 22 have input terminals B when the signal level applied to the selector terminals S is H.
To the output terminal Y, and when the signal level applied to the selector terminal S is L, the input terminal A
To the output terminal Y.

As a result, the data selector 20 outputs the maximum value Pmax when a positive extreme value is detected, and outputs the arithmetic mean value M otherwise, and the data selector 22 detects a negative extreme value. In this case, the minimum value Pmin is output, and in other cases, the arithmetic mean value M is output.
The output signal of 20 is data through the D-type flip-flop 21.
It is output as D _{2i and} the output signal of the data selector 22 is D
The data is output as the data D _1i via the flip-flop 23.

Next, N sets of representative value data stored in the memory 3 The procedure for reading and displaying as a waveform on the CRT5 will be described.

FIG. 6 is an explanatory diagram of a display screen of CRT5. Raster scanning is performed from bottom to top along the y-axis direction (longitudinal). Therefore, the raster arrangement is in the x-axis direction (horizontal, waveform time axis). When one raster on the display screen corresponds to the recording section T, the amplitude of the waveform is indicated by the position in the raster direction. The scanning time from the bottom to the top of the raster display screen is L
To divide. When the number of rasters is N, the screen can display L × N pixels. I read from the memory 3
Th representative value data Is displayed on the i-th raster.

A method of displaying _N time-series data Y _N as a waveform by a continuous curve on the screen of such a CRT will be described.
If the resolution of the time series data Y _N corresponds to the vertical resolution L of the screen, the value of the arbitrary data Y _i corresponds to the Y _i pixel of the _i th raster. Therefore, all data Y _N
By arranging on the N rasters, the given pixel shows the waveform shape of the analog input signal S _A sampled by the A / D converter 1 as shown in FIG.

By the way, although this method is simple, when the distance between adjacent pixels exceeds one pixel, continuous bright points do not form between pixels, and it is difficult to identify as a waveform in the case of a waveform with a large slew rate. Become. Therefore, as shown in FIG. 8, such a gap between adjacent pixels is interpolated by the pixels shown by the broken line. Also in this embodiment,
In this way, the pixels between the adjacent pixels are interpolated and displayed.

That is, two representative value data in one recording section T _i A method for displaying the extreme value data more clearly as well as for displaying as in FIG. 8 will be described. In the display of this example, the following display methods 1 to 3 are used together.

In one, one representative value data D ₁ is made to correspond to the starting point pixel ys _i , the other representative value data D ₂ is made to correspond to the ending point pixel ye _i , and interpolation display is performed between these two pixels ys _i , ys _i . Where y
Let s _i ≤ye _i .

In, the central value R _i of both data is calculated by the following equation.

R _i = INT {1/2 (D _1i + D _2i )} Then, using R _i as a data series, the start point pixel ys _i ′ and the end point pixel ye _i ′ are calculated for each raster, and these 2
Interpolation display is performed between the pixels ys _i ′ and ye _i ′.

, And when D ₁ <D ₂ , luminance modulation is applied to the display between the two pixels ys _i and ye _i in that section.

As a result, the display as shown in FIG. 9 is performed.

FIG. 10 shows a display selection circuit 4 for performing such a display.
It is a concrete circuit example figure of. In the figure, 24 is a D-type flip-flop, which is a data series read from the memory 3 by the clock φ _N. Latch. The output data of this D flip-flop 24 is the input data And become. 25 is the i-th data From the following equation, R _i = INT {1/2 (D _1i + D _2i )} based arithmetic circuit for calculating the median R _i , 26 is the i-1th data _Is an arithmetic circuit for calculating the median value R _i-1 based on the following equation, R _i-1 = INT {1/2 (D _1i-1 + D _2i-1 )}. 27 is a start point ys _i and an end point ye _i (ys _i ≤y for interpolating pixels on the i-th raster based on these median values R _i and R _i-1.
This is an arithmetic circuit that calculates e _i ). 28 is a dot counter that counts the number of pixels on the raster, and the count value is y
It is output as the dot address da in the axial direction. 29 is the starting point
A comparator 30 detects a match between ys _i and dot address da, and a comparator 30 detects a match between end point ye _i and dot address da. Reference numeral 31 is a mono-multi circuit that outputs a signal that interpolates between the two signals based on the output signals of these comparators 29 and 30. For video signal v ₁ . _{Reference numeral} 32 is a comparator that detects a match between the data D _2i and the dot address da, and 33 is a comparator that detects a match between the data D _1i and the dot address da. 34 is a mono-multi circuit that outputs a signal that interpolates between the two signals based on the output signals of these comparators 32 and 33.The output signal of this mono-multi circuit 34 continuously displays the median value of each data. For video signal v ₂ . Reference numeral 35 is a video synthesizing circuit for synthesizing these video signals v ₁ and v ₂ . 36 is a comparator for detecting the coincidence of the data D ₁ and the data D ₂ , and the output signal of this comparator 36 is added to the video synthesizing circuit 35.

FIG. 11 is a timing chart for explaining the operation of such a video synthesizing circuit 35. That is, the video composition circuit 35, for video signals v ₁ generates a signal voltage E ₁ (a), a video signal v for ₂ (b) voltage as shown in E ₂ Generate the signal. And
As these composite signals, as shown in (c), the timing is the same as the video signals v ₁ and v _2, and the voltage is the comparator 3
When the output signal of 6 is at the H level, E ₂ = E _1, and when it is at the L level, a signal S _V that produces E ₂ > E ₁ is generated.

As a result, the display portion related to either the maximum value or the minimum value is subjected to the brightness modulation, and can be clearly discriminated from the normal interpolation display portion.

Such a waveform storage device, for example, in the transition between the H level and the L level of the logic circuit, the output of the comparator, the input signal of the switch element, and other signals whose amplitudes greatly change, the amplitude, the jitter, and the chattering that occur at the transition. It is effective for observing harmful amplitude fluctuations that change rapidly. That is, in these observations, it is possible to detect and capture the peak fluctuation buried between the maximum value and the minimum value of the amplitude of the signal in the constant sample section.

Further, such a device is also effective for detecting the envelope of the amplitude modulation waveform and for identifying the occurrence of aliasing due to sampling.

The data series In the display of, the display based on the median value R _i and the display with D ₁ and D ₂ as the start point ys _i and the end point ye _i are switched for each display frame, and when D ₁ ≠ D ₂ in the display of Alternatively, the display brightness between the start point ys _i and the end point ye _i may be increased.

Also, data from memory 3 May be read out and the waveform may be expanded and displayed according to the method of the present invention in a bitmap type refresh memory using a microcomputer or the like.

In the above embodiment, the output signal S _D of the A / D converter 1 is added to the representative value calculation circuit 2 and the representative value data S _D ′ between the recording clocks output from the representative value calculation circuit 2 is stored in the memory. Three
However, as shown in FIG. 12, all the output signals S _D of the A / D converter 1 are temporarily stored in the acquisition memory 37.
Alternatively, the data stored in the acquisition memory 37 may be sequentially read and added to the representative value calculation circuit 2. Note that S ₅ is the acquisition memory 37
Control signal. With such a configuration, not only the detection of a meaningful peak, but also the time axis can be expanded and the details of the peak portion can be displayed and observed as necessary. The device having such a configuration is extremely effective for observing a noise waveform superimposed on a relatively low-frequency signal and observing an amplitude modulation waveform. Furthermore, according to such a configuration,
In some cases, the calculation result of the representative value calculation circuit 2 can be directly converted into an image signal without interposing the memory 3.

(Effect of the Invention) As described above, according to the present invention, it is possible to realize a waveform storage device capable of accurately detecting and displaying the amplitude fluctuation of a meaningful waveform generated between recording clocks, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of representative value calculation processing in the representative value calculation circuit of FIG. 1, and FIG. 3 is a concrete example of the representative value calculation circuit of FIG. FIG. 4 is a block diagram showing an example, FIG. 4 is a waveform diagram for explaining the operation of the extreme value detection circuit A in FIG. 3, and FIG. 5 is a diagram for explaining the operation of the maximum / minimum detection circuit B in FIG. Waveform diagram, FIG. 6 is an explanatory diagram of a CRT display screen, FIG. 7 is an explanatory diagram of a display waveform by a conventional pixel, FIG. 8 is an explanatory diagram of a display waveform by an interpolated pixel, and FIG. 9 is an explanatory diagram of a display waveform by the present invention. FIG. 10 is a block diagram showing a specific example of the display control circuit of FIG. 1, FIG. 11 is a timing chart for explaining the operation of the main part of FIG. 10, and FIG.
FIG. 13 is a block diagram showing another embodiment of the present invention, and FIG. 13 is a waveform diagram for explaining the operation of the conventional device. 1 ... A / D converter, 2 ... Representative value calculation circuit, 3 ... Memory, 4 ... Display control circuit, 5 ... CRT, 6 ... Timing control circuit.

Claims (1)

[Claims] 1. An A / D converter for sampling an analog input signal in a first cycle and converting it into a digital signal, and a first cycle based on a plurality of digital signals converted by the A / D converter. The maximum value (minimum minimum value) of the maximum value (maximum maximum value) and the minimum value (minimum minimum value) of the plurality of maximum values and the average value within the longer second cycle is obtained, and the maximum maximum value and the minimum minimum value are obtained. In the case where any one of the maximum maximum value or the minimum minimum value is obtained, the average value is set to 2
A representative value calculation circuit that outputs one set of representative value data and outputs an average value as one set of representative value data when neither the maximum maximum value nor the minimum minimum value is obtained, and this representative value calculation circuit And a memory for storing representative value data output from the waveform storage device.