JPH0779426A - Scramble system - Google Patents

Abstract

PURPOSE:To control the effect of scrambling in the digital transmission through comparatively simple configuration. CONSTITUTION:Data quantized by a quantizer 104 are received by a scramble circuit 220, in which the data are scrambled and the result is inputted to a variable length coder 111. The scramble circuit 220 has a scramble frequency selection circuit 202 and a scramble block selection circuit 201 and gives a PN from a PN generating circuit 203 to an optional frequency area of an optional data block. Block data information being an object of scrambling is inputted to the variable length coder 111, in which the information is included in header information of the transmission data and the result is sent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scramble system effective for scrambling pay broadcast programs and the like in television broadcasting.

[0002]

2. Description of the Related Art When pay broadcasting is performed in each broadcasting medium such as satellite broadcasting, terrestrial broadcasting, and CATV, video and audio are scrambled for a pay program, and a viewer solves this problem. It has a decoder so that you cannot watch it unless you pay the reception fee. CAT is a scramble method in analog transmission.
There are various methods such as a method of compressing the synchronization part, which is often used in the V system, and a line rotation method in which scanning lines used in satellite broadcasting are switched at appropriate points.

However, in recent years, due to the rapid development of digital technology, there has been an active movement of not only video processing but also transmission itself in digital form. In such a flow, a scramble system suitable for digital transmission is also being studied. The scramble system in this digital transmission is roughly classified into two. One is a method of uniformly scrambling at the stage of transmission, which mainly superimposes a pseudo-random signal. The other is to encrypt video and audio signals at the stage of compression coding.

FIG. 1 shows an example of a configuration in the case of scrambling at the stage of compressing and coding a video signal which is the latter method. Here, the encoding device has a configuration of DCT (discrete cosine transform) + motion compensation interframe encoding.

A video signal is input to the terminal 101. This signal is a signal converted from the original scanning order into a scanning order suitable for encoding. This is because the DCT process is performed in units of a specific block (for example, horizontal 8 pixels and vertical 8 lines). The unit of this block does not matter, but generally 8 × 8 pixels or 1
A unit of 6 × 16 pixels is often used. The blocked video signal is first input to the subtractor 102. The subtractor 102 controls the inter-intra switching circuit 110 that selectively switches between encoding within a frame (intraframe) and interframe (interframe) to control the input video signal from the input video signal. The frame signal or "0" is subtracted. This subtractor 102
The output of is subjected to orthogonal transformation by the next DCT device 103 to be a signal in the frequency domain, and is further quantized by the quantizer 104 to a predetermined number of bits. The output of the quantizer 104 is returned to the original signal in the time domain through the inverse quantizer 105 and further the inverse DCT unit 106, and is input to the adder 107. The output of the adder 107 is input to the frame memory 108. The motion compensation circuit 109 has an input terminal 101.
Current signal from the frame memory 108 and the previous signal from the frame memory 108 are compared to each other, and when there is motion between frames, a motion vector indicating the direction and magnitude is calculated, and the motion vector is used to vector the signal one frame before. The output is corrected in the direction. The corrected signal is input to the inter-frame / intra-frame switching circuit 110, further input to the adder 107, added to the output of the inverse quantizer 106, and then stored in the frame memory 108.

The signal encoded by such an encoding loop (that is, the output of the quantizer 104) is added by the adder 122 to the signal generated by the PN (pseudo random noise) generating circuit 121 in the scramble circuit 120. You can simply scramble the entire screen. The video signal scrambled by the scramble circuit 120 is Huffman coded by the variable length coding circuit 111, and the initial value of PN input from the scramble circuit 120 is coded as header information. These pieces of encoded information are guided to the output buffer 112 and send out signals at a constant transmission rate.
It is guided from a terminal 113 to a TV modulator (not shown), modulated into a predetermined TV channel, and transmitted to a transmission line. Further, the output buffer 112 outputs a control signal to the quantizer 104 by itself so that the output buffer 112 does not overflow or underflow, and controls the amount of generated information by increasing or decreasing the number of bits to be quantized. As described above, scrambling with high concealment can be performed by adding PN to the quantized DCT coefficient in the digital compression encoding device.

[0007]

However, in the case of pay broadcasting, the effect of scrambling is often controlled such that the degree of scrambling is lightened to some extent or that only a part of the scramble is scrambled to entice the viewer to buy. . It is difficult to perform such effect control of scramble by the above-mentioned method of simply adding PN. Therefore, an object of the present invention is to provide a scramble system that can freely control the degree of scrambling.

[0008]

According to the present invention, an input image is divided into blocks, and the input image is divided into two blocks within the processing unit of the blocks.
A means for performing a three-dimensional discrete cosine transform, a quantizing means for quantizing the result at a certain quantizing step, and a scrambling means at a stage subsequent to the quantizing means, wherein the scrambling means scrambles blocks to be scrambled. It is characterized by being selected and scrambled. A means for setting which block in the screen is to be scrambled and a means for setting which frequency component is encrypted for each block are provided, and the range to be scrambled and the degree of scrambling are determined by these control means. The configuration is

[0009]

It is possible to control the effect of scrambling any part at any level with a relatively simple circuit configuration.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and have the same functions.

That is, a video signal is input to the terminal 101. This signal is a blocking signal (for example, horizontal 8 pixels, vertical 8 lines) converted from the original scanning order to a scanning order suitable for encoding. The blocked video signal is input to the subtractor 102. The subtractor 102 controls the inter / intra switching circuit 110 that selectively switches between coding within a frame (intra frame) and between frames (inter frame), and controls from the input video signal. The signal of the previous frame or "0" is subtracted. The output of this subtractor 102 is the next D
The CT unit 103 performs orthogonal transformation to form a signal in the frequency domain, and the quantizer 104 quantizes the signal into a predetermined number of bits. The output of the quantizer 104 is the inverse quantizer 105,
Further, the signal is returned to the original time domain signal through the inverse DCT unit 106, and is input to the adder 107. Adder 107
Is output to the frame memory 108. The motion compensation circuit 109 compares the current signal from the input terminal 101 with the signal from the frame memory 108 before the frame, calculates a motion vector indicating the direction and magnitude of the motion between frames, and calculates the motion vector. It is used to correct the signal one frame before and output it in the vector direction. The corrected signal is input to the inter-frame / intra-frame switching circuit 110, further input to the adder 107, added to the output of the inverse quantizer 106, and then stored in the frame memory 108.

The signal encoded by such an encoding loop (that is, the output of the quantizer 104) is input to the adder 204 of the scramble circuit 220. In addition to the PN generation circuit 203, the scramble circuit 330 includes a scramble block selection circuit 201 for determining which block in the screen is to be scrambled, and which frequency component among the blocks selected by the scramble block selection circuit 201. A scramble frequency selection circuit 202 that determines whether or not to apply scramble is performed, and scramble control is performed by controlling these two circuits. This part is a feature of this system.

The scramble block selection circuit 201 is
A signal that becomes active only when the encoded output of the block to be scrambled on the screen is input to the scramble circuit 220 is generated, and scramble is turned on for that block. Also, as in this embodiment, the DCT
In the case of an encoding device using the processing, the output after the DCT processing is the DC component diagonally to the upper left as shown in FIG. 2A, the horizontal high-frequency component in the horizontal direction, and the vertical component in the vertical direction. High frequency components appear. By utilizing the conversion characteristic of this DCT processing, it is possible to construct a scramble system with high concealment without adding PN to all frequency components and scrambling. For example, in general, when DCT processing is performed on a video signal, energy concentrates on low frequency components, so that PN is added only to this portion and encryption is performed, which is almost the same as encryption on all components. Concealment is obtained. The scramble frequency selection circuit 202 selects which frequency component of the DCT coefficient is to be encrypted in this way, and becomes active only when the frequency component determined here is input to the scramble circuit 220. Generate a signal. AND circuits 204, 20 when these two circuits are activated
PN generated by PN generator 203 when 5 becomes active
Are added by the adder 206. As a result, as shown in FIG. 3, it is possible to scramble a specific portion in the screen in block units at an arbitrary level. At this time, the selected block and the signal indicating the frequency component selected in the block are simultaneously input to the variable length coding circuit 111 and coded as header information.

Huffman coding is performed in the variable length coding circuit 111. These pieces of encoded information are output to the output buffer 11
2 and sends a signal at a constant transmission rate to the terminal 1
13 is led to a TV modulator (not shown), and a predetermined TV
It is modulated into a channel and transmitted to the transmission line. Further, the output buffer 112 outputs a control signal to the quantizer 104 by itself so that the output buffer 112 does not overflow or underflow, and controls the amount of generated information by increasing or decreasing the number of bits to be quantized.

Next, the scramble block selection circuit 201 and the scramble frequency selection circuit 202, which are features of this system, will be described in more detail. Figure 2 (B)
Shows the scramble block selection circuit 201 in detail, and comprises a storage medium 501 such as a ROM, an arithmetic circuit 502, and a timing circuit 503. ROM for example
The number of the block to be scrambled is recorded in 501, and the arithmetic circuit 502 reads this number and compares it with the block number actually input by the timing circuit 503 and processed by the scramble circuit 220. If it does, it operates to output an active signal.

Further, the scramble frequency selection circuit 202
Is a storage medium 60 such as a ROM as shown in FIG.
1, an arithmetic circuit 602, and a timing circuit 603.
A table of frequencies to be scrambled recorded in the ROM 601 is read out to the arithmetic circuit 602 and is actually output from the timing circuit 603.
20 is compared with the signal representing the frequency component processed.
Then, an active signal is output when a timing signal indicating a pixel that matches the frequency table read from the ROM 601 is input.

There are many possible frequency selection patterns for scrambling in the scramble frequency selection circuit 201, and an embodiment will be described below. This selection pattern corresponds to the frequency table stored in the ROM 601 shown in FIG. 2C, and various scrambling can be performed by having a large number of this pattern.
An example of this pattern is shown in FIG. This FIG. 4 is shown in FIG.
Corresponds to the 8 × 8 DCT block in, and the pixels filled in black indicate the pixels that activate scrambling.

The pattern of FIG. 4 (A) is an example in which only the DC component is scrambled, and it is a very light scramble because it only changes the luminance value of the entire block. The pattern of FIG. 4B is an example of scrambling the low frequency part excluding the DC component, and the degree of scrambling is stronger than that of FIG. 4A.

The pattern of FIG. 4 (C) is an example of scrambling low-frequency components including DC components, and the scrambling is very highly concealed. The pattern of FIG. 4D is an example in which scrambling is applied only to the high frequency band. In the coding system using the inter-frame coding as in the present embodiment, when the signal having the inter-frame difference is coded, the high frequency band is coded. This is effective in this case because the level of the component is large.

The patterns of FIGS. 4 (E) and 4 (F) detect frequency components having energy exceeding a certain level,
This is an example of scrambling the detected frequency components. FIG. 4E shows a case of an image having a high correlation in the horizontal direction, and FIG. 4F shows an example of a pattern shown when an image having a high correlation in the vertical direction is input. .

FIG. 5 shows an example of a scramble frequency selection circuit to which a circuit for detecting the energy of such frequency components is added. Here, a level detection circuit 701 is provided instead of the ROM 601 of FIG. The output of the quantizer 104 of FIG. 1 is input to the level detection circuit 701, the level of each frequency component is detected based on the timing signal of the timing generation circuit 603, and when there is a level exceeding a certain level, The signal indicating that is given to the arithmetic circuit 6
Output to 02. The arithmetic circuit 602 outputs a signal for turning on the scramble based on this signal as described above.

From the viewpoint of scramble security, it is preferable that the scramble pattern as described above has several patterns rather than being uniquely determined. For example, in the pattern of FIG. 4C, a method of preparing some patterns in which the number and position of scrambling are changed and switching them arbitrarily or in an encoding device using interframe encoding as shown in FIG. A method of switching between the patterns of FIGS. 4C and 4D by the output of the intra switching circuit 110 may be used. Further, when the level detection circuit 701 as shown in FIG. 5 is used, even this alone can provide sufficiently high safety.

Next, FIG. 6 shows a block diagram of a decoder which receives a signal scrambled by using these scramble patterns and descrambles the signal. First, a video signal selected by a channel selection device (not shown) is input to the decoder from a terminal 901. The signal input from the terminal 901 is temporarily stored in the input buffer 902 and sequentially read by the variable length decoding circuit 903. The variable length decoding circuit 903 decodes the Huffman coded signal and outputs it to the subtractor 904 in the descramble circuit 920. Further, the header portion is input to the scramble control data extraction circuit 907, and information regarding scramble is extracted here. PN based on the data extracted here
The generation circuit 906 is controlled, and further, the AND circuit 905 is controlled to subtract the PN added to the signal to restore the original signal. The signal descrambled in this way returns to the signal in the time domain through the inverse quantization circuit 908 and the inverse DCT circuit 909, and when it is further encoded in the inter-frame, one frame before stored in the frame memory 911. Signal is added by the adder 910 and output from the terminal 912 to the monitor.

FIG. 7 shows a second embodiment of the present invention. Here, the same parts as those in FIG. 1 are designated by the same reference numerals and the same operation is performed. The control circuit for scrambling is also the same as the configuration of FIG. In this embodiment, the output of the quantizer 104 is the selector 100.
It is characterized in that a specific frequency is input to 7 and replaced with "0" by the control of the scramble control circuit.
This operation will be described below.

The control by the scramble frequency selection circuit 202 and the scramble block selection circuit 201 is the same as that of the first embodiment, so that it is omitted here. Similar to the first embodiment, when the frequency component to be scrambled among the blocks to be scrambled is input to the selector 1007, the control signal of the selector becomes active (“H”), and the variable length coding circuit 111 receives the signal. "0" is output.
On the contrary, the selector 1008 selects the output of the quantization circuit 104. This selection output is input to the adder 1006, where the PN from the AND circuit 205 is added, and this is input to the variable length coding circuit 111 as header information.

As the scramble frequency selection pattern used at this time, it is preferable to select pixels to be scrambled diagonally as shown in FIGS. 4 (G) and 4 (H). This is because the scanning order of the signals is obliquely converted when the Huffman coding is performed by the variable length coding circuit 111. That is, DC
The characteristic after DCT processing that the T-processed video signal is concentrated in the low frequency component and the high frequency component is almost "0" in many cases, and the Huffman coding is more compressed as the "0" portion continues. This is because the characteristic that it can be encoded at a rate is used for compression encoding. Therefore, FIG. 4 (G) and FIG.
When scrambling is performed diagonally as in (H), "0" continues in this part, so the compression rate increases, and the increase in the amount of information sent separately in the header part can be offset. It will be possible.

With such a configuration, the scrambled image is an image in which distortion occurs in each block because a certain specific frequency component is lacking. Although the concealment of the video is lower than that of the first embodiment, the security is similar, and such video is more likely to be effective especially when effect control is performed.

[0028]

As described above, according to the present invention,
It becomes possible to control the effect of scrambling in digital transmission with a relatively simple structure, and it is effective in promoting subscription to satellite broadcasting, CATV, and purchasing of pay programs.

[Brief description of drawings]

FIG. 1 is a diagram showing an encoder side in an embodiment of the present invention.

2 is a diagram of an example of DCT transform coefficients used in the circuit of FIG. 1, a scramble block selection circuit, and a scramble frequency selection circuit.

FIG. 3 is a diagram showing an example of a scrambled image.

FIG. 4 is an explanatory diagram showing an example of a selection pattern in a scramble frequency selection circuit.

FIG. 5 is a diagram showing another example of a scramble frequency selection circuit.

FIG. 6 is a diagram showing a decoder side in an embodiment of the present invention.

FIG. 7 is a diagram showing an encoder side according to another embodiment of the present invention.

FIG. 8 is a diagram showing a conventional scramble system.

[Explanation of symbols]

102 ... Subtractor, 103 ... DCT device, 104 ... Quantizer, 105 ... Inverse quantizer, 106 ... Inverse DCT device, 107
... adder, 108 ... frame memory, 109 ... motion compensator, 111 ... variable length encoder, 112 ... output buffer,
220 ... Scramble circuit, 201 ... Scramble block selection circuit, 202 ... Scramble frequency selection circuit,
203 ... PN generation circuit, 204, 205 ... AND circuit,
206 ... Adder, 902 ... Input buffer, 903 ... Variable length decoder, 904 ... Subtractor, 905 ... AND circuit, 9
06 ... PN generation circuit, 907 ... Scramble control data extraction circuit, 908 ... Inverse quantizer, 909 ... Inverse DCT device,
910 ... Adder, 911 ... Frame memory.

Claims (9)

[Claims] 1. A means for dividing an input image into blocks and performing a two-dimensional discrete cosine transform in a processing unit of the block, a quantizing means for quantizing the result at a certain quantizing step, A scramble system comprising a scrambler after the quantizer, wherein the scrambler selects a block to be scrambled and performs scrambling. 2. When the block is selected, it has a first control means for deciding an arbitrary area to be scrambled in the screen, and scrambles the block of the area selected by the first control means. The scramble system according to claim 1, wherein 3. When the block is selected, it has a second control means for determining which component in the block is to be scrambled, and scrambles the component designated by the second control means. The scrambling method according to claim 1, wherein the scrambling method is used. 4. When the block is selected, it has first control means for determining an arbitrary area to be scrambled in the screen, and when the block is selected, scrambled to which component in the block. To scramble the component selected by the first and second control means and having the second control means for determining whether to apply The scramble system according to claim 1, wherein 5. The scramble system according to claim 1, wherein the scramble means adds or subtracts pseudo random noise to the quantized output of the quantizer. 6. The scramble means replaces a specific component of the quantized output of the quantizer with "0",
Send to the variable length encoder in the next stage, and the certain component is
The scramble system according to claim 1, wherein the scramble method is transmitted as header information different from the original. 7. The scramble system according to claim 2, wherein the second control means has a plurality of control patterns, and these patterns can be arbitrarily switched. 8. The second control means comprises level detection means for detecting the level of an input signal, and scrambles only the portion determined to be above a predetermined level by the level detection means. The scramble system according to claim 3 or 4. 9. An input image is divided into blocks, a two-dimensional discrete cosine transform is performed in a processing unit of the block, the result is quantized, and a scramble target block is quantized from the quantized output. Scrambled and receiving means for receiving the scrambled signal, a signal including control information for recognizing the target block, and obtaining the control information from the reception output of the receiving and receiving means. An image decoding apparatus comprising: control information extracting means; and descrambling means for descrambling the received output based on the control information obtained from the control information extracting means.