JPH0779162A - Signal conversion circuit - Google Patents

Abstract

PURPOSE:To prevent deterioration in the conversion accuracy due to dispersion in the characteristic of components in the signal conversion circuit converting an input pulse signal into an analog signal based on its duty factor. CONSTITUTION:A control logic generating section 11 generates 1st-3rd control signals V1, V2, V3 based on an input pulse signal. An analog signal generating section 12 controls charge/discharge of a capacitor C0 according to the 1st control signal V, to provide a voltage V4 across the capacitor C0 at all times to an arithmetic operation section 14. A 1st sample-and-hold section 13 samples and holds a capacitor voltage (the voltage in this case is VT) when a current is constantly discharged from the capacitor C0 at a predetermined voltage CREF for one period of the input pulse signal according to the 2nd control signal V.. The arithmetic operation section 14 applies a predetermined arithmetic operation to the voltage VT and a voltage V4. A 2nd sample-and-hold section 15 samples and holds the arithmetic operation result of the arithmetic operation section 14 at the end of an H level of the input pulse signal according to the 3rd control signal V3 and provides the output of the resultant value as a converted value from the input pulse signal into an analog signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal conversion circuit for converting a pulse signal having an arbitrary duty ratio into an analog signal corresponding to the duty ratio.

[0002]

2. Description of the Related Art In recent years, in the control of various electric and electronic devices, the transition from analog control to digital control has progressed,
In the case of a device that drives with an analog signal,
Often digitally controlled. For example, when controlling the rotation speed of the DC power supply motor, it can be performed by using a pulse signal of a predetermined cycle as a control signal and changing the duty ratio of the pulse signal. Immediately before being input to the motor, the pulse signal is converted into an analog signal (for example, voltage) according to its duty ratio.
, And drive the motor with that voltage.

FIG. 8 shows a block diagram of an example of a signal conversion circuit for converting a pulse signal into an analog signal. In the figure, the input pulse signal is input to the “H” period counting circuit 1 and the 1-cycle counting circuit 4. And
"H" period counting circuit 1 and one cycle counting circuit 4
The respective voltages V _C1 and V _C2 output by the are input to the sample and hold circuits 2 and 5, respectively. Further, the voltage value V sampled and held by the sample and hold circuits 2 and 5
_h and V _t are input to the voltage / current conversion circuits 3 and 6, respectively. Subsequently, the voltage values V _h and V _t are converted into currents I _h and I _t by the voltage / current conversion circuits 3 and 6, respectively, and then input to the arithmetic circuit 7. Then, the arithmetic circuit 7 performs a predetermined arithmetic operation on the currents I _h and I _t and outputs the output voltage V _OUT which is the arithmetic operation result.

Next, the operation of the signal conversion circuit having the above configuration will be described.
This will be described together with the time chart shown in FIG. The "H" period counting circuit 1 includes a capacitor C ₁ having a capacitance of C _1.
And the capacitor C ₁ is charged, the output voltage of the “H” period counting circuit 1 becomes V _C1.
= V _REF (preset constant). In this state, when the input pulse signal is input to the "H" period counting circuit 1, the capacitor C ₁ The electric charge stored in the battery is discharged with a constant current I. After that, the capacitor C ₁ is charged again to the voltage V _REF . Here, the output voltage of the "H" period counting circuit 1 at the falling edge of the input pulse signal is given by the following expression (1).

[0005]

[Equation 1]

Then, the sample hold circuit 2 performs the above (1) at the timing of the falling edge of the input pulse signal.
Samples and holds the voltage V _h of the formula, and outputs the sample hold value V _h to the voltage-current conversion circuit 3. The voltage / current conversion circuit 3 converts the voltage V _h into a current represented by the following formula (2) and outputs it to the arithmetic circuit 7.

[0007]

[Equation 2]

On the other hand, the one-cycle counting circuit 4 has a capacitance of C
₂ has a capacitor C ₂ and the capacitor C ₂ is charged so that the one cycle counting circuit 4
_Has an output voltage of V _C2 = V _REF (the same as the value charged in the "H" period counting circuit 1). In this state,
When the input pulse signal is input to the 1-cycle counting circuit 4,
From that rising edge to the next rising edge,
That is, during one cycle (time T), the electric charge charged in the capacitor C ₂ is discharged by the constant current I, and then the capacitor C ₂ is charged to the voltage V _REF . Here, at the rising edge of the input pulse signal, the output voltage of the 1-cycle counting circuit 4 drops to the value of the following expression (3).

[0009]

[Equation 3]

Then, the sample-hold circuit 5 performs the above (3) at the timing of the rising edge of the input pulse signal.
The voltage V _t represented by the equation is sampled and held, and the sampled and held value V _t is output to the voltage / current conversion circuit 6. The voltage / current conversion circuit 6 converts the voltage V _t into a current represented by the following equation (4) and outputs it to the arithmetic circuit 7.

[0011]

[Equation 4]

[0012] calculation circuit 7, the (2) and (4) current I _h of the _formula, performs calculation according to the following equation (5) with respect to I _t, and outputs an output voltage V _OUT.

[0013]

[Equation 5]

Here, in the above equation (5), α and β
Is a constant for setting the change range of the voltage V _OUT output by the arithmetic circuit 7. Thus, the voltage V _OUT output from the arithmetic circuit 7 is, as shown in the above equation (5), the time t of the “H” period with respect to the time T of one cycle of the input pulse signal.
Of time, that is, it changes in an analog manner according to the duty ratio of the input pulse signal.

As an example, the output voltage V_OUT
To calculate. Input pulse signal frequency = 100 Hz (on
Force pulse signal period T = 10 ms), capacitor C₁Oh
And C₂Voltage V when charging_REF= 4V, voltage V_OUTStrange
Range = 1 to 3 V (α = 1.5, β = 1.0), capacitor
Sensor C₁And C₂Capacity = 0.1 μF, constant current during discharge
I = 20 μA, voltage / current conversion circuits 3, 6 and operation times
Resistance value R of the resistance of the path 7₁= R₂= R₃= 2 kΩ.
Under this condition, if the duty ratio of the input pulse signal is
If it is 10%, substitute t = 1ms into (5) above.
Output voltage V _OUT= 1.2V is obtained.

In this way, the conventional signal conversion circuit outputs the input pulse signal to the output voltage V according to its duty ratio.
The output was converted to _OUT and the output voltage was used to control the drive of the load.

[0017]

Under the above conditions, it is assumed that the capacity of the capacitor C ₁ of the "H" period counting circuit 1 is equal to the capacity of the capacitor C ₂ of the one-cycle counting circuit 4. However, in general, manufacturing variations of capacitors are not small, and it is rare that the capacitances of the _two capacitors C ₁ and C ₂ are exactly the same.

If the capacitances of the capacitors C ₁ and C ₂ vary, the duty ratio of the input pulse signal cannot be accurately detected, and as a result, the input pulse signal can be accurately converted into the output voltage V _OUT . Can not. For example,
Assuming that C ₁ = 1.1C ₂ , the output voltage V _OUT =
The voltage becomes 1.18 V, which causes an error compared with the case where C ₁ = C ₂ .

As described above, when a conventional signal conversion circuit is used to convert an input pulse signal into an output signal corresponding to its duty ratio, there is a problem that an error occurs in the output signal due to the characteristic variation of the capacitor. .

The present invention solves the above problem, and an object of the present invention is to prevent a decrease in conversion accuracy due to characteristic variations of parts in a signal conversion circuit for converting an input pulse signal into an analog signal corresponding to its duty ratio. And

[0021]

A signal conversion circuit according to the present invention has a control logic generation means, an analog signal generation means, a first sample hold means, a calculation means, and a second sample hold means.

The control logic generating means generates the first, second, and third control signals based on the input pulse signal. The analog signal generating means is composed of, for example, a capacitor and its capacitor charging / discharging means, and charges / discharges the capacitor according to the first control signal. The first sample and hold means samples and holds the analog value, for example, the voltage value output by the analog signal generating means, using the second control signal as a sample and hold timing pulse. The calculation means performs a predetermined calculation on the analog value output by the analog signal generation means and the value sample-held by the first sample-hold means. The second sample hold means samples and holds the output of the arithmetic means according to the third control signal and outputs the sample hold value.

According to the third aspect of the invention, control logic generating means for generating the first, second, and third control signals based on the input pulse signal, and analog according to the first control signal. Analog signal generating means for generating a signal, first sample and hold means for sampling and holding the analog value output by the analog signal generating means in accordance with the second control signal, and analog signal generating in accordance with the third control signal Second sample and hold means for sampling and holding the analog value output by the means, and computing means for performing a predetermined computation on the values sampled and held by the first and second sample and hold means. It may be configured to have.

[0024]

In the signal conversion circuit of the present invention, the duty ratio is obtained from the input pulse signal of two cycles. Hereinafter, the analog value generated by the analog signal generating means will be described as the voltage across the capacitor provided in the analog signal generating means.

In the first cycle of the input pulse signal, the analog signal generating means discharges the capacitor charged to the predetermined voltage V _REF with a constant current for one cycle time based on the first control signal. Then, the first sample and hold means samples and holds the voltage (V _T ) of the capacitor at the end of the first period based on the second control signal (this value V _T is the period of the input pulse signal). Depends on). After sample and hold, the capacitor is charged again to the voltage V _REF .

In the second cycle of the input pulse signal, the analog signal generating means generates the voltage V based on the first control signal.
_The capacitor charged in _REF is discharged by the constant current for a period when the input pulse signal is at "H" level (the circuit can be configured as "L" level instead of "H" level).

The voltage value (V _T ) sampled and held by the first sample and hold means and the voltage value of the capacitor which changes with time based on the first control signal are input to the arithmetic means. A predetermined calculation is always performed on these two voltage values. Then, the second sample hold means samples and holds the voltage value output by the calculating means at the end of the “H” level of the second cycle of the input pulse signal based on the third control signal.

Here, the voltage value of the capacitor at the end of the "H" level in the second cycle of the input pulse signal is a value determined by the time (pulse width) during which the input pulse signal is at the "H" level. Therefore, the value sampled and held by the second sample and hold means is based on the voltage (V _T ) of the capacitor at the end of the first cycle and the voltage value of the capacitor at the end of the “H” level in the second cycle. Since the calculation means is a value obtained by performing a predetermined calculation, the second
The voltage value output by the sample hold means is a value determined by the ratio of the period of the input pulse signal and the time when the input pulse signal is at the “H” level, that is, the duty ratio of the input pulse signal.

In the signal conversion circuit according to the third aspect, the analog signal generating means discharges the constant current from the capacitor charged to the predetermined voltage V _REF according to the first control signal. Then, the first sample and hold means samples and holds the voltage value of the capacitor when one cycle of the input pulse signal has elapsed from the time when the constant current discharge was started, in accordance with the second control signal, and the second sample and hold means. However, according to a third control signal, the voltage value of the capacitor when the “H” time of the input pulse signal has elapsed from the time when the constant current discharge was started is sampled and held, and the arithmetic means performs the above two sample hold values. Perform a predetermined calculation. With such a configuration, the duty ratio of the input pulse signal of one cycle can be obtained.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the signal conversion circuit of the present invention. In the figure, an input pulse signal having an arbitrary duty ratio is the control logic generation unit 1
Input to 1. The control logic generation unit 11 uses the input pulse signal to output the first to third control signals V ₁ , V ₂ ,
Generate V ₃ .

The first control signal V ₁ is output to the analog signal generator 12 as a charge / discharge command signal. In the analog signal generation unit 12, the capacitor charging / discharging unit 121
Of the capacitor C ₀ based on the first control signal V _1.
Control the charging and discharging of. Then, the analog signal generator 12
Outputs a voltage value determined according to the amount of electric charge stored in the capacitor C ₀ to the arithmetic unit 14 as the capacitor voltage V ₄ .

The second control signal V ₂ is used as a sample hold timing pulse by the first sample hold unit 1.
It is output to 3. First sample and hold unit 13
Is the capacitor voltage V ₄ of the analog signal generator 12,
The second control signal V ₂ in accordance with the timing (the capacitor voltage V ₄ at this timing and V _T) by sampling and holding, the sample hold voltage value V _T of the calculation unit 1
Output to 4. The calculation unit 14 uses the first control signal V
_A calculation (described later) is performed on the capacitor voltage V ₄ that changes with time according to ₁ and the sample hold voltage V _T, and the calculation result is output to the second sample hold unit 15 as an analog voltage V _ANA . To do.

The third control signal V ₃ is used as a sample hold timing pulse by the second sample hold unit 1.
It is output to 5. Second sample hold unit 15
Samples and holds the analog voltage V _ANA according to the third control signal V ₃ . The sample hold value is the output voltage V _{OUT obtained} by converting the input pulse signal into an analog voltage value.

Next, the operation of the signal conversion circuit having the above configuration will be described.
This will be described with reference to the time chart shown in FIG. Here, the period of the input pulse signal to the signal conversion circuit is T and T, and the time (pulse width) when the input pulse signal is at the “H” level is t. Moreover, since the signal conversion circuit of this embodiment is configured to detect the duty ratio of the input pulse signal of two cycles, the input pulse signal will be described as a repetitive signal of the pulse signals of the first and second cycles.

The control logic generator 11 starts from the rising edge of the first cycle of the input pulse signal (to be exact, after ΔT ₁ from the rising edge) to the rising edge of the second cycle (to be exact, after ΔT ₁ from the rising edge). ) time to (time T _1), and the second period of the rising edge (precisely,
From ΔT ₁ + ΔT ₂ after the rising edge) to the falling edge of the second cycle (more precisely, from the falling edge to ΔT ₂
The control signal V ₁ is generated such that the period (time t ₁ ) up to the latter) is at the “H” level and the other period is at the “L” level. Here, ΔT ₁ and ΔT ₂ are sufficiently smaller than the time T ₁ or t ₁ , and can be regarded as T ₁ = T (cycle of input pulse signal) and t ₁ = t (pulse width of input pulse signal).

Upon receiving the control signal V ₁ , the capacitor charging / discharging unit 121 of the analog signal generating unit 12 controls the control signal V 1.
_{When 1} is "H" level, the electric charge stored in the capacitor C ₀ is discharged by the constant current I, and when it is "L" level, the voltage across the capacitor C ₀ is charged to a predetermined value V _REF .
Therefore, the capacitor voltage V ₄ which is the voltage across the capacitor C ₀ is linearly V from the predetermined voltage V _REF during one cycle from the rising edge of the first cycle to the rising edge of the second cycle of the input pulse signal. It falls to _T and returns to the predetermined voltage V _REF at the rising edge of the second cycle. Subsequently, the capacitor voltage V ₄ is maintained for one pulse width from the rising edge of the second cycle to the falling edge of the second cycle,
It linearly drops from the predetermined voltage V _REF to V _H and returns to the predetermined voltage V _REF again at the falling edge of the second cycle.

Further, the control logic generator 11 generates the control signal V ₂ which generates a pulse at the rising edge of the second period of the input pulse signal. This control signal V ₂
Is a sample-hold timing pulse of the first sample-hold section 13, and the first sample-hold section 13 samples and holds the value of the capacitor voltage V ₄ at the rising edge of the second cycle, that is, the voltage V _T. , And outputs the sample-hold voltage V _T to the calculation unit 14.

The calculation unit 14 calculates the capacitor voltage V ₄ and the sample hold voltage V _T , and outputs the calculation result as an analog voltage V _ANA . This calculation is not particularly limited as long as a unique analog voltage V _ANA is output with respect to the input voltages V ₄ and V _T. An example of the calculation is shown.

[0039]

[Equation 6]

Here, the capacitor voltage V ₄ is a value that changes with time as shown in FIG. 2, and as a result, the analog voltage V _ANA also changes with time. The equations (6) to (8) can be calculated by the circuits shown in FIGS. 3 and 4, for example.

In FIG. 3, the capacitor voltage V ₄ (or V _T ) output from the analog signal generator 12 is converted into the current I.
₄ is a circuit diagram of a voltage / current conversion circuit for converting into ₄ ( _IT ). FIG. Further, FIG. 4 is a circuit for generating an analog voltage V _ANA from the currents I ₄ and I _T which are the outputs of the voltage / current conversion circuit. In FIG. 4, constants α and β are R ₄ R
It can be set by ₅ and the current value sent by the constant current source. Then, the constants α and β are changed to set the fluctuation range of the analog voltage V _ANA .

Returning to FIG. 1 and FIG. Control logic generator 1
1 also produces a control signal V ₃ which produces a pulse at the falling edge of the second period of the input pulse signal. This control signal V ₃ is applied to the second sample hold unit 1
5 sample and hold timing pulse, second
The sample-and-hold unit 15 of (1) samples and holds the analog voltage V _ANA output from the arithmetic unit 14 at the falling edge of the second cycle. Here, since the capacitor voltage V ₄ = V _H at the falling edge of the second cycle, the voltage value sampled and held by the second sample hold unit 15, that is, the voltage value output by the second sample hold unit 15. Is expressed by the following equation.

[0043]

[Equation 7]

The equation (9) has the same shape as the equation (5) shown as the prior art, but the equation (5) includes two capacitors (C _1, C ₂ ) for charging and discharging. On the other hand, in the equation (9), there is only one capacitor (C ₀ ). This is because in the signal conversion circuit of this embodiment, the period measurement of the input pulse signal and the pulse width measurement thereof are performed at the common portion. Therefore, these two measurements can be performed under the same conditions, and problems due to component variations (variations in capacitor capacitance) and the like do not occur.

In the above equation (9), if the pulse width value t with respect to the period T of the input pulse signal is changed, that is, if the duty ratio of the input pulse signal is changed, the voltage V _OUT changes. The voltage V _OUT controls a load such as a DC motor. Also, the voltage V _OUT can be fed back to an input pulse signal generator (not shown) to adjust its duty ratio.

Next, from the input pulse signal, the control signal V
FIG. 5 shows an example of a circuit that constitutes the control logic generator 11 that generates ₁ , V ₂ , and V ₃ . And the operation,
This will be described with reference to the time chart of FIG.

In FIG. 5, the input pulse signal is input to a rising delay 21 having a delay value ΔT ₁ , a falling delay 22 having a delay value ΔT ₂ , and a T flip-flop 23. The output signal A of the rising delay 21 is input to the T flip-flop 24, the rising delay 25 having a delay value of ΔT ₁ , and the inverter 26, and the output of the inverter 26 is input to the AND gate 29. The output signal B of the fall delay 22 is input to the AND gate 29 and the inverter 27, and the output of the inverter 27 is input to the R terminal of the SR flip-flop 28.

The T flip-flop 24 outputs the signal D, which is logically inverted at each rising edge of the signal A, to the OR gate 3.
2, AND gate 33, and output to the inverter 34. In addition, the rising delay 25 delays the rising edge of the signal A by ΔT ₁
It is input to the S terminal of the flip-flop 28. further,
The SR flip-flop 28 outputs the signal F to the OR gate 32 according to the logic of the signal input to the S and R terminals. Then, the logical sum of the signal D and the signal F is output from the OR gate 32 as the control signal V ₁ .

The T flip-flop 23 outputs a signal C for logically inverting each rising edge of the input pulse signal to the inverter 30, and the output of the inverter 30 is input to the AND gate 31. Also, AND gate 2
The output signal G of 9 is input to the AND gate 31. Further, the output signal H of the AND gate 31 changes to the AND gate 33.
And AND gate 35. And signal D
AND signal H is output from AND gate 33 as control signal V ₂ . On the other hand, a logical product of the signal H obtained by logically inverting the signal D by the inverter 34 and the signal H is output from the AND gate 35 as the control signal V ₃ .

As described above, in the signal conversion circuit of the present embodiment, in order to eliminate the influence of component variations and the like in the period measurement of the input pulse signal and the "H" level time measurement of the input pulse signal, These two measurements are performed by a common circuit (both using the analog signal generation unit 12). Therefore, the duty ratio can be accurately detected from the input pulse signal, and conversion into an analog value according to the duty ratio can be performed accurately.

Next, a signal conversion circuit according to another embodiment of the present invention will be described with reference to FIG. In the figure, the control logic generation unit 41 uses the first, second, and
And third control signals V ₁ ′, V ₂ ′, and V ₃ ′ are generated and output to the analog signal generation unit 42, the first sample hold unit 43, and the second sample hold unit 44, respectively. .

Here, the input pulse signal and the control signal V
₁ timing relationship between _{', V 2', V 3} ' may be similar to the timing relationship between the input signal shown in FIG. 2 and the control signals V _1, V _2, V _3. In this case, the analog signal generator 42 charges and discharges the electric charge stored in the capacitor or the like according to the control signal V ₁ '. Then, the first sample hold unit 43 samples and holds the voltage value V _T of the analog signal generation unit 42 determined by the input pulse signal 1 cycle time according to the control signal V ₂ ′, and the second sample hold unit 44 According to the control signal V ₃ ′, the voltage value V _H of the analog signal generator 42, which is determined by the “H” level time of the input pulse signal, is sampled and held.

The calculation section 45 responds to the output V ₄ '(V ₄ ' = V _T ) of the first sample hold section 43 and the output V ₅ (V ₅ = V _H ) of the second sample hold section 44. ,
The output voltage V at this time is calculated by the following formula (10).
Obtain the duty ratio of the input signal from _OUT .

[0054]

[Equation 8]

By the way, in the embodiment shown in FIG.
It is also possible to obtain the duty ratio of the input pulse signal for one cycle period. In this case, the first, the second, and the second generated by the control logic generation unit 41 based on the input pulse signal.
The third control signals V ₁ ′, V ₂ ′, and V ₃ ′ are shown in FIG.
The control signals V ₁ , V ₂ and V ₃ shown in FIG.

The control signal V ₁ 'outputs an "L" level pulse at each rising edge of the input pulse signal (to be exact,
The following control signal V ₂ 'after the pulse by), and the control signal V _2' outputs a "H" level at every rising edge of the input pulse signal pulse, the control signal V ₃ 'is the falling edge of the input pulse signal An "H" level pulse is output every time.

In the operation at this time, the rising edge of the input pulse signal is used as a trigger to linearly decrease the voltage value of the analog signal generator 42 (similar to the first cycle of FIG. 2). Then, the second sample hold unit 44 samples and holds the voltage value (V _H ) of the analog signal generation unit 42 at the falling edge of the input pulse signal according to the control signal V ₃ ′. The sample hold value V _H is a value corresponding to the “H” time of the input pulse signal. The first sample-and-hold unit 43 according to the control signal V ₂ ', samples and holds the voltage value of the analog signal generator 42 (V _T) at the time of the rising edge of the input pulse signal.
The sample hold value V _T is a value corresponding to one cycle of the input pulse signal. Then, the calculation unit 45 performs, for example, the calculation of the above formula (10) on the voltage values V _H and V _T , and outputs the output voltage V _OUT .

Although the "H" level time is measured as the pulse width of the input pulse signal in the two embodiments described above, the "L" level time may be measured.

Further, in the embodiment, the control signals V _1,
V _2, V ₃ (or the control signal V ₁ ', V _2',
V ₃ ') pattern is shown, but the present invention is not limited to this, and the period and the pulse width of the input pulse signal are measured using one analog signal generation circuit, and the period and the pulse width are measured. It suffices that the predetermined arithmetic operation is performed on the analog value based on the analog value and the arithmetic operation result is output as a conversion signal.

Further, although the analog signal generator shown in the embodiment controls charging / discharging of the capacitor and outputs the voltage value as an analog signal, the present invention is not limited to this, and the input pulse is not limited thereto. It includes all means for producing an analog signal in response to a signal.

[0061]

Since the signal conversion circuit of the present invention measures the period of the input pulse signal and the pulse width ("H" level time or "L" level time) of the pulse signal in the same circuit portion. , Each measurement can be performed under the same condition without being affected by the component variation. Therefore, the duty ratio of the input pulse signal can be accurately measured, and the accuracy of conversion into an analog signal according to the duty ratio is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a signal conversion circuit of the present invention.

FIG. 2 is a time chart for explaining a relationship between an input pulse signal, a control signal, and a voltage value generated by an analog signal generation unit in the signal conversion circuit shown in FIG.

3 is a circuit diagram showing an example of a voltage / current conversion circuit provided in the arithmetic unit shown in FIG.

FIG. 4 is a view showing one of arithmetic circuits provided in the arithmetic unit shown in FIG.
It is a circuit diagram which shows an example.

5 is a circuit diagram showing an example of a control logic generation unit shown in FIG.

FIG. 6 is a time chart explaining the operation of the control logic generation circuit shown in FIG.

FIG. 7 is a block diagram showing another embodiment of the signal conversion circuit of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional signal conversion circuit.

9 is a time chart explaining the relationship between an input pulse signal and a voltage value generated by the input pulse signal in the conventional signal conversion circuit shown in FIG.

[Explanation of symbols]

11 Control Logic Generation Section 12 Analog Signal Generation Section 121 Capacitor Charging / Discharging Section C ₀ Capacitor 13 First Sample Hold Section 14 Calculation Section 15 Second Sample Hold Section 41 Control Logic Generation Section 42 Analog Signal Generation Section 43 First Sample Hold unit 44 Second sample hold unit 45 Calculation unit

Claims (3)

[Claims] 1. A control logic generation means for generating first, second, and third control signals based on an input pulse signal, and an analog signal generation means for generating an analog signal according to the first control signal. A first sample and hold means for sampling and holding an analog value output by the analog signal generating means in accordance with the second control signal; an analog value output by the analog signal generating means; and a sample by the first sample and hold means And a second sample-hold means for sample-holding the output of the arithmetic means according to the third control signal and outputting the sample-hold value. A signal conversion circuit characterized by. 2. The analog signal generating means includes a capacitor and a capacitor charging / discharging means, and the capacitor charging / discharging means controls charging / discharging of the capacitor according to the first control signal. 1. The signal conversion circuit according to 1. 3. A control logic generating means for generating first, second, and third control signals based on an input pulse signal, and an analog signal generating means for generating an analog signal according to the first control signal. First sample-hold means for sampling and holding the analog value output by the analog signal generating means in accordance with the second control signal, and sample-holding analog value output by the analog signal generating means in accordance with the third control signal Signal conversion, comprising: a second sample-hold means for performing a predetermined operation on the values sampled and held by the first sample-hold means and the second sample-hold means. circuit.