JPH0776913B2 - Arithmetic logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial field of application) [0001] The present invention relates to an arithmetic logic operation circuit used in an operation unit or the like requiring high speed.

(Prior Art) Conventionally, an information processing apparatus such as a microcomputer is provided with an arithmetic logic operation circuit (ALU) that executes arithmetic operations or logical operations to process data.

FIG. 5 is a block diagram of an ALU conventionally used.
The ALU shown in FIG. 5 is a 2-bit ALU,
Arithmetic and logical operation of A ₀ and B ₀ is performed, and the arithmetic processing unit 1 of the 0th bit that gives the result as output F ₀ and arithmetic and logical operation of inputs A ₁ and B ₁ are performed, and the result is output as F _1. Give 1
It has an arithmetic processing unit 3 of the bit.

The arithmetic processing unit 1 includes a full adder (FA). The full adder 5 adds the logical operation result of the logical operation values of the control signals S ₀ , S ₁ , S ₂ for controlling the arithmetic logical operation and the inputs A ₀ , B ₀ to the inputs X ₀ , Y ₀
Then, the addition result is used as the output F ₀ of the full adder 5 as the arithmetic logic operation result of the inputs A ₀ and B ₀ .

The arithmetic processing unit 3 includes a full adder 7 and is configured similarly to the arithmetic processing unit 1. The arithmetic processing unit 1 receives inputs A ₁ and B _{1 from each} other.
Works the same as.

Further, the carry is given to the arithmetic processing unit 1 as the carry Cin, the carry is given to the arithmetic processing unit 3 from the upper arithmetic processing unit 1, and the carry of the arithmetic processing unit 3 is output as the carry Cout.

In such a configuration, ALU shown in Fig. 5, the control signals S _0, S _1, S ₂ in accordance with the arithmetic processing unit 1, 3, input A _0,
An arithmetic logic operation as shown in FIG. 6 is performed on B ₀ and inputs A ₁ and B ₁ . In FIG. 6, the logical level of the X mark may be "0" or "1" (do
n't care).

When an arithmetic logic operation as shown in FIG. 6 is performed with a plurality of bits, the carry operation on the lower bit side is considered in the arithmetic operation, but the carry operation is not considered in the logical operation. Therefore, as shown in FIG.
In the ALU in which the same full adder 5 performs the arithmetic operation and the logical operation, it is necessary to control the carry input by the arithmetic operation and the logical operation. That is, when performing a logical operation, the carry given to full adders 5 and 7 is forced to "0".
I have to

For this reason, the carry on the lower side is set to the A corresponding to each full adder 5, 7 using the inverted signal of the control signal S ₂ as one input.
Each full adder via ND (logical product) gates 9 and 11
I am trying to give it to 5,7. That is, when performing a logical operation, the control signal S _{2 is set} to the “1” level,
The output of each AND gate 9 and 11 is set to "0" level regardless of the logic level of the carry on the lower side.

(Problems to be Solved by the Invention) In the above configuration, when an arithmetic operation is performed, a carry on the lower side propagates to the upper side via an AND gate. Therefore, when an N-bit ALU is to be constructed, it is difficult to propagate the carry at high speed because N AND gates are serially connected. In particular, this becomes more remarkable when the number of bits to be processed is large.

Therefore, since the speedup of the ALU can be realized by speeding up the carry propagation, when the multi-bit input ALU is configured as shown in FIG.
There is a problem that it is very difficult to speed up the arithmetic processing.

Furthermore, in the past, since the presence or absence of carry propagation, which is a characteristic of arithmetic operations and logical operations, has not been effectively utilized, bit allocation of microcode that is a control signal for controlling arithmetic operations becomes complicated. However, there was a problem that it became difficult to control.

Therefore, the present invention has been made in view of the above, and an object thereof is to provide an arithmetic logic operation circuit that can be easily controlled and can achieve high-speed operation processing.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an arithmetic circuit that performs arithmetic processing common to arithmetic operations and logical operations of input information, and an output of the arithmetic circuit. In response to this, a logical operation is performed, and a logical operation result of the input information is output according to a control signal that determines the operation content of the input information, and an output of the operation circuit and a carry signal (carry signal provided from the lower side). ) And performs an arithmetic operation, outputs the arithmetic operation result of the input information according to the control signal, and gives a carry to the upper side in accordance with the arithmetic operation result.

(Operation) In the above configuration, the present invention separates the arithmetic operation processing and output path from the logical operation processing and output path,
The logical operation is performed regardless of the carry given from the lower side.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an arithmetic logic operation circuit according to an embodiment of the present invention. The arithmetic logic operation circuit (AL
U) is based on a Manchester-type adder circuit so that arithmetic and logical operation results can be obtained from different paths, and operation results obtained from these different paths can be selected and output. Therefore, the logical operation is performed regardless of the carry on the lower side.

In FIG. 1, the ALU inputs (A ₀ , B ₀ ) and (A ₁ , B ₁ )
And then, it is output for each input of a two-bit configuration for the F _0, F _1, a carry input and CIN, has a carry output Cout.

The ALU receives the inputs A ₀ and B ₀ and outputs the operation result as output F ₀ , and the 0-bit operation unit 15 receives the inputs A ₁ and B ₁ and outputs the operation result as output F ₁ Operation unit 17 and ALU
It is configured by a logic gate which controls the arithmetic processing of 1 to receive a control signal represented by MVA, MVB, XOR, CON, OR and AND, and supplies the control signal to the arithmetic units 15 and 17. The arithmetic unit 15 and the arithmetic unit 17 have the same configuration and function in the same manner, and the explanation of the arithmetic unit 17 will be omitted instead of the explanation of the arithmetic unit 15.

Next, with respect to the inputs A and B, FIG. 2 showing the outputs of the respective gate circuits and the carry logic constituting the operation units 15 and 17, and the outputs and functions of the operation units 15 and 17 for the respective control signals are shown. The configuration and operation of the calculation unit 15 will be described with reference to FIG. In FIG. 2, the * mark indicates that the carry on the lower side propagates to the upper side, and the X mark indicates “don't care” in FIG.

The arithmetic unit 15 includes exclusive OR (XOR) gates 21 and 23, a NAND gate (NAND) gate 25, and a NOR gate 27 that are commonly used for arithmetic operations and logical operations. There is.

Inputs A ₀ and B ₀ are given to XOR gate 21 and XOR gate 2
1 output has control signal CON applied to one input
It is supplied to the other input of the XOR gate 23. Therefore, X
The output a of the OR gate 23 is A ₀ B ₀ when the control signal CON is at “0” level (however, represents an exclusive OR), and when the control signal CON is at “1” level. , Becomes

The output of the XOR gate 23 is applied to the other input of a non-exclusive or (NXOR) gate 29 whose carry CIN is applied to one input. The output of the NOR gate 29 is given to a tri-state type inverting gate 31 which inverts and outputs the input signal, and its output is the output F of the arithmetic unit 15 as the arithmetic operation result of the inputs A ₀ and B ₀ including the carry CIN. It becomes ₀ . That is, XO
With R gates 21 and 23, NXOR gate 29 and inverting gate 31,
When the control signal is "0" level, the addition of the input A _0, B ₀ is performed, when the control signal is "1" level, the input A _0, B
Subtraction of ₀ is performed.

In such an arithmetic operation, a carry is generated by the transfer gate 35 and the carry generation circuit 37. The transfer gate 35 includes an N-channel FET (field effect transistor) (hereinafter referred to as “NFET”) 39 having a gate connected to the output of the XOR gate 23, and an inverting gate 41 for inverting the output of the XOR gate 23. P-channel FETs (hereinafter, referred to as "PFETs") connected to the output of the P-channel are connected in parallel with each other, and are inserted into the carry line 45 through which the carry is propagated, and the carry CIN is calculated by the operation unit 1
It becomes a gate to propagate to 7.

The carry generation circuit 37 has an output b and an input A ₀ of the inverting gate 41.
PF that receives the output d of the NAND gate 25 that receives
An ET47 and an NFET 49 that receives the output c of the NOR gate 27 whose input is the output of the XOR gate 23 and the input A ₀ are connected in series between the high voltage source and the low voltage source, and the connection point is a carry point. It is connected to the line 45 and configured, and the calculation unit 15
It is to generate a carry of the arithmetic operation performed in.

Such a transfer gate 35 and a carry generation circuit
37 is controlled by inputs A ₀ , B ₀ and outputs a, b, c, d of the respective gates which are determined by the control signal CON, whereby the carry output e of the arithmetic unit 15 is shown in FIG. Like

Next, a logical operation in the arithmetic unit 15 will be described.

The logical product of the inputs A ₀ and B ₀ is a tri-state inversion via the transfer gate 51 whose conduction is controlled by the control signal CON and the inverted signal of the output of the NAND gate 25 with the control signal CON set to “0” level. It is given to the gate 53 and obtained as the output of the inverting gate 33. The conduction of the inverting gate 53 is controlled by the control signal AND and its inverted signal.

The exclusive OR for the inputs A ₀ and B ₀ sets the control signal CON to “1”.
As a level, the output of the XOR gate 23 is inverted by the tri-state type inversion gate 55 and is obtained as the output of this inversion gate 55.

The logical sum of the inputs A ₀ and B ₀ is a tristate inversion via the transfer gate 57 whose conduction is controlled by the control signal CON and the inverted signal of the output of the NOR gate 27 with the control signal CON set to “0” level. It is given to the gate 59 and obtained as the output of the inverting gate 59.

Further, the control signal MVA is set to “1” level, and the input A ₀ is obtained through the tri-state type inversion gate 61 and the inversion gate 53 whose conduction is controlled by the inversion signal of the control signal AND, so that the input A ₀ is transferred. Are doing. Further, the control signal MVB as "1" level, by obtained via an inverting gate 63 and inverter gate 59 of the tri-state whose conduction controlled by the inverted signal of the control signal OR input B _0, the transfer of the input B ₀ Are doing.

The inverting gates 31, 53, 55, 59 that output the results of such arithmetic and logical operations are controlled by the control signals MVA, MVB, XOR, OR, AN.
Continuity is controlled according to D.

The inverting gate 53 is conductively controlled by the output of the OR gate 65, which receives the control signals MVA and AND, so that the output F ₀ has a calculation result as shown in FIG. The inverting gate 55 is conductively controlled by the control signal XOR and becomes conductive only when outputting the operation result of the exclusive OR. Inversion gate 59
Is controlled by the output of the OR gate 67 to which the control signal MVB, OR is input so that the output F ₀ has the calculation result shown in FIG. The inverting gate 31 is conductively controlled by the outputs of the OR gates 65 and 67 and the output of the NOR gate 69 to which the control signal XOR is input so that the inverting gate 31 becomes conductive only when the arithmetic operation result is output.

That is, by setting the respective control signals as shown in FIG. 3 and selecting the outputs of the respective inverting gates 31, 53, 55, 59, the arithmetic logic operation result for the inputs A ₀ , B ₀ is obtained. I am trying.

In this way, the output paths for the arithmetic operation and the logical operation are separated, and the logical operation is performed regardless of the carry given from the lower side. Therefore, a gate circuit for controlling the carry during the logical operation is unnecessary. . Thereby, the carry can be propagated at high speed, and the arithmetic operation can be performed at high speed.

Further, since the gate circuit for performing the logical operation and the arithmetic operation is partially shared for simplification, it is possible to reduce the number of elements and speed up the arithmetic processing.

Furthermore, the bit structure of the control signal for controlling the arithmetic operation can be decoded at high speed, and the bit structure of the control signal for controlling the logical operation which does not require relatively high-speed processing is complicated. Bits can be assigned. As a result, as shown in FIG.
When decoding the control signal with a 1-clock signal,
As compared with the conventional method, the arithmetic processing can be performed at a high speed with a large margin.

Furthermore, by applying the inputs A ₀ , B ₀ and the inputs A ₁ , B ₁ to the arithmetic units 15 and 17 via the selector circuit, F = A, F = B, F
= A + 1, F = B + 1, etc. can be obtained,
Further, the calculation function can be diversified. In addition, the carry look-ahead circuit (CLA, Carry Look
A head) makes it possible to further speed up the arithmetic processing.

[Effects of the Invention] As described above, according to the present invention, the arithmetic operation processing and output path and the logical operation processing and output path are separated, and the logical operation is performed without the carry given from the lower side. Since this is done, it is not necessary to provide the carry given from the lower side to the upper side by performing different control during arithmetic operation and during logical operation. As a result, the carry can be propagated at high speed, and it is possible to provide an arithmetic and logic operation circuit that is easy to control and performs arithmetic processing at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an arithmetic logic operation circuit according to an embodiment of the present invention, FIGS. 2 and 3 are explanatory views of the operation of the circuit shown in FIG. 1, and FIG. 4 is a circuit diagram shown in FIG. FIG. 5 is a timing chart of a conventional arithmetic logic operation circuit, FIG. 5 is a configuration diagram showing an example of a conventional arithmetic logic operation circuit, and FIG. 6 is an operation explanatory view of the circuit shown in FIG. 15,17 ...... Arithmetic processing unit 21,23 ...... Exclusive OR gate 25 …… Negative AND gate 27 …… Negative OR gate 29 …… Negative exclusive OR gate 31,53,55,59 …… Inverting gate 35,51,57 …… Transfer gate 37 …… Carry generating circuit A ₀ , B ₀ , A ₁ , B ₁ …… Input data CIN, MNA, MVB, XOR, CON, OR, AND …… Control signal

Claims (1)

[Claims] 1. A Manchester-type arithmetic logic operation circuit in which a carry signal is propagated to an upper side to perform an arithmetic operation, and an operation circuit which performs an operation process common to an arithmetic operation or a logical operation of input information, and an operation circuit. Performs a logical operation based on the operation result of, and selects and outputs the logical operation result based on the control signal indicating the operation content, and the operation result of the operation circuit and the carry signal given from the lower side to perform the arithmetic operation. An arithmetic logic operation circuit which performs an operation, selectively outputs an arithmetic operation result based on a control signal indicating an operation content, and gives a carry signal to the upper side in accordance with the arithmetic operation result. .