JPH077690U - Power supply over detection circuit for gaming machines - Google Patents
Power supply over detection circuit for gaming machinesInfo
- Publication number
- JPH077690U JPH077690U JP4290693U JP4290693U JPH077690U JP H077690 U JPH077690 U JP H077690U JP 4290693 U JP4290693 U JP 4290693U JP 4290693 U JP4290693 U JP 4290693U JP H077690 U JPH077690 U JP H077690U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- circuit
- detection circuit
- supply voltage
- supply over
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pinball Game Machines (AREA)
Abstract
(57)【要約】
【目的】 パチンコ機等の遊技機において、電源電圧が
所定値を超えたことの検出を安定化させる。
【構成】 電源電圧が所定値を超えると、コンデンサー
Cと抵抗R1による時定数回路で定まる時間の経過後に
オペアンプ13の出力が反転し、論理回路14からこれ
を示す信号が出力される。この信号がバス6を介してC
PU1等に入力され、これによってCPU1等が所定の
動作を行なうか、あるいは動作を停止する。
(57) [Summary] [Purpose] In gaming machines such as pachinko machines, stabilize the detection that the power supply voltage exceeds a specified value. [Structure] When the power supply voltage exceeds a predetermined value, the output of the operational amplifier 13 is inverted after a lapse of time determined by the time constant circuit formed by the capacitor C and the resistor R1, and the logic circuit 14 outputs a signal indicating this. This signal is sent via bus 6 to C
The data is input to the PU 1 or the like, whereby the CPU 1 or the like performs a predetermined operation or stops the operation.
Description
【0001】[0001]
本考案は遊技機の電源オーバー検出回路に関し、特に遊技機における電源異常 の検出を安定的に行なえるようにしたもの関する。 The present invention relates to a power supply over detection circuit for a game machine, and more particularly to a power supply over detection circuit for a game machine capable of stably detecting a power supply abnormality.
【0002】[0002]
近年パチンコ機等の遊技機においては、遊技機本体の動作や、表示の制御にマ イクロコンピュータを応用した制御装置が用いられている。このような制御装置 では、CPUその他各電子回路に印加される電源電圧(一般に+5V)の変動、 特に電圧のオーバーが、各電子回路の誤動作を招くなど種々問題があるため、電 源電圧の監視、検出が非常に重要となっている。 In recent years, in gaming machines such as pachinko machines, control devices that use a micro computer have been used to control the operation of the gaming machine body and display. In such a control device, fluctuations in the power supply voltage (generally +5 V) applied to the CPU and other electronic circuits, especially overvoltage, causes various problems such as malfunction of each electronic circuit. , Detection has become very important.
【0003】 従来よりこのような電源オーバー検出については種々の技術が用いられている が、本考案は電源異常の検出をより安定的に行なえる手段を提供しようとするも のである。Conventionally, various techniques have been used for such power supply over-detection, but the present invention aims to provide means for more stable detection of power supply abnormality.
【0004】[0004]
本考案に係る遊技機の電源オーバー検出回路は上記目的を達成するために、パ チンコ機等の遊技機において、電源電圧が所定値を超えたことを検出して遊技機 本体の動作、表示等を制御する制御装置に対し所定の異常検出信号を送出する手 段と、該信号送出手段による信号送出を所定時間だけ遅延させる手段とを備える ようにしたものである。 In order to achieve the above-mentioned object, the power supply over detection circuit of the gaming machine according to the present invention detects the power supply voltage exceeding a predetermined value in a gaming machine such as a pachinko machine and operates and displays the gaming machine body. A means for sending out a predetermined abnormality detection signal to the control device for controlling the above and a means for delaying the signal sending out by the signal sending means by a predetermined time are provided.
【0005】[0005]
以下本考案の実施例を図面を参照して説明する。図1は本考案に係る電源オー バー検出回路の一実施例をパチンコ機を制御するマイクロコンピュータ応用回路 に適用した例を示す。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example in which an embodiment of a power supply over detection circuit according to the present invention is applied to a microcomputer application circuit for controlling a pachinko machine.
【0006】 図中1はCPUで、2はROM、3はアドレスデコーダ、4は入力回路、5は 複数のラッチ回路からなる出力回路であり、これらはバス6によって接続されて いる。入力回路4、出力回路5にはパチンコ機本体7側のドライバ回路や、表示 器、センサー等が接続される。またバス6には音響制御回路8が接続され、その 出力はパチンコ機本体7に配する音響回路9が接続されている。さらにCPU1 に対して定期的にリセットをかける定期リセット回路10と、出力回路5に対し て電源投入時にリセットをかける初期化リセット回路11も備えている。In the figure, 1 is a CPU, 2 is a ROM, 3 is an address decoder, 4 is an input circuit, 5 is an output circuit consisting of a plurality of latch circuits, and these are connected by a bus 6. The input circuit 4 and the output circuit 5 are connected to a driver circuit on the pachinko machine body 7 side, an indicator, a sensor, and the like. An acoustic control circuit 8 is connected to the bus 6, and an output of the acoustic control circuit 8 is connected to an acoustic circuit 9 arranged in the pachinko machine body 7. Further, a periodic reset circuit 10 for periodically resetting the CPU 1 and an initialization reset circuit 11 for resetting the output circuit 5 when the power is turned on are also provided.
【0007】 バス6にはさらに電源オーバー検出回路12が接続されている。この回路は、 非反転入力端子に正帰還をかけたオペアンプ13を備える。オペアンプ13の非 反転入力端子には+5vの電源に接続する抵抗R1とツェナーダイオードZDと によって作り出された基準電圧がかかり、反転入力端子には同じく+5vの電源 に接続する抵抗R2、R3によって分割された電圧がかかっている。またオペア ンプ13の非反転入力端子には抵抗R4、R5を介して+5vの電源が印加され 、これによる電圧が帰還電圧に加えて印加されている。さらにオペアンプ13の 出力には論理回路14が接続され、この論理回路14の出力はバス6に接続され ている。A power supply over detection circuit 12 is further connected to the bus 6. This circuit includes an operational amplifier 13 in which positive feedback is applied to the non-inverting input terminal. The non-inverting input terminal of the operational amplifier 13 receives the reference voltage generated by the resistor R1 and the Zener diode ZD connected to the + 5v power source, and the inverting input terminal is divided by the resistors R2 and R3 also connected to the + 5v power source. The voltage is on. Further, a + 5v power source is applied to the non-inverting input terminal of the operational amplifier 13 via the resistors R4 and R5, and the resulting voltage is applied in addition to the feedback voltage. Further, the output of the operational amplifier 13 is connected to the logic circuit 14, and the output of the logic circuit 14 is connected to the bus 6.
【0008】 さらにオペアンプ13の非反転入力端子側に接続するコンデンサーCは、抵抗 R1とともに時定数回路を形成しており、電源電圧が変化した場合にその変化が オペアンプ13の非反転入力にかかるのを所定時間遅らせることができるように なっている。もちろん遅延時間はコンデンサーCと抵抗R1の値を適宜選定する ことによって変えることができる。Further, the capacitor C connected to the non-inverting input terminal side of the operational amplifier 13 forms a time constant circuit together with the resistor R1, and when the power supply voltage changes, the change is applied to the non-inverting input of the operational amplifier 13. Can be delayed for a predetermined time. Of course, the delay time can be changed by appropriately selecting the values of the capacitor C and the resistor R1.
【0009】 この電源オーバー検出回路12においては、オペアンプ13がシュミットトリ ガ動作を行なうことになり、電源電圧が+5vを超えると、コンデンサーCと抵 抗R1による時定数回路で定まる時間の経過後にオペアンプ13の出力は反転低 下し、論理回路14からは電源電圧が+5vを超えたことを示す信号が出力され 、これがバス6を介してCPU1等に入力され、これによってCPU1等が所定 の動作を行なうか、あるいは動作を停止することになる。もちろんパチンコ機本 体7や音響回路9はCPU1等の動作あるいは動作停止によって制御される。即 ち、+5vの電源電圧の変動が即座にパチンコ機の制御回路に対して影響を及ぼ さず、電源電圧の変動が一定の時間を経過しても続く状態において検出されるこ とになり、電源オーバーの検出に誤動作が生じにくくなり安定する。In the power supply over detection circuit 12, the operational amplifier 13 performs a Schmitt trigger operation, and when the power supply voltage exceeds + 5v, the operational amplifier is operated after a lapse of time determined by the time constant circuit formed by the capacitor C and the resistor R1. The output of 13 is inverted and lowered, and a signal indicating that the power supply voltage has exceeded + 5v is output from the logic circuit 14 and is input to the CPU 1 and the like via the bus 6, whereby the CPU 1 and the like perform a predetermined operation. You will either perform or stop the operation. Of course, the pachinko machine body 7 and the acoustic circuit 9 are controlled by the operation or stop of the operation of the CPU 1 and the like. Immediately, the fluctuation of the power supply voltage of + 5v does not immediately affect the control circuit of the pachinko machine, and the fluctuation of the power supply voltage is detected even after a certain period of time. It is stable because the malfunction does not occur in the detection of power over.
【0010】 なお以上の説明においては本考案の実施対象をパチンコ機としているが、本考 案はこれに限定されず、スロットマシン等と称される他の種類の遊技機において も適用できる。また電源オーバー検出回路の回路構成は単なる一例であり、本考 案の回路がこれに限定されることはなく、電源異常の検出や検出信号の送出を遅 延させる手段として用いることができる者であれば適宜採用できるものである。In the above description, the object of implementation of the present invention is a pachinko machine, but the present invention is not limited to this, and can be applied to other types of gaming machines called slot machines and the like. Moreover, the circuit configuration of the power supply over detection circuit is merely an example, and the circuit of the present invention is not limited to this, and it can be used by a person who can be used as a means for delaying the detection of a power supply abnormality or the transmission of the detection signal. If there is one, it can be appropriately adopted.
【0011】[0011]
請求項1に係る遊技機の電源オーバー検出回路は以上説明してきたように、遊 技機本体の動作、表示等を制御する制御装置にかかる電源電圧が所定値を超えた ことを検出して送出する所定の異常検出信号を所定時間だけ遅延させて送出する 構成としたので、制御装置にかかる電源電圧が所定値をオーバーした場合、その 変動が所定時間に渡って続く状態で初めて検出されることになり、電源オーバー の検出を非常に安定化させるようになるという効果がある。 As described above, the power supply over detection circuit of the gaming machine according to claim 1 detects that the power supply voltage applied to the control device that controls the operation, display, etc. of the gaming machine exceeds a predetermined value and sends it out. Since the specified abnormality detection signal is sent after delaying for a specified time, if the power supply voltage applied to the control device exceeds a specified value, the fluctuation must be detected for the first time in a state where it continues for a specified time. Therefore, there is an effect that the detection of power supply over becomes extremely stable.
【図1】本考案に係る電源オーバー検出回路の一実施例
をパチンコ機を制御するマイクロコンピュータ応用回路
に適用した例を示す回路ブロック図である。FIG. 1 is a circuit block diagram showing an example in which an embodiment of a power supply over detection circuit according to the present invention is applied to a microcomputer application circuit for controlling a pachinko machine.
1 CPU 2 ROM 3 アドレスデコーダ 4 入力回路 5 出力回路 6 バス 7 パチンコ機本体 8 音響制御回路 9 音響回路 10 定期リセット回路 11 初期化リセット回路 12 電源オーバー検出回路 13 オペアンプ 14 論理回路 1 CPU 2 ROM 3 Address Decoder 4 Input Circuit 5 Output Circuit 6 Bus 7 Pachinko Machine Main Body 8 Acoustic Control Circuit 9 Acoustic Circuit 10 Periodic Reset Circuit 11 Initialization Reset Circuit 12 Power Over Detection Circuit 13 Operational Amplifier 14 Logic Circuit
Claims (1)
圧が所定値を超えたことを検出して遊技機本体の動作、
表示等を制御する制御装置に対し所定の異常検出信号を
送出する手段と、該信号送出手段による信号送出を所定
時間だけ遅延させる手段とを備えたことを特徴とする遊
技機の電源オーバー検出回路。1. In a gaming machine such as a pachinko machine, the operation of the gaming machine body is detected when the power supply voltage exceeds a predetermined value.
A power supply over detection circuit for a gaming machine, comprising means for sending a predetermined abnormality detection signal to a control device for controlling display and the like, and means for delaying signal sending by the signal sending means by a predetermined time. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4290693U JPH077690U (en) | 1993-07-09 | 1993-07-09 | Power supply over detection circuit for gaming machines |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4290693U JPH077690U (en) | 1993-07-09 | 1993-07-09 | Power supply over detection circuit for gaming machines |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH077690U true JPH077690U (en) | 1995-02-03 |
Family
ID=12649080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4290693U Pending JPH077690U (en) | 1993-07-09 | 1993-07-09 | Power supply over detection circuit for gaming machines |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH077690U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001096041A (en) * | 1999-10-01 | 2001-04-10 | Sankyo Kk | Game machine |
-
1993
- 1993-07-09 JP JP4290693U patent/JPH077690U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001096041A (en) * | 1999-10-01 | 2001-04-10 | Sankyo Kk | Game machine |
JP4565682B2 (en) * | 1999-10-01 | 2010-10-20 | 株式会社三共 | Game machine |
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