JPH077597B2 - Memory cell and superconducting memory circuit using the same - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a superconducting memory circuit having a memory cell using a Josephson device.

[Background of the Invention]

The Josephson device is expected to be a future computer device due to its low power consumption and ultra-high speed operation. Various circuit types have been proposed for the Josephson device. Among them, the DC magnetic flux parametron circuit (DC
The power consumption of Flux Parametron Circuit (DCFP circuit, hereinafter) is extremely small, 1/1000 of that of the conventional Josephson circuit, and the switching speed can be expected to be 10ps or less. Its performance exceeds that of the conventional Josephson circuit. The basic form of the DCFP circuit is disclosed in JP-A-59-139728. The application range of DCFP circuits is extremely wide, and can be applied to logic circuits and memory circuits. An example of applying a DCFP circuit to a memory cell is Goto et al., RIKEN symposium “Josephson Electronics” pages 96-102 (March 16, 1984).
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FIG. 1 is a principle configuration diagram of a memory cell using a DCFP circuit. This memory cell has two Josephson junction elements 101,
DCFP consisting of series loop of 102 and inductors 103, 104
Circuit, Josephson junction element 201, inductors 202, 203
A load circuit 200 in which the load circuits 200 are connected in series is connected. Here, by the inductor 203 and the constant current source,
It constitutes a DC bias current source.

This load circuit 200 is a quantum interference circuit (AC-SQUID), and the magnetic flux interlinking via the inductor 203 is one of the quantum magnetic flux.
When the current value of the constant current source 204 is set to be / 2 (π as the magnetic flux phase angle), the memory operation is performed through the magnetic flux. The stored information can be discriminated by the directions a and b of the current flowing out of the quantum interference circuit 200. For details of the quantum interference circuit, see page 99 of the Premises Manual.

The DCFP circuit serves as a sense amplifier for the quantum interference circuit. When a current in the direction of C is passed through the selection line 105, the current flowing through the Josephson junction element 102 increases and enters a voltage state when the current from the quantum interference circuit 200 is in the direction of a.
On the other hand, when the current from the quantum interference circuit 200 is in the low direction, the current flowing through the Josephson junction element 101 increases and enters a voltage state. As a result, a large current excited by the current of the select line 105 flows in the direction a or the direction b.

Reading and writing of information from the memory cell is performed by providing a data line magnetically coupled to the inductor 202.

When reading information, apply a current to the select line 105
By exciting the circuit, the magnetic flux in inductor 202 is increased and read on the data line.

In the case of information writing, the information of the quantum interference circuit 200 is stored by passing the information desired to be written in the data line in the direction of the current while the current is not passed through the selection line 105.
The memory cell using the DCFP circuit according to the prior art shown here has a drawback that it causes circuit resonance during the switching operation because it is composed of an inductor and a Josephson junction, which causes a malfunction of the memory cell. In addition, the load circuit 200 in which the inductors 202 and 203 and the Josephson junction 201 are connected in series has a large impedance, and a large output current cannot be obtained from the memory cell.

[Object of the Invention]

An object of the first invention of the present application is to provide a memory cell using a DCFP circuit that suppresses a resonance phenomenon and can extract a large output current.

An object of the second invention of the present application is to provide a highly integrated superconducting memory circuit.

[Outline of Invention]

In order to achieve the above object, in the first invention of the present application, a damping resistor for suppressing resonance is inserted in a memory cell using a DCFP circuit. Further, in the second invention of the present application, a phase wiring is separately provided to realize a highly integrated superconducting memory circuit.

Example of Invention

FIG. 2 shows a first embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, damping resistors 110, 111 and 210 are connected in parallel to the Josephson junction elements 101, 102 and 201, respectively. By connecting these three damping resistors, the resonance energy can be dissipated and the oscillation phenomenon can be suppressed.

FIG. 3 shows a second embodiment of the first invention of the present application. The same parts as those in FIG. 2 are designated by the same reference numerals. In this embodiment, a load inductor 300 is additionally connected in parallel to the quantum interference circuit 200 in the circuit shown in FIG. With this circuit configuration, the load impedance of the DCFP circuit as a whole can be lowered and the output current can be increased. The memory operation is performed by the quantum interference circuit 200, and the memory information amplified by exciting the DCFP circuit can be taken out to the outside via the load inductor 300. Writing is also done through the load inductor without exciting the DCFP circuit.

FIG. 4 shows a third embodiment of the first invention of the present application. The same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, instead of the DC bias current source (inductor 203, constant current source 204) shown in FIG. 3, a common DC bias current source that supplies a current whose phase is deviated from the baseline 150 by π, and phase wiring 400 is installed, and the quantum interference circuit 200 'is connected to the phase wiring 400. The phase wiring 400 is also connected to a quantum interference circuit of another memory cell (not shown) and has a configuration for sharing the DC bias current source 500. In a memory circuit using such memory cells, a plurality of memory cells are arranged in a matrix and the phase wiring 400 is commonly connected to all the memory cells. In this case, in order to reduce the inductor of the phase wiring 400, the wiring 400 is installed as a planar phase plane. The memory cell 600 shown in FIG. 4 was used. A preferred superconducting memory circuit embodiment is shown in FIG. FIG. 5 is a diagram showing a configuration of a memory circuit using a plurality of memory cells 600a, 600b, 600c, 600d ... As an embodiment of the second invention of the present application. Each memory cell is arranged in a matrix. Each memory cell has a baseline of 15
It is tangent to 0 and the phase wiring 400. The phase wire 400 and the base line 150 are connected via a phase inductor 501, and a constant current flows from the constant current source 500 to the phase inductor. The value of the constant current flowing from the constant current source 500 is set so that the phase between the phase wiring 400 and the base line 150 becomes π. The output current of each memory cell is read out via the bit lines 601A, 601B, 601C ....

FIG. 6 shows another preferred embodiment of the superconducting memory circuit according to the second invention of the present application. In this embodiment, offset resistances 700a, 700b, 700c, 700d ... Are provided for each memory cell of the memory circuit shown in FIG. 5, and the other end of the offset resistance is connected to a positive power source 703 via offset lines 701, 702. Alternatively, it is connected to the negative power source 704. Each memory cell 600a-d has a configuration in which an offset current is supplied through a corresponding offset resistance 700a-d. According to this configuration, each memory cell 600a ~
For example, an offset current corresponding to the difference between the maximum superconducting currents of the two Josephson junctions of d can be applied to cancel the variation in the device characteristics of the Josephson junctions. That is, it is possible to cancel the element variation of the memory cell and form a high gain circuit. For this purpose, it is necessary to determine the value of the offset resistance of each memory cell and the connection method of the power supply in accordance with the characteristics of the elements constituting each memory cell, and use a current source for supplying a desired offset current. For this purpose, a trimming method using a laser or the like can be used. The trimming method is used to select the resistance value of the offset resistance and the connection to the positive and negative power supplies.

In the embodiment shown in FIG. 6, the offset resistance is used to determine the offset current, but it is obvious that other inductors can be used.

〔The invention's effect〕

According to the first invention of the present application, the resonance phenomenon of a memory cell using a DCFP circuit can be suppressed, and a large output current can be obtained from the memory cell. Therefore, the operation of the memory cell is stable and a wide operation margin can be realized. Also, the structure of the memory cell can be simplified. Further, according to the second invention of the present application, it is possible to realize a highly integrated superconducting memory circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a memory cell using a DCFP circuit according to the prior art, FIG. 2 is a diagram showing a first embodiment of the first invention of the present application with a damping resistor inserted, and FIG. The figure which shows the 2nd Example of this invention 1st invention in which the load inductor was inserted, FIG. 4 is the figure which shows 3rd Example of this invention 1st invention which installed the phase wiring, FIG. 5 is this application FIG. 6 is a diagram showing a configuration example of a preferable memory circuit according to the second invention, and FIG. 6 is a diagram showing another configuration example of a preferable memory circuit according to the second invention of the present application. 101,102,201 …… Josephson junction, 103,104 …… Inductor, 200 …… Quantum interference circuit, 202,20
3 ... Inductor, 204 ... Constant current source, 110, 111, 210 ...
Damping resistance, 300 ... Load inductor, 105 ... Selection line, 150 ... Baseline, 400 ... Phase wiring, 600 ... Memory cell, 601, ... Bit line, 501 ... Phase inductor, 500 ...
… Constant current source, 700a-d …… Offset resistance, 701,702…
… Offset line, 703 …… Positive power supply, 704 …… Negative power supply.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiichi Goto 2-1, Hirosawa, Wako-shi, Saitama RIKEN (72) Inventor Nobuo Miyamoto 1-280, Higashi Koigakubo, Kokubunji, Tokyo Hitachi Central Research Institute In-house

Claims (5)

[Claims] 1. A first circuit configured by connecting first and second Josephson junction elements and first and second excitation inductors in a loop, and the first and second excitation inductors. A selection line magnetically coupled to the second circuit, which is connected to the connection point of the first and second excitation inductors and in which a third Josephson junction element and a third inductor are connected in series; A memory cell having a DC bias current source connected to the second circuit, wherein a resistance element is connected in parallel to the third Josephson element. 2. A memory cell according to claim 1, wherein a load inductor is provided in parallel with the second circuit. 3. The memory cell according to claim 1, wherein the DC bias current source is an inductor connected in series to the second circuit, and a current source magnetically coupled to the inductor. A memory cell comprising: 4. A first circuit configured by connecting first and second Josephson junction elements and first and second excitation inductors in a loop, and the first and second excitation inductors. A selection line magnetically coupled to the second circuit, which is connected to the connection point of the first and second excitation inductors and in which a third Josephson junction element and a third inductor are connected in series; A load inductor connected between a connection point of the first and second excitation inductors and a connection point of the first and second Josephson junction elements, and connected in parallel to the third Josephson junction element Memory cells having the resistive elements arranged in a matrix are arranged, and the other end of the second circuit of each memory cell arranged in the matrix is connected to a common current source. Connection of 1st and 2nd Josephson junction elements A point is connected to the other end of the phase inductor connected to the common current source, and a data line for reading and writing data is provided by being coupled to the load inductor of each memory cell. . 5. The superconducting memory circuit according to claim 4, wherein each of the memory cells has a maximum of first and second Josephson junctions at a connection point of the first and second excitation inductors. A superconducting memory circuit, characterized in that an offset current source for flowing an offset current corresponding to a difference in superconducting current is connected.