JPH0775394B2 - Image transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a plurality of image processing devices are connected by a transmission line,
The present invention relates to an image transmission device that transmits and receives compressed image data between a plurality of image processing devices via the transmission path.

In recent years, a digital image is read by a photoelectric conversion element such as a solid-state image sensor such as a CCD, converted into digital image data, subjected to image processing, transmitted through a digital transmission line, and then reproduced by a laser beam printer or the like. Copiers and fax machines are being considered.

In such a device, when the device on the image data transmitting side performs the enlarging process or the resolution improving process, the data amount of the image data to be transmitted increases.
The occupancy time of the transmission line becomes long, and the utilization efficiency of the transmission line is deteriorated. Further, when the device on the image data receiving side performs reduction processing or resolution reduction processing, unnecessary image data is transmitted on the transmission line by the device on the receiving side. Is making poor use of.

Therefore, the reception side device performs the enlargement process and the resolution improvement process, and the transmission side device performs the reduction process and the resolution reduction process to prevent an increase in the data amount of the image data transmitted on the transmission path. Or it is possible to reduce. However, providing a dedicated configuration for these processes complicates the apparatus configuration and is not preferable in terms of cost.

The present invention has been made in view of the above points, and at the time of image scaling processing and resolution conversion processing, an increase in the data amount of image data transmitted on a transmission path is prevented or reduced.
For the purpose of enabling execution with a simple configuration, more specifically, an image in which a plurality of image processing devices are connected by a transmission line and compressed image data is exchanged between the plurality of image processing devices through the transmission line. In the transmission device, the image processing device on the transmission side reads the image line by line and outputs the read image data and the read line synchronization signal, and the image data output from the reading unit according to the read line synchronization signal. The reading unit includes a compression unit that performs a compression process for each line, and a gate unit that thins out the read line synchronization signal output from the reading unit according to a reduction rate or a resolution reduction rate and inputs the thinned signal to the compression unit. Each time a plurality of lines of image data are output from the above, the compression means performs a compression process on one line of image data, and is output from the reading means. By thinning out the image data in units of lines and performing compression processing, reduction processing or resolution reduction processing is executed together with the compression processing for the image data, and the receiving-side image processing apparatus records the image line by line based on the image data. Recording means for outputting a recording line synchronizing signal, decompressing means for decompressing compressed image data received from the transmitting side image processing device for each line according to the recording line synchronizing signal, and recording line outputted from the recording means. Gate means for thinning out the synchronizing signal in accordance with the enlargement rate or resolution improvement rate and inputting it to the restoring means, and each time the recording means records a plurality of lines of images, one line of the restoring means is recorded. The compressed image data is decompressed, and the decompressed image data for one line is output to the recording means a plurality of times. By, there is provided an image transmission apparatus for executing enlargement processing or resolution enhancement with restoration process for the compressed image data.

Hereinafter, the present invention will be described with reference to examples.

FIG. 1 is a system block diagram to which the present invention is applicable.

The reader 1 reads an original using, for example, a CCD image sensor, performs analog-to-digital conversion, then performs shading correction, binarization processing, etc., and outputs it as a digital image signal to an external circuit.

The printer 2 is, for example, a laser beam printer (LB
P) is a device for forming a digital image signal on a print sheet. By directly connecting the reader 1 and the printer 2, it is possible to operate as a copying apparatus. In the present embodiment, the reader 1 and the printer 2 are connected by using a connection interface between the reader 1 and the printer 2.
It is configured to add the functionality of a Faximilli device without major changes to.

The RP adapter 3 is a conversion circuit for converting a digital image signal between the reader 1 and the printer 2 so that it can be handled by the computer bus 11. The computer bus 1 is, for example, an Intel multi-bus,
It has a maximum data transfer rate of several M words / sec, and has multiple data processing devices such as main CPU4, memory 5, disk controller 6, and line control circuit 9 that mainly control the bus.
It is connected to each other in the form of a board together with the RP adapter 3 to transfer information.

The document image data read by the reader 1 is converted by the RP adapter 3, temporarily stored in the memory 5, and further stored in the magnetic disk 7 or the floppy disk 8 via the disk controller 6 if necessary. The stored data is sent to the communication line via the line control circuit 9 (modem etc.) and the coupler 10.

On the contrary, the original image data sent from the communication line is stored in the memory 5 via the coupler 10 and the line control 9, and is similarly stored in the magnetic disk 7 and the floppy disk 8 by the disk controller 6 if necessary. The stored data is sent to the printer 2 via the RP adapter 3 and an image is formed on the print paper.

The main CPU 4 centrally manages a series of these facsimile operations.

FIG. 2 is a block diagram of the RP adapter. Reference numeral 1-1 denotes an original reading device that sends a serial digital image signal together with a synchronization signal for each original reading line.
Main scanning is performed by a CCD having a line length, and sub-scanning is performed by moving the CCD or the imaging system at a predetermined speed. It is read at a resolution of 400 bpi (bit / inch) in both the main scanning direction and the sub-scanning direction.

1-2 is the bit format image data vi from the document reading section.
This is a circuit for compressing deo by a method such as encoding. In this embodiment, a circuit of a well-known run length encoding system is used. 1-3 are bit serial image data vi
It is a serial-parallel converter (hereinafter referred to as an S → P converter) that converts deo into a parallel format. The double buffer memories 1-4, 1-5 and 1-6, 1-7 work in pairs, and have the capacity to write and read the image data for one line obtained in 1-2, 1-3. 1-4 (1-
While writing the image data to 6), 1-5 (1-
When the image data is read from 7), the operation is performed. 1
-8 and 1-9 are write address counters for giving a data write address to each double buffer memory. 1-10 is an image compression unit of 1-2 and S → P of 1-3.
This is a comparator for judging the size of the conversion data obtained from the conversion unit, and the output of the comparator controls the selector 1-26 to convert the conversion image data from the conversion logic with the smaller data amount into a multi-bus (computer bus) system. 1-11. The converted image data is applied to the memory shown in FIG. 1 through the multibus at a predetermined multibus system speed.

The structure of the decoding unit for compressed image data is as follows 1-3
0 and 1-31 are double buffers for synchronizing the data transfer from the multi-bus system 1-11 which is the source of compressed data and the reading of the compressed data of the decompression logic.
A data request is transmitted to the multi-bus system 1-11 in synchronization with the read address counter 41. Reference numeral 1-32 is a selector logic which determines the attribute of the compressed data read from the double buffer and selects the restoration logic to be used. 1
-33 is a decompression unit corresponding to the 1-2 compression unit, and 1-34
Is a parallel → serial converter (hereinafter referred to as P / S converter) corresponding to 1-3 S → P converters.

The RAM for reading the image signals obtained in the bit serial format by the above-mentioned restoring means in an overlapping manner and converting the pixel density in the sub-scanning direction is 1-35. The output of this RAM is 1
Reproduce with a −45 printer.

In the present embodiment, the image compression is performed in synchronization with the sync signal HSYNC corresponding to the completion of reading one line from the document reading section 1-1, and the image restoration is performed by the sync signal D-HSYNC (from the printer 1-45). In case of LB printer, it corresponds to the end of 1 line beam scan). By the way, gate these tuning signals to the compression or decompression circuit,
By applying it to the compression or decompression circuit, the pixel density can be converted and the image can be enlarged or reduced. The synchronizing signal gate means for this purpose is HSYNC, Video Enable gate logic 1-12 and D-HSYNC gate logic 1-36.

The operation of the circuit in this embodiment will be described below.

(Compression Circuit) The left side of the chain double-dashed line in FIG. 1 is a compression circuit, which processes the digital image signal from the document reading section 1-1 and transfers it to the multibus system 1-11. The output signal from the document reading section and its signal format are shown in FIG.

The signal from the document reading unit is HSYNC which is a section signal for each line, Video Clock which is an image information transfer clock, Video and HSYNC which is a serial image signal, and the image signal which is actually an image signal in one line section until the next HSYNC. Vi to indicate that it is valid
It comes from deo Enable.

HSYNC is output for one clock in synchronization with Video Clock. The maximum main scanning length of the reading unit used in this embodiment is
Since 8 1/2 inch is read at a resolution of 400 bps, 3400 bit image data is sent as one line. Therefore, High level section of Video Enable (image valid section)
Is the Video Clock 3400 clock minutes.

These signals are S / of the image data compression units 1-2 and 1-3.
Parallel data is independently given to the P converters, and the coded data of 1-2 is in the double buffer of 1-4 and 1-5, and the parallel data from 1-3 is 1-
Written in 6, 1-7 double buffer. Controlling the write operation to the double buffer is 1-8, 1-
9 is a write address counter. Each counter is Video
Initialized by Enable. 1-8 counter is 1-
The counting operation is performed by the clock synchronized with the image coding from the compression unit 2 and the counter 1-9 is S → 1-3 →
The clock counts in synchronization with the conversion operation of the P converter. In addition, the switching operation of the double buffer is 1-18, 1-19, 1-2 because the toggle flip-flop of 1-13 changes every line by the input of HSYNC signal.
0, 1-21, 1-22, 1-23 are respectively performed by the operation of the address selector and the data selector. The Read address data is input from the multibus via the address buffers 1-29, and each buffer is read and data is transmitted in synchronization with the multibus.

The operation of the above circuit of the compression unit is shown in the timing chart of FIG. Since the S → P converter 1-3 converts the image signal into 14-bit parallel, 14 clocks of Video Clock generate a clock input of 1 clock to the write address counter. In this case, the address counter output counts from 0 to 242 by the video clock of 3400 clocks per line. This corresponds to a memory capacity of 256 words. When the resolution is reduced to 1/2 and the serial-parallel conversion is performed at 200 bpi, the output state of the address counter changes by 1 with the 28 clock Video Clock, and the output state of 3400 clock is changed.
Up to 122 is counted by Video Clock. Thus S →
The address counter 1-9 for the P conversion unit performs a steady count operation in one main scanning period, but the operation of the write address counter 1-8 for compressed run length data is different. Since the image data compression unit 1-2 encodes and outputs how many clock states each video signal is continuous, the clock input to the write address counter 1-8 indicates that the video signal status is It happens every time it changes. Therefore, a clock from 1 clock to 3400 clocks is input to the address counter by an image signal of 3400 bits on one line. That is, the output of the address counter 1-9 is constant for each line, whereas the counter output 1-8 takes values from 1 to 3400. Here, which conversion data is smaller in each of the image conversion units 1-2 and 1-3 is determined by comparing the values of the address counters. The converted data volume is Video
Since it is determined at the end of Enable, the value at that time is 1-14,1
The flip-flop of -15 is latched, the value of each flip-flop is compared by the comparator of 1-10, and the output is latched to the flip-flop of 1-25 by the line synchronizing signal HSYNC. Depending on the output state of this flip-flop, 1-
The selectors 1-26 select the data to be read by the 11 multibus system. If the number of clocks input to the 1-8 run length data address counter exceeds the memory capacity (256 words), 1-24 O
The selector 1-26 is set to select the data from the serial-parallel conversion from the other input of the R gate.

The data written in the buffer RAMs 1-4 to 1-7 will be described with reference to FIG. The data for one line from the image converters 1-2 and 1-3 is 16 from the first address of RAM.
The data is sequentially written in the bit-parallel manner while increasing the address at addresses 2 and 3. The format of the data is as follows.

In the case of the run length code data of the compression unit 1-2, it becomes as shown in (a), and the data from the S → P unit 1-3 is RAM1-6, 1-7.
Written in the form (b). In this case, 0 at 14th and 15th bit
0 indicates that the 0th to 13th bits are image data.

Then, when the writing for one line is completed, 1-1
The identification code of the start of one line is added to the value of the address counter latched at 4, 1-15, and it is written in the address 0 of RAM. The format is as shown in (c). Ie RA
A 1 is written in the 13th bit of the data written in the 0th address of M1-4, 1-5, and a 0 is written in the 13th bit of the RAM1-6, 1-7. The 15th bit and the 14th bit are identification codes, which are used to distinguish whether the data is the delimiter for each line or the actual image data.

In this way, 1-2, 1-
Each of the two image converters of No. 3 independently writes the conversion data to the RAM, but only one of them is actually read out. As described above, it is the address counter 1-8, It is determined by the value of 1-9.

The multibus system 1-11 receives the interrupt signal by the HSYNC signal from 1-27 and starts reading the conversion data (one line before) for one line written in the RAM. This read speed must be fast enough to read the valid data written in RAM during one section of HSYNC. First, the multibus system 1-11 sends a data read request signal from 1-27 to the main CPU 4 or the disk controller 6 to judge it there, output read address data, and start reading data from address 0 of RAM. . Since the type of the data for one line contained in the addresses after the address 1 is written in the address 0, the memory device such as another disk connected to the multi-bus takes in the data corresponding to the data length. This data is sent to 5-8 and the communication control unit 9. In this case, it is not necessary to read unnecessary data in the RAM by controlling the output of the read address data by determining the data length by the CPU or the controller 6, and there is an advantage that the occupation time of the multibus is minimized.

Therefore, an empty time can be created for each line when the read data is compressed and sent, and the multi-bus can be released during that time. That is, the bus can be effectively used for communicating the data of the disk 6 by line control.

Next, a method for converting the pixel density of the compressed data will be described. As a result, the image data can be reduced, and the document reading device can be adapted to a recording device having a small recording pixel density.

That is, a high resolution of 400 bpi may not be required when the read image is a character image. In that case, it is more economical to transfer at a lower resolution, because the transfer time is shortened, the exclusive time of the multi-bus is reduced, and the efficiency of use of the intermediate buffer memory such as a disk memory is increased. If the image recording device does not have the image reduction function, the transmitting side must compress the image when the reduction is required. By providing the recording device with the enlargement function, it is possible to prevent an increase in the amount of information on the transmission side.

By the way, the method of reducing the resolution in the main scanning direction is to change the frequency of the image sample clock that has been used conventionally, and it corresponds to the video of serial data before conversion in the conversion units 1-2 and 1-3. Controls the clock frequency. The clock rate at that time is set as EM ₁ .

1-12 for reduction in the sub-scanning direction (decrease in resolution)
The synchronizing signal gating means is used. The image data compression circuits described so far are all performed by the HSYNC.Vides Enable synchronization signal. Therefore, if the synchronizing signal for the data of a predetermined line corresponding to the rate is gated so as not to be output, the data of the line will not be processed, so that the line is spread. Also,
Since no data read request Req corresponding to the above line is issued to the multibus 1-11, there is no fear that the data of the gated line will be read and transmitted to the bus.

Thus, in order to obtain the data of the desired resolution,
The 12 synchronization signal gate circuits are configured as follows.
That is, it is composed of a clock-spreading means such as 7497TTC, and HSYNC, which is a 1-line synchronization signal, is input to the clock to generate a gate signal, whereby HSYNC.Video is generated.
The enable sync signal is transmitted. The blink rate that determines the resolution (reduction rate) is set as EM ₂ by setting means such as a switch (not shown). By setting EM ₁ and EM ₂ independently, the vertical and horizontal pixel densities and reduction ratios can be determined.

Next, a method for restoring compressed data will be described.
The restoration unit restores the data provided from the multibus system 1-11 of 1-11. Although this data is data generated by the above-described compression method, it does not have to be from the compression unit connected to the same multi-bus as the decompression unit.

First, the multi-bus system 1-11 writes a predetermined amount of data in any one of the RAMs 1-30 and 1-31. In this embodiment, it is set to 256 words. 1-30, 1-31 RAM,
It is configured as a double buffer, and when writing data to one, it operates to read the data from the other. The decoder select unit 1-32 sends a clock to the read address counter 1-41 in order to find a section signal for each line from the data in the RAM. When the section signal of one line is found, the format of the next data (Fig. 5) is written therein, so a signal is issued to the selector 1-44 to select the restoration section corresponding to it. A printer 1 that can also be configured to switch the restoration operation 1-
The restoration operation is started from 45 in synchronization with a synchronization signal G-HSYNC (described later). Here, the compressed data decompression circuit corresponds to the compression circuits 1-2 and 1-3, and the compressed data decompression circuit 1-33, and the parallel data 14-34 that converts parallel data to serial data. Section (hereinafter referred to as the P → S conversion section), and these two circuits use the synchronization signal G-HS.
It is always operating by YNC. Each restoration circuit synchronizes with the restoration operation and outputs a signal (Data Res.
However, the decoder select unit 1-32 sends only the request signal from the restoration circuit designated by the line delimiter signal as the clock of the read address counter 1-41. In this way, the line serial video signal is sent to the printer 1-45, which is shown in FIG. That is, the synchronizing signal D- from the printer 1-45.
Clock generation means 1-4 which is internally provided according to HSYNC
Serial clock signal, D-Video and D-Video Enable for the 2nd clock by D-Video Clock which is the image clock.
Is sent.

The decoder select unit 1-32 sends the Data request signal from the restoration unit to the read address counter 1-41 to fetch the next data, but if it is a line delimiter signal, the data is not passed to the restoration unit. Instead, it waits for the next line synchronization signal D-HSYNC, thereby setting the data selector 1-41 in a predetermined state and sending the next data to the restoration unit.

Note that the counter 1-41 outputs the count-up signal 1- when the reading from one of the double buffers is completed (when it is empty).
It outputs to the toggle flip-flop of 37, switches the write and read operations of the two RAMs, and makes an interrupt request logic of 1-27 to request the next 256 word data to the multibus system 1-11. Also outputs a count-up signal for 256 addresses.

Since the maximum amount of data per line in the compression unit is about 256 words, a 256 word double buffer 1-30, 1-31 causes the interrupt signal cycle input to the multi-bus system 1-11 to be 1-45. To 1 line sync signal D-
Since it is certainly longer than the HSYNC interval, the speed of the multi-bus system should be such that at least 256 words of data can be transferred during one line section. Therefore, as the bus speed increases, the idle time for each line increases, and the bus can be used for other information processing and transmission.

The pixel density conversion means in the restoration unit is as follows.

The conversion of the pixel density in the main scanning direction is often used conventionally.
The technique of sampling the image data by spreading the basic clock from 1-42 is used. In this case, sample processing is performed on the output by 1-33 and 1-34 and the real data. The density conversion data is set as DM ₁ by a preset switch or the like. The following means is used to convert the pixel density in the sub-scanning direction. When outputting an image at the same size to a printer having a resolution higher than that of the transferred data, or when enlarging and outputting to a printer having the same resolution, the same restored line data is output multiple times. Therefore, the line memory 1-35 is used after the restored data selector 1-44. This RAM is an address counter 1 that operates in synchronization with a synchronization signal D-HSYNC (beam detection signal BD) from the printer.
It operates by the output of −43. Then, the output of the selector 1-44 can be stored and then read. When outputting data on the same line multiple times, 1-
In order that the data input signal of the 44 selector becomes the output signal of RAM 1-35, the selector 1
Continue to output select signal DS to -44. This is because when the same data is output, the data from the restoring unit 1-33 is discarded, so that the synchronizing signal gate unit 1-36 stops the synchronizing signal G-HSYNC that goes to the restoring unit so as not to perform the restoring operation. To gate. The select signal DS to the selector 1-44 is also output in synchronization with this gate operation. This gate period is proportional to the expanded conversion data DM ₂ , and DM ₂ is preset. DM ₂ can be preset independently of DM _1, and the magnification of vertical and horizontal can be changed. The structure of the synchronization signal gate unit 1-36 for obtaining a predetermined resolution (enlargement ratio) is the same as that of 1-12 described above. Since G-HSYNC is not input to the gate period select logic 1-32, the clock to the read address counter 1-41 is stopped. Therefore, it does not read the buffer RAM and waits for data to be stored. Therefore, during this period, Multibus 1-11
Are released and used for other devices in the first round. When the gate period expires, the subsequent G-HSYNC causes the select logic 1-32 to start reading and decoding the data of the next line from the RAM. The decoder outputs DATE REQ at the end of the signal for each word and outputs the clock to the read address counter to read the RAM. 1 data from RAM
Select logic 1-
When it is judged at 32, the sending of the next line data to the decoder 1-33 or the converter 1-34 is blocked, and the process waits until G-HSYNC occurs. Read and receive RAM1-30 by G-HSYNC. When the RAM1-30 is read until it becomes empty, it switches to the RAM1-31 read and starts storing from the bus to the RAM1-30.
It depends on the write address data from the bus.

In addition, when outputting to a printer having a resolution lower than the resolution of the data transferred from the multi-bus system 1-11 at the same size, or when reducing and outputting even a printer having the same resolution, line spread may occur. Needed. This is done in the decoder select unit 1-32. That is, the line delimiter signal is skipped so that the resolution set as the data DM ₂ in the decoder select section is achieved. For example, when outputting to a printer with half the resolution, when decoding of one line is completed,
(This can be understood from the fact that the next line section signal is input to the decode select logic 1-32.) Skip the next line and clock the read address counter 1-41 until the next line delimiter signal comes. When generated, the data of one line interval can be supplied to the restoration unit 1-33.

In this example, the conversion units 1-2 and 1-3 are switched according to the image information, but the first, second, and compression conversions having different compression methods are switched according to the amount of image information (for example, MH conversion). And MR conversion).

Further, in this example, the multi-bus is released after the transmission of the one-line processing at the time of compression, but it is also possible to release it every plural lines, thereby reducing the complicated exchange of control signals via the bus by the main CPU or the like. In this example, an interrupt request signal is issued to the released multibus to interrupt the low-priority bus utilization processing between other devices and execute the data transfer. , Can be stored in a file device or the like. Note that a part of this example can be applied to the case where all the read images are stored in the memory once.

As described above, according to the present invention, an image transmission apparatus that connects a plurality of image processing apparatuses via a transmission line and transmits / receives compressed image data between the plurality of image processing apparatuses via the transmission path. In the image processing device on the side, a read line synchronization signal, which is a reference for compression processing for image data, is thinned out in accordance with the reduction rate or resolution reduction rate without providing a dedicated configuration for reduction processing or resolution reduction processing for image data. With such a configuration, reduction processing or resolution reduction processing can be executed together with the compression processing on the image data, whereby the transmission amount of the compressed image data on the transmission path can be reduced. It is a standard for decompression processing for compressed image data without providing a dedicated configuration for resolution improvement processing. The simple configuration of thinning in accordance with the enlargement ratio or resolution enhancement rate recording line synchronization signal,
Enlargement processing or resolution improvement processing can be executed together with decompression processing for compressed image data, which can prevent an increase in the transmission amount of image data on the transmission path.

[Brief description of drawings]

FIG. 1 is a system block diagram in the present invention, FIG. 2 is an image processing circuit diagram in the present invention, and FIGS.
FIG. 5 is a processing time chart in the figure, and FIG. 5 is an explanatory view of transmission data. Reference numeral 1-11 is a multibus, 1 is a reader, and 2 is a printer.

Claims (1)

[Claims] 1. An image transmitting apparatus, wherein a plurality of image processing apparatuses are connected by a transmission path, and compressed image data is exchanged between the plurality of image processing apparatuses via the transmission path. A reading means for reading the image line by line and outputting the read image data and the read line synchronization signal; and a compression means for compressing the image data output from the reading means for each line according to the read line synchronization signal. Gate means for thinning out the read line synchronizing signal output from the reading means in accordance with the reduction rate or the resolution reduction rate and inputting to the compression means, and the image data for a plurality of lines is output from the reading means. The image data for one line is compressed by the compression means for each time, and the image data output from the reading means is thinned out in line units and compressed. By performing the processing, the image data is subjected to the compression process and the reduction process or the resolution reduction process, and the receiving side image processing device records the image line by line based on the image data and outputs the recording line synchronization signal. A decompression means for decompressing the compressed image data received from the transmitting image processing device line by line in accordance with the recording line synchronization signal, and a recording line synchronization signal output from the recording means. And a gate means for thinning out and inputting to the decompression means according to the above. Every time an image for a plurality of lines is recorded by the recording means, the decompression means performs a decompression process on the compressed image data for one line. By outputting the restored image data for one line to the recording means a plurality of times, the compressed image data An image transmission apparatus, which performs enlargement processing or resolution improvement processing together with restoration processing.