JPH0774973A - Data conversion device - Google Patents

Abstract

PURPOSE:To make it possible to receive packed data from an external memory as they are and to restore the received data in a color conversion device using a lookup table. CONSTITUTION:A counter 104 is driven at a 9 count period and packed 8-bit data inputted to a terminal 102 are loaded to a shift register 103 when the value of the counter 104 is '0'. On the other hand, 1-bit data successively outputted from the register 103 are added to the most significant bits of eight packed 8-bit data inputted to the terminal 102 thereafter and 9-bit data are restored and stored in an LUT 107 in accordance with address data from a terminal 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion device for performing color conversion and the like using a look-up table (hereinafter also referred to as LUT).

[0002]

2. Description of the Related Art Non-linear conversion (γ conversion, log conversion, etc.) of a digitized image signal is generally performed by an LUT. This is because if an attempt is made to perform a non-linear conversion, the operation becomes relatively complicated and the scale of hardware for the operation becomes large. On the other hand, when an LUT is used to perform arbitrary nonlinear conversion on an 8-bit image signal, for example, this conversion process can be realized with a memory having a relatively small capacity of 256 bytes. Since such conversion is for converting one image signal into another image signal having another property, the LUT used therein is called a one-dimensional LUT.

On the other hand, with the recent spread of the desktop publishing (hereinafter, also referred to as DTP) environment, the chances of handling color images are increasing. The color image input device in the DTP is a scanner or a video camera, while the output device is an inkjet, dye thermal sublimation type, or electrophotographic color printer.

Each of these color input / output devices has its own color space. For example, when color image data obtained by a scanner is directly input to a color printer to output a print image, the print image is printed. It is unlikely that the color of the image will match the color of the original image read by the scanner. In order to match the two colors, it is necessary to perform processing such as converting the color space of the so-called input device (scanner, video camera, etc.) into the color space of the output device (various color printers described above). Is called color conversion processing).

In this color conversion process, for example, the image signals of three colors of the input device are simultaneously referred to, and the three colors on the output device side are referred to.
The image signals are converted into color or four-color image signals. However, obtaining the three-color or four-color image signals on the output device side at the same time requires a relatively large scale of hardware. Therefore, normally, the image signals are output one by one in dot-sequential or frame-sequential manner. Therefore, the color conversion process converts the image signals of three colors into one.
The process of converting into the color image signal is performed for the number of colors of the output device.

Such an image signal of, for example, three colors is
If an image signal of 8 bits per color is to be converted by using only the LUT, the input 2
It becomes a LUT of 4 bits and 8 bits of output, and a memory capacity of 16 Mbytes is required, and the above memory is required for the number of colors of the output device. Therefore, the actual memory capacity becomes as large as 48 to 64 Mbytes. Since such an LUT is not practical in terms of cost, it is common to use interpolation in the color conversion processing by the LUT. As a result, color conversion suitable for practical use can be performed with a relatively small memory capacity.

The structure of color conversion using the LUT will be described with reference to FIG.

8-bit image signals of red (R), blue (B) and green (G) components are input from terminals 201, 202 and 203, respectively. These image signals R, B, G
Each 8-bit upper 4-bit signal is input to the three-dimensional LUT 210, and an interpolation space that is a subspace of the input color space is selected. Further, the lower 4-bit signal is input to the interpolation calculation unit 220 and defines the local coordinates of the interpolation target point in the interpolation space.

That is, when the upper 4 bits of the R, B, G 8-bit signal are rh, bh, gh and the lower 4 bits are rl, bl, gl respectively, the signals rh, b
The data 211 to 218 read out from the three-dimensional LUT 210 by h and gh indicate eight grid points that define the interpolation space used in the interpolation operation unit 220 in the next stage. Specifically, the content of the LUT corresponding to (rh, bh, gh) is provided on the signal line 211, and (rh + 1, bh,
The contents of the LUT corresponding to gh) and (r
content of the LUT corresponding to (h, bh + 1, gh) and L corresponding to (rh + 1, bh + 1, gh) on the signal line 224.
The contents of the UT, (rh, bh, gh + on the signal line 225
The contents of the LUT corresponding to (1), and (rh
The contents of the LUT corresponding to (+1, bh, gh + 1), the contents of the LUT corresponding to (rh, bh + 1, gh + 1) on the signal line 227, and the contents of (rh + 1, bh +) on the signal line 228.
The contents of the LUT corresponding to (1, gh + 1) are output respectively.

The eight data thus read are, for example, r
When h = 5, bh = 10, and gh = 13, as shown in FIG. 2, the coordinates of each vertex of the three-dimensional cube, that is, eight grid points that define the interpolation space are represented. At this time, the lower 4 bits of the input signal define the interpolation target point in the three-dimensional cube shown in FIG. 2 as described above. It should be noted that this interpolation target point is the signals rl, b of the lower 4 bits.
When one of l and gl is 0, it exists in the plane that constitutes the cube, and when two are 0, it is located on the side of the cube, and when all three are 0 ( 5, 10, 1
It is located at the top of 3). The target output signal is output from the terminal 221 by performing the interpolation calculation corresponding to the position of the interpolation target point defined by the lower 4 bits of the input signal.

As described above, when the signal output from the LUT 210 is 8 bits,

[0012]

[Outer 1]

That is, it becomes 4 kbytes. This memory capacity is for outputting one color, and in order to output three colors or four colors, a memory capacity of 112k to 16k bytes is required.

[0014]

By the way, the 8-bit data obtained by the color conversion having the configuration shown in FIG. 1 is often overlapped with an interpolation error or a calculation error, which often causes the signal to be relatively deteriorated. . As a method for preventing this deterioration, increasing the calculation accuracy of the interpolation calculation unit 220 and increasing the number of bits of the eight data input to the interpolation calculation unit 220 (considering that the grid point spacing of the interpolation space is fine is considered. Of these, for example, when the number of bits of data input to the interpolation calculation unit, that is, the number of output data bits of the three-dimensional LUT is increased to 9 bits or 10 bits instead of 8 bits, 8 bits are used. How to handle the data becomes a problem due to the data transfer that takes the structure and the reason of the memory structure.

It is an object of the present invention to provide a data conversion device which can properly handle such 9-bit or 10-bit data.

[0016]

To this end, in the present embodiment, in a data conversion device for converting data using a lookup table, the table data written in the lookup table has a size different from the data size. Holding means for temporarily holding one of the plurality of packing data input to the data conversion device from a memory stored as a plurality of packing data; and all or part of the packing data held in the holding means, The data conversion device further comprises a connecting unit that connects the plurality of packing data to another data, and a storage unit that stores the data connected by the connecting unit as the table data in the lookup table. It is characterized by

[0017]

With the above configuration, when storing the table data of the lookup table in the data conversion device,
When one of a plurality of packing data having a smaller size than the table data is input, the data is held by a holding unit having a register or the like, and a part or all of the data and a part or other of the other packing data to be input. By connecting with all, the table data to be stored in the lookup table is restored. As a result, the data conversion device can receive and restore the packed data as it is and use it.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, two types of methods can be considered for handling data that is not an integral multiple of 8 bits, such as 9 bits and 10 bits described above for explaining the proportionality of the present embodiment.

The first method is a method of adding dummy data ("0") to the upper bits to form 16 bits. This method is easy to handle because each piece of data remains independent, but the capacity of the memory required to store the data increases, and this increase in the memory capacity causes an increase in cost.

The second method is a method of packing data. For example, in the case of 9-bit data, eight 9
Only the most significant bit (or the least significant bit) is extracted from the bit data, eight of them are collected, and these are arranged into 8-bit data, and the remaining 8 bits remain as they are.
Use bit data.

According to the second method, eight pieces of 9-bit data become nine pieces of 8-bit data, and the memory capacity is not increased to store the problematic data in the first method. , The minimum memory capacity required. However,
Since the individual data are not independent, it becomes impossible to directly load the data from the ROM or the like that stores the LUT data used as a table into the LUT. In this case, the data read from the ROM is temporarily stored in the CPU.
It is necessary to load the data into the original independent data by the process inside the CPU and then load the data into the LUT.

That is, in order to output data in which the number of bits is increased from 8 bits such as 9 bits from the LUT, L is used.
Each data in the table, which is the content of the UT, must be, for example, 9 bits, and when such data is loaded into the LUT data corresponding to the standard color space as described above, the above-mentioned CPU is used. It is necessary to restore the packing data.

As described above, in the device for converting data using the LUT, the number of bits of the table data to be loaded into the LUT is a value that is not an integral multiple of 8 bits, for example, 9 bits.
In the case of bits, such an LU that is not an integral multiple of 8 bits
When the T data is stored in another memory (ROM or the like) in advance, the stored data is packed in order to save the capacity of this memory.

In this case, since the individual data stored in the other memory are not independent from each other, the data read from the other memory cannot be directly transferred to and stored in the LUT, and the CPU once Data into C
The original independent data (data before packing) must be restored in the PU, and then transferred to the LUT for storage.

However, in the above configuration, compared with the configuration in which the data stored in another memory without packing is transferred to the LUT, it takes several times as long as the data transfer and the like, and it is temporarily necessary for the CPU. However, it will increase the load.

The embodiment described below discloses a data conversion device capable of accepting packed data in a data conversion device such as a color conversion device using an LUT as it is and restoring the packed data for use. .

(First Embodiment) FIG. 3 is a block diagram showing the arrangement of a color conversion apparatus according to the first embodiment of the present invention.

In the figure, a one-dimensional structure of a three-dimensional LUT is shown. That is, as shown in FIG. 1, in addition to the 8-bit data input via the terminal 101, two other 8-bit data are input, but these are not shown. Similarly, in addition to the output data at the terminal 109, the output of seven other pieces of 9-bit data is omitted,
Further, the illustration of the interpolation calculation unit is also omitted. The same applies to each of the examples described below.

The data received by the color conversion apparatus shown in FIG. 3 and loaded as LUT data in the LUT is stored in the ROM (not shown) and packed as shown in FIG.

That is, FIG. 4 shows the packing state of the top eight 9-bit data of the LUT data.
These eight data _{a 8 ~a 0, b 8 ~b} 0, c 8 ~
_{c 0, d 8 ~d 0,} e 8 ~e 0, f 8 ~f 0, g 8 ~g 0
, H _{8 to} h ₀ , only the most significant bits of each data are collected and stored in the address 0 of the ROM,
The lower 8 bits of each are sequentially stored from the first address of the ROM.

The operation shown in FIG. 3 will be described below.

First, the counter 104 is cleared to 0 by a reset signal (not shown). The counter 104 operates in a 9-count cycle and outputs a load signal to the register 103 when the value is 0. At this time, the 8-bit data a read from the address 0 of the ROM shown in FIG.
_{8 b 8 c 8 d 8 e} 8 f 8 g 8 h 8 is input, in response to the clock input to the register 103, the 8-bit data is loaded into the register 103.

By this loading, the 1-bit signal 105 output from the register 103 becomes the most significant bit a ₈ . At this time, an 8-bit address signal (actually, three pieces of 4-bit data as shown in FIG. 1) designating the start address: address 0 of the LUT 107 is input to the terminal 101, and the terminal 102 is set to 1 of the ROM. Address contents (a
_{7 to} a ₀ : 8 bits) are input. As a result, the output (a ₈ ) of the shift register 103 is added to the higher order of this 8-bit input data, and the 9-bit signal 106 (a ₈ ) is added.
~ A ₀ ). This 9-bit signal is written in the LUT 107 by a write control signal (not shown).

Then, a clock is input to the shift register 103 to shift the data by 1 bit, and b ₈ is output from the shift register in the next cycle. At this time,
The terminal 101 8-bit signal that specifies the first address of the LUT are input, the contents of the second address of the ROM to the terminal 102 (b ₇ ~b _0: 8 bits) are input. The contents of the 9-bit signal 106 at this time are b _{8 to} b ₀ , and are written in the LUT 107 by the write control signal as described above.
The same processing is performed thereafter, and the values shown in FIG. 5 are stored at addresses 0 to 7 of the LUT, and the storage of one set of eight data is completed.

When the storage of these eight pieces of data is completed, the value of the counter 104 returns to 0, and the data of only the most significant bit of the next eight pieces of 9-bit data stored in the address 9 of the ROM is transferred to the terminal. Shift register 10 via 102
3 is loaded, the storage of the next set of 8 data is started, the same processing is repeated in sequence, and all data is LUT1.
It is stored in 07.

When the storage of the LUT data in the LUT 107 is completed, the original operation of the color conversion device becomes possible, the mode is shifted to, and the 8 input from the terminal 101 is entered.
The bit data is converted into a predetermined 9-bit data group and transferred to the interpolation calculation unit.

In this embodiment, the most significant bit and the 8 bits below it are separated, but a configuration in which the least significant bit and the higher 8 bits are separated can be easily realized. In this case, the 1-bit signal output from the shift register 103 is input from the terminal 102.
It is added below the bit data.

(Second Embodiment) FIG. 6 is a block diagram showing the arrangement of a color conversion apparatus according to the second embodiment of the present invention.

The structural difference between this embodiment and the first embodiment is as follows.

In this example, there is no counter 104, but a block 201 for detecting that the lower 3 bits of the 8-bit address signal input from the terminal 101 is “000” is provided. Block 201 is "0
When "00" is detected, a load signal for the shift register 103 is generated.

The signal to be loaded into the shift register 103 is not the 8-bit data input from the terminal 102 but the 8-bit data previously stored in the LUT 107, which is read and loaded from the LUT 107. This loading operation is "00" in the block 201 described above.
Perform when 0 "is detected.

Corresponding to the above configuration of this example, the order of data stored in the ROM is also shown in FIG. The first
In the embodiment, the entire operation of the embodiment could be explained by using a set of eight data, but the operation of this embodiment is explained in 4 cases.
A set (32) of data is required. That is, in FIG.
In FIG. 8, one set of 8 (9 bits each) data is distinguished for each set, and the first set is not marked with “′”.
The 8th data of the second set is a ′, b ′, ..., H ′, and the 8th data of the 3rd set is a ″, b ″, ..., H ″.
, The 4th set of 8 data is a ″ ″,
, b ″ ″, ..., h ″ ″ are distinguished.

In the first embodiment, one set of eight data is stored in the ROM as one lump at nine consecutive addresses, but in the present embodiment, data of only the most significant bit is stored. Data of only the lower 8 bits are completely separated at the address and stored (see FIG. 7).

The operation of this embodiment will be described below.

In this embodiment, the data consisting of the most significant bit is stored in the LUT 107 in advance. That is, FIG.
As shown in, the contents of the N address of the ROM are transferred to the 0 (= 8 × 0) address of the LUT 107, and the contents of the N + 1 address of the ROM are transferred to the L level.
The contents of the address N + i of the ROM are sequentially stored in the address 8 (= 8 × 1) of the UT 107 and the address 8 × i of the LUT 107. The contents of the LUT 107 after this storage are shown in FIG.

When the storage of the data of only the most significant bit is completed, next, the lower 8 bits stored from the address 0 of the ROM are stored.
Stores bit data.

First, an 8-bit address signal designating address 0 of the LUT 107 is input to the terminal 101. At this time, the lower 3 bits of this address signal are all 0,
“000” detection block 201 detects that LU
8-bit data a ₈ b already stored from address 0 of T
_{8 c 8 d 8 e 8 f} 8 g 8 h 8 is read and loaded into the shift register 103. And ROM at the terminal 102
The 8-bit data of a ₁ ... A ₀ read from address 0 is input, a ₈ output from the shift register 103 is added to the higher order, and the data is stored again at address 0 of the LUT. At this time,
The data of the most significant bit group stored in advance at this address disappears, but the shift register 103
Holds its contents, so there is no problem at all.

Thereafter, as in the first embodiment, a clock is input to the shift register 103, data is shifted by 1 bit, an address signal designating the first address is input from the terminal 101, and the first address of the ROM is input to the terminal 102. The contents of b _{7 to} b ₀ are input, b ₈ is added to this data, and then stored in the LUT 107. This processing is continuously continued until the first eight sets of data are stored in the LUT 107.

Next, the second set of eight data is converted to the LUT10.
The process proceeds to the process of storing in 7.

An 8-bit address signal designating address 8 is input to the terminal 101. At this time, the lower three bits are all 0 the address signals again, "000" is detected it in detection block 201, the 8 address of LUT 107, already the stored 8-bit data a ₈ 'b _{8'
c 8 'd 8' e 8} 'f 8' g 8 'h 8' is read, it is loaded into the shift register 103. Then, a ₇ ′ ... a ₀ ′ read from the ROM address 8 at the terminal 102.
8-bit data inputted to the a ₈ 'which is outputted from the shift register 103 is added on top of, LUT 107
Re-store in address 8. In this way, the 8th data of the second set is also stored in the LUT 107, and then the third set,
The fourth group, ... Continues, and the storage of all data is completed.

The configuration in which the most significant bit data and the least significant 8 bit data are separated and stored in the ROM and the most significant bit data is stored in the LUT 107 in advance as in the present embodiment has the following features. .

The most significant bit data to be stored in advance is
Although the addresses do not become continuous at the time of storage in the LUT, the ROM and LUT addresses of the lower 8-bit data to be stored after that become continuous, so DMA (direct memory access) transfer is possible, and color conversion from ROM to this example is possible. Data can be transferred to the device at high speed.

In the following third and fourth embodiments, the lower 8
Not only in the bit data but also in the preceding storage of the most significant bit data, the addresses are made apparent or actually continuous.

(Third Embodiment) FIG. 9 is a block diagram showing the arrangement of a color conversion apparatus according to the third embodiment of the present invention.

As described above, in this embodiment, the addresses of the most significant bit data stored in the LUT prior to the second embodiment are apparently continuous. In order to realize this, a shifter 301 and a selector 302 for shifting an 8-bit address signal to the upper 3 bits are provided. When the most significant bit data is stored in the LUT 107 in advance, the selector 302 selects the 1-a side, so that 0, 1, 2,
When 3, ... (Decimal number display) is input, this address value is converted to 0, 8, 16, 24, ... (Decimal number display) by the shifter 301. As a result, even if the addresses input from the outside to the color conversion device are continuous addresses, the storage as shown in FIG. 8 is possible as in the second embodiment. The selector 302 selects the 1-b side when storing the lower 8-bit data in the LUT and when performing the color conversion process.

According to the above construction, the operation is the same as that of the second embodiment, and hence the description thereof is omitted.

According to this embodiment, both the preceding storage of the most significant bit data and the storage of the lower eight bit data are apparently continuous address accesses, so that DMA can be performed on both of them and the data transfer time can be further shortened.

(Fourth Embodiment) FIG. 10 is a block diagram showing the arrangement of a color conversion apparatus according to the fourth embodiment of the present invention.

In this embodiment, in the second and third embodiments described above, the address of the most significant bit data to be stored in the LUT in advance is not apparent to the color conversion device, but is actually used in the device. It is intended to be continuous. In order to realize this, an address conversion unit 401 and a selector 402 for selecting its output are provided.

The address conversion unit 401 shifts the address signal input from the terminal 101 by 3 bits lower and then adds the offset value. The offset value to be added is the value of the start address of the most significant bit data that was stored in advance, and this value appears on the address signal when the most significant bit data is actually stored in advance. It can be latched and held.

Since the address converter 401 is not used when the most significant bit data is stored in advance at consecutive addresses, the selector 402 selects the 2-b side. That is, the continuous address for storing the most significant bit data is input from the terminal 101. By the way, this continuous address raises the question of which address should be the starting point. As is clear from the above description of the above-described embodiments, the most significant bit data stored in advance is finally overwritten with the 9-bit table data and disappears. Therefore, it is necessary to store the data so that the unused most significant bit data is not erased. Therefore, the most significant bit data of the last set is set to the LUT 107.
Be stored at the final address of.

When the most significant bit address is stored in advance by the above method, the lower 8 bit data is stored next.

First, an address designating address 0 of the LUT 107 is input to the terminal 101. The second one already explained
Similar to the third embodiment, before storing the first lower 8-bit data of each set, the most significant bit data of the corresponding set must be loaded into the shift register 103. This data is not located at address 0 as in the second and third embodiments, but at a completely different address, but that address is obtained by the address converter 401. Therefore, the data to be loaded into the shift register 103 is stored in the LUT 107.
The selector 402 selects the 2-a side only when reading from, and otherwise selects the 2-b side.

By performing the control described above, the required most significant bit data is loaded into the shift register 103 at a predetermined timing, and thereafter, the above-described second and third bits are loaded.
The lower 8 bits of data are sequentially transferred from the ROM to the color conversion device of this example in the same manner as in the embodiment of FIG.
Data for table of bits can be stored.

In the four embodiments described above, the input data size of the LUT was all 9 bits, but in these four embodiments, the data size is 8 + 2 ^k (k =
It can be easily extended to 1, 2).

Specifically, when k = 1, that is, when the number of output data bits of the LUT is 10 bits, one set of data is 4, and the data output from the shift register is the upper 2 bits, which is the terminal 102. It may be added to the higher-order bits of the data input from to make it 10 bits and then stored in the LUT.

At this time, the number of shifts per data in the shift register is 2 bits. It uses two 4-bit shift registers, one shift register with only the most significant bit and the other register with the two most significant bits.
The above operation may be achieved by loading only the 2nd bit, or a normal shift register with 2 clocks.
It may be input twice to realize 2-bit shift.

In addition, four high-order 2-bit data are collected to obtain 8
The bit data is preceded by the lower 8-bit data and L
When storing in the UT, according to the second and third embodiments, it is sufficient to store every four addresses, and the shift amount of the shifter 301 in the third embodiment is 2 bits.

Further, when k = 2, that is, when the number of output data bits of the LUT is 12 bits, one set of data is 2, but the configuration in this case can be understood from the case of 9 bits and 10 bits. .

The number of output data bits of the LUT is 8 + 2 ^k
When (k = 0, 1, 2) bits are not obtained, for example, 11
Bits are as follows.

There are two methods for this, the first is 11
Add a dummy 1 bit to the top of the bit data,
This is a method in which 12 bits are used and processing is performed in the same configuration as in the first to fourth embodiments, and when the data is stored in the LUT, only the effective lower 11 bits are stored.

The second is a method of processing using another packing method, which will be described in the fifth and sixth embodiments. This method is also effective for all bit numbers, that is, 9 to 15 bits.

(Fifth Embodiment) FIG. 11 is a block diagram showing the arrangement of a color conversion apparatus according to the fifth embodiment of the present invention.

The major difference between the present embodiment and the first to fourth embodiments described above is the external memory RO.
This is the packing format of the packing data stored in M. The packing format used in this embodiment is shown in FIG.

As is clear from this figure, the 11-bit LUT data are concatenated in order from the head data (the most significant bit (MSB) of the next data is immediately to the right of the least significant bit (LSB) of the head data. They are arranged and arranged as a one-dimensional bit string), arranged, cut out in 8-bit units from the beginning, and stored in order from address 0 of the ROM.

In order to handle such packing format data, as shown in FIG. 11, the color conversion apparatus of this embodiment has a 10-bit register 501 having no shift function.
And a selector 5 for selecting the input data of the register 501
02, shift amount of shifter 503 and shifter 503 for outputting desired 11-bit data from 18-bit data obtained by combining 8-bit data input from terminal 102 and 10-bit data output from register 501 And a selection signal output terminal 505. In addition, the LUT 107 of this embodiment
The input data bit width of is of course 11 bits.

The other input / output terminals have the same functions as those in the first to fourth embodiments.

In the basic processing of this embodiment, first, the terminal 1
The 8-bit data input from 02 is taken into the register 501, the 8-bit data output from the register is concatenated to the higher-order input 8-bit data, and the 11-bit table data is selected by the shifter 503. And store it in the LUT 107.

However, the output of the shifter 503 does not always have the desired 11-bit data.
There may be only 8 bits, 9 bits, or 10 bits in the bits. In such cases, shifter 5
The 8th, 9th or 10th bit output from the register 03 is fetched again in the register 501, held therein, and prepared for the next input. In the above-described operation, the selector 502 selects the H-side input, and otherwise selects the L-side input.
Although it is necessary to control the selector 502, this control is performed by the shift amount control unit 504. More specifically, when the shift amount control value sent from the shift amount control unit 504 to the shifter 503 is 8 or more (the upper limit of the shift amount control value by the shift amount control unit 504 is limited to 8 as described later). Therefore, the number of valid bit data output from the shifter 503 is 10 bits or less. Shifter 50
The operation of No. 3 is all 18 input when the shift amount is m bits.
The upper m bits of the bit data are removed, followed by (1
This is because 8-m) bits are output. In such a case, since 11-bit data cannot be stored in the LUT 107, it is necessary to hold the data in the register 501 again. Therefore, when the shift amount control value output from the shift amount control unit 504 is 8 or more, the selector 50
The control signal of 2 becomes High, and the selector 502 selects the input on the H side. On the other hand, when the shift amount control value is 7 or less, the control signal of the selector becomes Low, and the selector 502
Selects the input on the L side.

FIG. 13 is a circuit block diagram showing an example of the internal configuration of the shift amount control unit 504.

By the adder 601, the comparator 602, the gate circuit 603, the subtractor 604 and the register 605, the constant "3" is added to the output value (initial value) of the register 605 by the operation of modulo 11 every cycle. It Here, the calculation of modulo 11 means that when the addition result is 11 or more, 11 is subtracted from the value and the operation result is 0 or more and 10 or more.
It is to be included in the following.

Further, the comparator 606 and the selector 607.
Thus, the output of the register 605 is further limited to 8 or less, and the value is output from the terminal 608 as a shift amount control value.

The comparison result of the comparator 606 is output to the terminal 609. This output value is High when the output value of the register 605 is 8 or more, and Low when the output value is less than 8. The register 605 is set to 10 as an initial value.

Subsequent register values and terminal 60
The output of 8,609 is the value shown in FIG.

From the operation of the shift amount control unit 504 described above, the operation of the configuration shown in FIG. 11 according to the present embodiment can be understood. The operation will be described below.

In this embodiment, 11 bytes of data (11 bits × 8 pieces) form one set, so to fully explain the operation of the present embodiment, 11 bytes, that is, 11 clock cycles. However, the input data and output data of the shifter 503 and the input data of the register 501 in each cycle are shown in FIG. The description is omitted.

In FIG. 11, first, at the terminal 102, the contents of address 0 of the external memory (ROM) a ₁₀ a ₉ ... A ₄ a ₃
However, an address signal designating address 0 of the LUT 107 is input to the terminal 101, respectively. Shift amount control unit 50
Since the internal register 605 of No. 4 is set to the initial value 10, the control signal of the selector 502 is High and the shift amount of the shifter 503 is 8 bits. Therefore, in the data input from the terminal 102, the upper 8 bits are removed by the shifter 503 after the upper 10 bits of data are added, and as a result, XXa ₁₀ a ₉ ... A ₄ a ₃ (X represents an indefinite signal). 10 bits (shown below)
Entered in. When the above data is input, the signal output from the terminal 505 is High, which means that data is not stored in the LUT 107.

The address signal input to the terminal 101 is generally given from a CPU or a DMA controller. Here, if given from the CPU,
The CPU monitors the output signal of the terminal 505, and when this output signal is High, the previous value is held without incrementing the address signal. Further, when the output signal is Low, the address designation of the LUT 107 can be accurately managed by incrementing the address signal.

In the next cycle, the contents of the first address of the ROM a ₂ a ₁ a ₀ b ₁₀ ...
₆ is input from the terminal 102. At this time, since the value of the internal register 605 of the shift amount control unit 504 is “2” (see FIG. 14), the control signal of the selector 502 and the output signal of the terminal 505 are Low, and the shifter 50 is low.
The shift amount of 3 is 2 bits.

As a result, the 8
The upper bit data _{a 2 a 1 a 0 b 10} ... b 6, XXa
₁₀ ... a ₃ with 10 bits added, XXa ₁₀ ... a ₀ b
It becomes 18 bits of ₁₀ ... b ₆ and the most significant 2 bits (X
X) is removed, the upper 11 bits a ₁₀ ... A ₀ are LU
It is stored in the address 0 of T107. At this time, register 50
A 10-bit signal obtained by adding the upper 2 bits (XX) to the 8-bit data input from the terminal 201 is input to 1 via the selector 502.

After this, the signals of the respective parts are changed and the 11-byte data of 1 set is changed to L as in the list shown in FIG.
It is stored in the UT 107. Subsequent data storage is the same as the above 1
It is performed by repeating a cycle in which 1 byte is 11 sets.

Although the present embodiment has shown the structure corresponding to only 11-bit data (the output bit number of the LUT has the same meaning as 11 bits), it can be easily expanded to any of 9 to 15 bits. Specifically, the number of bits of the register 501 and the value of each unit in the shift amount control unit 504 may be determined based on the parameters shown in FIG.

If a maximum length of 14 bits is secured for the register 501 and the value of each part in the shift amount control section 504 can be set programmable, the same configuration can correspond to any of 9 to 15 bits.

(Sixth Embodiment) FIG. 17 is a block diagram showing the arrangement of a color conversion apparatus according to the sixth embodiment of the present invention.

The data packing format in this embodiment is the same as that in the fifth embodiment. In this packing format, the input data bit width of the LUT is 8 + 2 ^k (k
In the case of = 0, 1, 2), the control method is relatively simple unlike the other cases. This is shown in this embodiment.

In the case of this example, the selector 502 is unnecessary in the configuration of FIG. 11 according to the fifth example, and FIG.
It is only necessary to use the 3-bit counter 701 in place of the shift amount control unit 504 having the relatively complicated structure shown in FIG.

In this embodiment, k = 1, that is, the input data bit width of the LUT is 10 bits. The contents of the external memory (ROM) in this case are shown in FIG. 1
In the case of 0 bit, 5 bytes of data form one set, so only 5 bytes are shown. The element block different from that of FIG. 11 according to the fifth embodiment is only the 3-bit counter 701, and this operation will be described.

In FIG. 17, the counter 701 is set to 4 as an initial value, and at this time, only the most significant bit of the output of 3 bits becomes "1" and other bits become "0". This most significant bit is output to the terminal 505 and also used as a clear signal for the counter 701. Therefore, in the next cycle, the counter value returns to "0" and then 1
When it counts up one by one and reaches '4' again, it returns to 0 again.

The lower 2 bits of the counter 701 are sent to the shifter 503. The number of input bits of the shift amount control signal of the shifter 503 in this embodiment is 3 bits, and the upper 2 bits thereof are 2 bits of the counter output. Enter. Input 0 to the remaining input terminals. Therefore, the shift amount of the shifter 503 is four kinds of 0, 2, 4, and 6 bits.

In FIG. 17, the relationship between the output signal of the terminal 505 and the address signal input from the terminal 101 is the same as that of the fifth embodiment described above, and therefore its explanation is omitted.

The contents a ₉ ... A ₂ of the address 0 of the ROM input to the terminal 102 are taken into the register 501 and the first cycle ends. In the next cycle, register 501
From a ₉ ... a ₂ is output, the contents to the terminal 102 of the first address of the _{ROM a 1 a 0 b 9 ...} b 4 is input. The two data are input is connected to _{a 9 ... a 2 a 1 a} 0 b 9 ... b 4 , and the shifter 503. At this time, shifter 503
Shift amount 0 bit, namely what is the most significant bit is also not removed, 10 bits of data, ie _{a 9 a 8 ... a 1 a} 0 starting with a ₉ is output from the shifter 503 L
It is stored in the UT 107.

Then, the current input data a ₁ a ₀ b ₉ ... B ₄ is taken into the register 501, and the second cycle is completed.

In the next cycle, data: a ₁ a ₀ b ₉
.. b ₄ is output from the register 501, and the data at address 2 of the ROM: b ₃ ... b ₀ c ₉ ... c ₆ is input from the terminal 102. As in the previous cycle, these two data are concatenated into a ₁ a ₀ b ₉ ... B ₄ b ₃ ... B ₀ c ₉ ... C ₆ and are input to the shifter 503. Shifter 503 at this time
Since the shift amount by 2 is 2 bits, the most significant 2 bits: a ₁ a ₀ are removed and the upper 10 bits of the remaining data: b ₉ b ₈ ... b ₁ b ₀ are output from the shifter 503 and the LUT 107 Stored in. Then register 501
To, the current input data _{b 3 ... b 0 c 9 ...} c 6 is taken, the third cycle is completed.

After that, the same processing is performed, and FIG. 19 explains how the output of the register 501 and the input / output of the shifter 503 change in this processing.

In this embodiment, the case where the number of input data bits of the LUT is 10 is shown, but other bits, for example, 9 bits are used.
In the case of bits, the counter 701 changes from 3 bits to 4 bits, and the signal sent to the shifter 503 becomes the lower 3 bits.

(Seventh Embodiment) FIG. 20 is a block diagram showing the arrangement of a color conversion apparatus according to the seventh embodiment of the present invention.

In all of the six embodiments described so far, the data of 9 to 15 bits is packed in 8-bit units and the data is transferred to the data conversion device including the LUT in the unit. In the embodiment, packing is performed in units of 16 bits, and data is transferred in that unit. The embodiment which is the basis of this embodiment is the above-mentioned sixth embodiment, and the other conditions are the same as the sixth embodiment except that the packing unit and the data transfer unit are different. Since the unit of packing and data transfer is 16 bits, the size of registers, shifters, etc. changes accordingly.

The most significant bit of the register 803 is input to the clock terminal of the register 801. As a result, the 16-bit data input from the terminal 102 when the most significant bit signal changes from Low to High is taken into the register 801. An external CPU or the like that controls the data supply to the terminal 102 monitors the signal output to the terminal 805, and when this signal becomes High, reads the next 16-bit data from an external memory such as a ROM, Terminal 1
Enter in 02.

From the number of input data bits of the LUT 107,
When the number of bits of data input from the terminal 102 is larger, the data storage in the LUT 107 is executed every cycle, but the data input to the terminal 102 must be performed intermittently. The signal output to the terminal 805 is used for the control.

The operation of the color conversion apparatus of this example from the initial state will be described below with reference to FIG.

[0112] First, the output of the register 803 is set to an initial value '7', most terminal 102 first 16-bit _{data: a 8 ... a 0 b 8} ... b 2 is input. This is the initial state (first cycle).

In the next cycle, "9" is added to the initial value "7", and "16" is output from the register 803. At this time, the most significant bit becomes High,
The 16-bit data input to the terminal 102 in the immediately preceding cycle is taken into the register 801. Also, terminal 8
The next 16-bit data for High is output to _{05: b 1 b 0 c 8} ... c 0 d 8 ... d 4 is input to the terminal 102. Since the storage of data in the LUT 107 is started from this cycle, the address signal designating the address 0 of the LUT is input to the terminal 101.

The shifter 802 has a total of 3 bits including the upper 16 bits from the register 801 and the lower 16 bits from the terminal 102.
2 bits are input, and a 4-bit signal designating the shift amount of the shifter 802 is given from the register 803. These 4 bits are the lower 4 bits of the 5 bits output by the register 803 and have a value of 0 in the current cycle. Therefore, the higher 9 bits of 32 bits a ₈ ... A ₀ input to the shifter 802 are output from the shifter 802, and the LU
It is stored in T107.

In the next cycle, the register 803
'9' is added to the output '0' in the previous cycle of the lower 4 bits of, and the result '9' is output from the register 803. At this time, the most significant bit returns to Low. Therefore, in this cycle, there is no acquisition of data to the 16-bit register 801 or new data input from the terminal 102, and the same 32-bit signal as in the previous cycle is input to the shifter 802. However, since the LUT 107 is stored every cycle, only the address signal is incremented.

[0116] Also signal inputted to the shifter 802 is the same, since the shift amount is changed from '0''9', 9 bits of a ₈ ... a ₀ output in the previous cycle shifter 8
02, the upper 9 bits of the remaining data, that is, b ₈ ... B ₀ are output from the shifter 802, and LUT1
It is stored in address 1 of 07.

Similarly, LUT address 2, address 3, ...
9-bit data is stored. In the initial state and in each cycle, the input signal of the shifter 802, the shift amount,
The value of the most significant bit of the 5-bit register 803 is shown in FIG.
Shown in.

The present invention relates to a data conversion device using an LUT, and more particularly to a method of storing data in the LUT, and the present invention is not limited to the three-dimensional LUT described in each of the above-mentioned embodiments, but a conventional example. The one-dimensional LUT, etc.
It goes without saying that it can be applied to all LUTs, and the number of bits of data input to the LUT is not limited to the 9 to 11 bits shown in the above embodiment. Furthermore, in each of the above-described embodiments, the data conversion device including the three-dimensional LUT and the interpolation calculation part has been described. It is applied.

[0119]

As described above, according to the present invention,
When storing the table data of the look-up table in the data conversion device, if the packing data to be stored in the look-up table is input, the data is held by the holding means having a register or the like, and a part or all of the data and new data are stored. The table data to be stored in the lookup table is generated by combining some or all of the packing data input to the. As a result, the data conversion device can receive and restore the packed data as it is and use it.

As a result, the capacity of the external memory for storing the table data can be minimized and the processing such as the transfer of the table data can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional color conversion device including a three-dimensional LUT and an interpolation calculation unit.

FIG. 2 is an explanatory diagram showing a positional relationship of eight pieces of data output from a three-dimensional LUT.

FIG. 3 is a block diagram showing a configuration of a color conversion device according to a first embodiment of the present invention.

FIG. 4 is a schematic diagram showing the contents of an external memory (ROM) in the first embodiment.

FIG. 5 is a schematic diagram showing the contents of 9-bit data stored in the LUT in the first embodiment.

FIG. 6 is a block diagram showing a configuration of a color conversion device according to a second embodiment of the present invention.

FIG. 7 is a schematic diagram showing the contents of an external memory (ROM) in the second embodiment.

FIG. 8 is a schematic diagram showing 8-bit data stored prior to an LUT in the second embodiment.

FIG. 9 is a block diagram showing a configuration of a color conversion device according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a color conversion device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a color conversion device according to a fifth embodiment of the present invention.

FIG. 12 is a schematic diagram showing the contents of an external memory (ROM) in the fifth embodiment.

13 is a block diagram showing an example of a configuration of a shift amount control unit 504 in FIG.

14 is an explanatory diagram showing a transition of output values of main parts in the shift amount control unit shown in FIG.

FIG. 15 is an explanatory diagram showing a transition of input / output values of a main part in the fifth embodiment shown in FIG.

FIG. 16 is an explanatory diagram showing various parameters when the fifth embodiment is applied to other applications (the number of bits of the LUT is arbitrary from 9 to 15).

FIG. 17 is a block diagram showing the configuration of a color conversion device according to a sixth embodiment of the present invention.

FIG. 18 is a schematic diagram showing the contents of an external memory (ROM) in the sixth embodiment.

FIG. 19 is an explanatory diagram showing changes in input / output values of main parts in the sixth embodiment.

FIG. 20 is a block diagram showing the configuration of a color conversion device according to a seventh embodiment of the present invention.

FIG. 21 is an explanatory diagram showing changes in input / output values of main parts in the seventh embodiment.

[Explanation of symbols]

 101 LUT address signal input terminal 102 packing data input terminal 103 shift register 104 counter 107 LUT 109 conversion data output terminal 201 '000' detection block 301, 503, 802 shifter 401 address converter 302, 402, 502, 607 selector 501 , 605, 801 register 504 shift amount control unit 601, 804 adder 602, 606 comparator 604 subtractor 701 3-bit counter 803 5-bit register

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06T 5/00 H04N 1/46 8420-5L G06F 15/66 310 9191-5L 15/68 310 310 A 4226 -5C H04N 1/46 Z 8125-5L G06F 15/62 310 A

Claims (8)

[Claims] 1. A data conversion device for converting data using a look-up table, wherein table data written in the look-up table is stored as a plurality of packing data having a size different from the data size from the memory. Holding means for temporarily holding one of the plurality of packing data input to the conversion device, and the plurality of packings for inputting all or part of the packing data held by the holding means to the data conversion device. A data conversion device comprising: a connection unit for connecting the data to another data; and a storage unit for storing the data connected by the connection unit as the table data in the lookup table. 2. The data conversion device according to claim 1, wherein the holding unit has one or a plurality of shift registers. 3. One of a plurality of the packing data is stored in advance in the look-up table as it is, and the stored data is read and held in the shift register. The described data converter. 4. When one of the plurality of packing data is stored in advance in the look-up table, the address signal of the look-up table is bit-shifted, and when not stored, the address signal is stored. 4. The data conversion apparatus according to claim 3, wherein the bit shift of step 1 is not performed. 5. When one of the plurality of packing data is stored in advance in the lookup table, it is stored in consecutive addresses of the lookup table,
4. The data conversion device according to claim 3, further comprising address conversion means for generating a read address when the stored data is read and held in the shift register from a write address of the lookup table. 6. The holding means comprises a register and a shifter for selecting the table data to be stored in the lookup table from the connected data. 1. The data conversion device described in 1. 7. The data converter according to claim 6, wherein the data held in the register is the input packing data or the output data of the shifter. 8. A data conversion device for converting data using a look-up table, wherein the data to be stored is packed in a number of look-up tables and stored in another memory in advance. Data converter.