JPH0774958A - Method and device for storing picture - Google Patents

Abstract

PURPOSE:To make it almost unnecessary to detect block distortion and to hold a picture of high picture quality by separating and storing the block average of image data in an extracted gradation memory even in the case of a block having no extracted picture element and making it unnecessary for an encoding means to encode the block average. CONSTITUTION:A character/line drawing extracting circuit 4 extracts picture elements constituting a character/line drawing included in an 8X8 image data e.g inputted from a blocking circuit 3, stores the positional information of the extracted picture elements in an extraction judging memory 9 and outputs gradation data to a gradation (i.e., color data) selector 7. An extracted block judging signal indicating the existence of extracted picture elements in a block concerned is outputted to the selector 7 through a mean value separating circuit 6 and the gradation data are stored in a memory control circuit 10 as an address through an extraction gradation memory 11. A backgound color, i.e., white, is previously initialized in the of an image area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage method and apparatus, and more particularly to an image storage method and apparatus for storing image information in which line drawings such as characters and graphics and halftone images such as photographs are mixed. is there.

[0002]

2. Description of the Related Art As a method for efficiently storing image information in which line drawings such as characters and graphics (hereinafter referred to as "text") and halftone images such as photographs (hereinafter referred to as "image") are mixed, For example, an image is divided into small blocks of 8 × 8 pixels, text is extracted, and then orthogonal transformation such as discrete cosine transformation (hereinafter referred to as “DCT”) is performed,
The present applicant has proposed to encode and store the coefficient.

FIG. 8 shows a block diagram of an image storage device according to the image information recording method.

In FIG. 8, image data in which text and an image are combined and layout information of the image data are input to a terminal 51 from an external host computer, a formatter, or the like.

The data separation circuit 52 separates image data and layout information from the data input through the terminal 51, and outputs the layout information to the blocking circuit 53, the memory control circuit 58, and the decoding circuit 62. Also, the image data is output to the blocking circuit 53.

The blocking circuit 53 is a data separation circuit 5
The image data input from 2 is cut out for each small block of 8 × 8 pixels.

The character / line drawing extraction circuit 54 extracts the pixels forming the character / line drawing included in the image data of 8 × 8 pixels (hereinafter referred to as “block”) input from the blocking circuit 53, and extracts the extracted pixels. The judgment result (position information of the extracted pixel) is stored in the extraction judgment memory 57, and the gradation (color) data of the extracted pixel is stored in the extraction gradation memory 59.

The extracted pixel replacement circuit 55 uses the judgment result of the character / line drawing extraction circuit 54 to extract the extracted pixel data of the block input through the character / line drawing extraction circuit 54, for example, the average of the pixels excluding the extracted pixels in the block. Replace with a value etc.

The encoding circuit 56 has an extracted pixel replacement circuit 55.
Block input from the so-called JPEG ADC
Encoding is performed by a method suitable for halftone image data such as the T method or vector quantization.

The image memory 61 is a memory control circuit 6
When 0, the coded data output from the coding circuit 56 is stored.

On the other hand, a printer engine (not shown) is connected to the terminal 65, and when the printer engine is started, an engine synchronizing signal is input to the memory control circuit 58 and the decoding circuit 62 via the terminal 65. To be done.

The memory control circuit 58 uses the extraction judgment memory 5
7 and the data stored in the extracted gradation memory 59 are controlled so that the data are read in synchronization with the engine synchronization signal.

The decoding circuit 62 outputs a request to the memory control circuit 60 so that the image data is output from the engine synchronization signal at a timing according to the layout information input from the data separation circuit 52. The encoded data is read from the memory 61. continue,
The decoding circuit 62 rasterizes the data obtained by decoding the encoded data input from the image memory 61 in the image area designated by the layout information, and rasterizes the white (background color) data outside the image area. Output to the circuit 63.

The rasterization circuit 63 restores the block data input from the decoding circuit 62 to the original raster scan data and outputs it to the synthesis circuit 64.

The synthesizing circuit 64 synthesizes the gradation data read from the extraction gradation memory 59 and the image data input from the rasterizing circuit 63 based on the judgment result read from the extraction judgment memory 57. Then, the original input image data is restored and the image data is output to the printer engine via the terminal 66.

[0016]

However, in the above example, when there is no pixel extracted by the character / line drawing extraction circuit 54 in the block, the extraction gradation memory 59 is not used and is wasted. was there.

Desktop publishing (hereinafter "DT
In the image data created by
The ratio of pixels extracted by the character / line drawing extraction circuit 54 is usually about several percent to several tens of percent, and particularly when the area of a halftone image such as a photograph is large, The ratio becomes small and the extracted gradation memory 59 is hardly used and is wasted. On the other hand, since the capacity of the image memory 61 is fixed, the larger the area of a halftone image such as a photograph is, the higher the compression rate by the encoding circuit 56 is, and the image quality is deteriorated. .

The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide an image storage method and apparatus with high memory utilization efficiency.

[0019]

In order to achieve the above object, an image storage device according to the present invention has the following configuration.

That is, blocking means for cutting out image data into a predetermined block, predetermined pixels are extracted from the blocked image data, and position information of the extracted pixels is stored in the first storage means. Extraction means for storing the gradation data of No. 2 in the second storage means, replacement means for replacing the pixels extracted by the extraction means with predetermined data, and an average of blocks having no pixels extracted by the extraction means. A code for separating the values and storing the average value in the second storage means, and a code for encoding the image data of which the average value has been separated by the average value separation means and storing it in the third storage means. And a conversion means.

Further, the image storing method according to the present invention for achieving the above object includes the following steps.

That is, a block forming step of cutting out image data into a predetermined block, a predetermined pixel is extracted from the blocked image data, and position information of the extracted pixel is stored in the first storage means. A step of storing the gradation data of 1. in the second storage means, a step of replacing the pixels extracted by the extraction step with predetermined data, and an average value of blocks having no pixels extracted by the extraction step. And an average value separation step of storing the average value in the second storage means, and an encoding step of encoding the image data of which the average value has been separated by the average value separation step and storing the encoded image data in the third storage means. And a process.

[0023]

With the above configuration, in the block having no extracted pixel at all, the separated average value is stored in the second storage means, and in the encoding means,
Since the block average value need not be coded, the coding efficiency is improved and the image quality is improved.

[0024]

<Embodiment 1> FIG. 1 is a block diagram showing an example of the arrangement of an image storage device according to Embodiment 1 of the present invention.

In FIG. 1, reference numeral 1 denotes an input terminal to which image data in which text and an image are combined and layout information of the image data are input from an external host computer, a formatter or the like.

Reference numeral 2 denotes a data separation circuit which separates image data and layout information from the data input through the terminal 1 and outputs the layout information to the blocking circuit 3, the memory control circuit 10 and the decoding circuit 14. , And outputs the image data to the blocking circuit 3.

Reference numeral 3 is a block circuit, which is a data separation circuit 2.
The image data input from is cut out for each small block of 8 × 8 pixels.

Reference numeral 4 denotes a character / line drawing extraction circuit, which extracts the pixels forming the character / line drawing included in the image data of 8 × 8 pixels input from the blocking circuit 3, and determines whether or not the pixel is an extracted pixel ( The extracted pixel position information) is stored in the extraction determination memory 9 and output to the gradation (color) data selector 7 of the extracted pixel. Also, the extraction block determination signal indicating the presence or absence of the extraction pixel in the block is output to the average value separation circuit 6 and the selector 7.

Reference numeral 5 denotes an extraction pixel replacement circuit, which determines the pixel data extracted by the character / line drawing extraction circuit 4 from the judgment result of the character / line drawing extraction circuit 4 by a value convenient for encoding to be described later.
For example, the average value of the pixels excluding the extracted pixels in the block is replaced.

An average value separation circuit 6 separates the block average value from the input image data according to the extraction block determination signal input from the character / line drawing extraction circuit 4, and separates the average value from the input image data. Is output to the selector 7 and the image data obtained by subtracting the block average value from the input image data is output to the encoding circuit 8.

Reference numeral 7 denotes a selector which, in accordance with the extraction block determination signal input from the character / line drawing extraction circuit 4, outputs the gradation (color) data of the extraction pixel when the block has an extraction pixel,
If there is no extracted pixel in the block, the block average value input from the average value separation circuit 6 is stored in the extracted gradation memory 11.

An encoding circuit 8 encodes the image data input from the average value separating circuit 6 by a method suitable for halftone image data such as the JPEG ADCT method or vector quantization.

Reference numeral 9 is an extraction judgment memory, and the judgment result as to whether or not it is an extraction pixel input from the character / line drawing extraction circuit 4, for example, the bit corresponding to the extraction pixel is set to "1" and the other bits are set to "0". It is stored as the bitmap data set to "." Note that the extraction determination memory 9 is assumed to be initialized to "1" in advance in order to prevent malfunction of the average value determination circuit 15 described later.

Reference numeral 10 denotes a memory control circuit, which extracts the determination result (position information of the extracted pixel) output from the character / line drawing extraction circuit 4 and the gradation data output from the selector 7, respectively. Judgment memory 9 and extracted gradation memory 1
Each memory is controlled so as to be stored in the corresponding address of 1. On the other hand, when the printer engine synchronization signal is input through the terminal 19, the extraction determination result is read from the extraction determination memory 9 in accordance with the synchronization signal, and is read to the average value determination circuit 15 and the synthesis circuit 17 at predetermined timings. The extraction determination memory 9 is controlled to output. Further, grayscale data is read from the extracted grayscale memory 11 according to the synchronization signal,
The extraction gradation memory 11 is controlled so as to output to the average value synthesizing circuit 16 and the synthesizing circuit 17 at each predetermined timing.

Reference numeral 11 denotes an extraction gradation memory, which stores gradation data output from the selector 7 at an address indicated by the memory control circuit 10. In order to prevent the invalid data from flowing out of the image area, the extracted gradation memory 9 is preliminarily initialized to white (background color) data.

A memory control circuit 12 controls the image memory 13 so that the coded code output from the coding circuit 8 is stored in a corresponding address of the image memory 11. On the other hand, at the time of decoding, control is performed so that the coded code stored in the image memory 11 is read according to a control signal input from a decoding circuit 14 described later.

An image memory 13 stores the encoded code output from the encoding circuit 8 at an address indicated by the memory control circuit 12.

Reference numeral 14 denotes a decoding circuit, which outputs image data at a timing corresponding to the layout information input from the data separation circuit 2 in accordance with a printer engine synchronizing signal input via a terminal 19. The request is output to the memory control circuit 12, the encoded data is read from the image memory 13, and is decoded. Then, the decoded data is output to the average value synthesis circuit 16.

Reference numeral 15 is an average value judgment circuit, which is a decoding circuit 14
The extraction determination result of the block that has been decoded in (1) is read from the extraction determination memory 9, the block in the image area that does not have the extracted pixel at all is determined, and the determination result is output to the average value synthesis circuit 16. . Outside the image area, the extraction determination memory 9 is initialized to determine that there are extracted pixels.

Reference numeral 16 is an average value synthesizing circuit, and in accordance with the determination signal input from the average value determination circuit 15, the image data output from the decoding circuit 14 includes the extracted gradation memory in the block in which the extracted pixel is not present at all. The average value of the corresponding block read from 11 is added, 0 is added when the extracted pixel is present in the block, and the result is output to the rasterization circuit 18.

Reference numeral 18 is a rasterization circuit, which is an average value synthesis circuit 1
The block-shaped image data input from 6 is converted into the original raster scan and output to the synthesis circuit 17.

Reference numeral 17 denotes a synthesizing circuit, which synthesizes the gradation data read from the extraction gradation memory 11 and the image data input from the rasterizing circuit 18 based on the judgment result read from the extraction judgment memory 9. Then, the original input image data is restored, and the image data is output to the printer engine via the terminal 20. That is, when the extraction judgment result is "1", the gradation data read from the extraction gradation memory 59 is output, and when the extraction judgment result is "0", the rasterization circuit 1 is output.
The image data input from 8 is output.

Reference numeral 19 denotes an input terminal to which a printer engine (not shown) is connected. When the printer engine is started, an engine synchronizing signal is sent to the memory control circuit 10 and the decoding circuit 14 via the terminal 19. Is entered.

An output terminal 20 is connected to the printer engine, and outputs the image data restored by the synthesizing circuit 17 to the printer engine.

As described above, in the image storage device of the first embodiment, the extracted block average value is stored in the extraction gradation memory 11 even in the block having no extracted pixel at all, so that extraction is performed. There is no waste of gradation memory. Further, in the encoding means, since the block average values are separated, it is not necessary to encode the block average values, the encoding efficiency is improved, and as a result, the image quality is improved.

<Second Embodiment> FIG. 2 shows a second embodiment according to the present invention.
3 is a block diagram showing a configuration example of the image storage device of FIG. The same processes as those in the first embodiment are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted.

In FIG. 2, reference numeral 21 is a data separation circuit,
The bitmap data, the drawing gradation (color) data, the image data and the layout information of each data are identified from the information input through the terminal 1, and the bitmap data is stored in the bitmap memory 24 and the layout information of the bitmap data. To the memory control circuit 25, the drawing gradation data of the bitmap data to the block gradation memory 26, the image data to the blocking circuit 3, and the layout information of the image data to the blocking circuit 3, the memory control circuit 25 and the decoding. Output to the circuit 14.

Reference numeral 24 is a bit map memory which stores the bit map data and the character data input from the data separation circuit 21.
For example, the bit corresponding to the extracted pixel is set to “1” as the determination result of whether or not the extracted pixel is input from the line drawing extraction circuit 22.
Then, the other bits are stored as bitmap data in which "0" is set. It is assumed that the extraction determination memory 9 is initialized to “0” in advance in order to prevent malfunction of the drawing pixel detection circuits 23 and 27 described later.

Reference numeral 25 denotes a memory control circuit which, when bit map data is input from the terminal 1, outputs the data separation circuit 21.
Each memory is controlled so that the bitmap data and the drawing gradation are stored in the corresponding addresses of the bitmap memory 24 and the block gradation memory 26, respectively, in accordance with the layout information of the bitmap data input more. Also,
When the image data is input from the terminal 1, the bitmap memory 24 is controlled so that the bitmap data of the target block is read and output to the drawing pixel detection circuit 23. Furthermore, the determination result (position information of the extracted pixel) whether the pixel is an extracted pixel output from the character / line drawing extraction circuit 22 and the grayscale data output from the selector 7 are stored in the bit map memory 24 and the block grayscale memory, respectively. Each memory is controlled so as to be stored in 26 corresponding addresses.

On the other hand, when the printer engine synchronization signal is input through the terminal 19, the bitmap data (extraction determination result) is transferred to the bitmap memory 2 in accordance with the synchronization signal.
4, and the bit map memory 24 is controlled so as to output the read pixel data to the drawing pixel detecting circuit 27 and the synthesizing circuit 17 at predetermined timings. Also, according to the synchronization signal,
The gray scale data is read from the block gray scale memory 26, and the block gray scale memory 26 is controlled so as to output the gray scale data to the average value synthesis circuit 16 and the synthesis circuit 17 at predetermined timings.

Reference numeral 26 is a block gradation memory, which outputs the drawing gradation of the bitmap data when the bit map data is input from the terminal 1, and outputs it from the selector 7 when the image data is input from the terminal 1. The gradation data to be stored is stored in the address indicated by the memory control circuit 25. It is assumed that the block gradation memory 26 is initialized to “0” in advance in order to prevent malfunction of the average value synthesis circuit 16 outside the image area.

A drawing pixel detection circuit 23 reads the bitmap data of the block processed by the character / line drawing extraction circuit 22 from the bitmap memory 24. When the bitmap data is all "0", the bitmap is invalid. The signal is output to the character / line drawing extraction circuit 22.

Reference numeral 22 is a character / line-drawing extraction circuit, and only for a block in which the drawing pixel detection circuit 23 determines that the bitmap of the processing block is invalid (that is, when the bitmap data of the processing block is all "0"). , The pixels constituting the character / line drawing included in the image data of 8 × 8 pixels input from the blocking circuit 3 are extracted, and the determination result (position information of the extracted pixels) as to whether the pixel is an extracted pixel is stored in the bitmap memory 24. Stored in the extracted pixel gradation (color) data selector 7
Output to. Further, the extraction block determination signal indicating the presence or absence of the extraction pixel in the block is converted into the average value separation circuit 6 and the selector 7.
Output to.

27 is a drawing pixel detection circuit, which is a decoding circuit 1
4, the extraction judgment result of the block decoded in 4 is read from the bit map memory 24, the block in the image area which does not have the extracted pixel at all is judged, and the judgment result is output to the average value synthesis circuit 16. To do. In addition,
Outside the image area, it is determined that there is no extracted pixel by initializing the extraction determination memory 9, but as described above,
Since the block gradation memory 26 is initialized to “0” in advance, “0” is added in the average value synthesis circuit 16. Therefore, if the pixel data outside the image area is set to have the background color (white) in the decoding circuit 14, the output of the average value synthesis circuit 16 becomes the background color.

In the second embodiment, bitmap data can be written in the extraction judgment memory of the first embodiment, and drawing gradation data can be written in the extraction gradation memory. Normal,
Since it is rare to write bitmap data on image data, almost the same effect as that of the first embodiment can be obtained.

In this embodiment, since the bitmap data is prioritized, the character / line drawing is not extracted except when all the bitmap data of the processing block is "0", but the trailing data is prioritized. In this case, the drawing pixel detection circuit 23 is deleted, and the data in which the extracted pixel position information (bitmap data) of the block from which the average value is separated is all “0” is set in the bitmap memory 2 as in the first embodiment.
It should be stored in 4.

<Third Embodiment> FIG. 3 shows a third embodiment according to the present invention.
3 is a block diagram showing a configuration example of the image storage device of FIG. The same processes as those in the second embodiment are designated by the same reference numerals as those in FIG. 2, and the description thereof will be omitted.

In FIG. 3, reference numeral 28 denotes an encoding circuit, which detects an extracted pixel from the image data input from the extracted pixel replacement circuit 5 when there is no extracted pixel in the block according to the extracted block determination signal input from the character / line drawing extraction circuit 4. D by DCT
The C component (block average value) is separated, the DC component is output to the selector 7, the data other than the DC component is encoded, and stored in the image memory 13. If the block has extracted pixels, the DC component is also encoded and stored in the image memory 13.

Reference numeral 29 is a decoding circuit, which is a drawing pixel detection circuit 2
If there is no drawing pixel (extracting pixel) in the block according to the drawing pixel detection signal input from 7, the DC component input to the block gradation memory 26 is used for decoding, and the decoded image data is sent to the rasterization circuit 18. Output. If the block has a drawing pixel (extracted pixel), decoding is performed using the DC component stored in the image memory 13.

Next, the encoding circuit 28 will be described in detail.

FIG. 4 is a block diagram showing a configuration example of the encoding circuit 28.

In FIG. 4, reference numeral 30 denotes a DCT circuit, which converts the image data input from the signal line 101 into each component for each block, and outputs the DC component to the quantization circuit 31 and the AC component to the scan conversion circuit 32. To do.

A quantizing circuit 31 quantizes the DC component input from the DCT circuit 30 and outputs it to the selector 7 and the switch 34 via the signal line 102.

A switch 34 is turned on only when there is an extraction pixel in the processing block according to the extraction determination signal of the character / line drawing extraction circuit 22 input from the signal line 103, and is input from the quantization circuit 31. The quantized DC component is output to the packing circuit 36.

A scan conversion circuit 32 is a DCT circuit 30.
Convert the input AC component into zigzag scan,
Output to the quantization circuit 33.

A quantizing circuit 33 quantizes the AC component input from the scan converting circuit and outputs it to the VLC circuit 35.

A VLC circuit 35 encodes the quantized AC component input from the quantization circuit 33 by known entropy coding (for example, run length + Huffman coding), and outputs it to the packing circuit 36. .

36 is a packing circuit 36, which is a switch 3
When the DC component is input from 4, the identification code is added to the DC component and then the AC input from the VLC circuit 35.
Packing is performed in a predetermined bit unit together with the encoded code of the component, and when packing is completed, a request is issued to the memory control circuit 12 from the signal line 104 and packing data is output from the signal line 105.

Next, the decoding circuit 29 will be described in detail.

FIG. 5 is a block diagram showing a configuration example of the decoding circuit 29.

In FIG. 5, reference numeral 37 is a DC component separating circuit, which checks the identification code added by the packing circuit 36 from the coded code inputted through the signal line 106, and when the identification code is detected, next. The subsequent DC component data is separated and output to the switch 40. The AC component data is output to the inverse VLC circuit 38.

Reference numeral 40 denotes a switch, which, when it is determined that there is no drawing pixel in the processing block according to the determination result of the drawing pixel detection circuit 27 input from the signal line 109, the signal line 108.
Data (that is, the DC component read from the block gradation memory 26) is output from the DC component separation circuit 37 when it is determined that there is a drawing pixel in the processing block.
The component is selected and output to the inverse quantization circuit 42.

Reference numeral 42 denotes an inverse quantization circuit, which converts the DC component input from the switch 40 into a quantized representative value, and performs inverse DCT.
Output to the circuit 44.

Reference numeral 39 denotes an image area detecting circuit, which is a signal line 1
It is determined whether the printer engine is scanning the image area based on the layout information of the image data input from 12 and the printer engine synchronization signal input from the signal line 110. When the image area is scanned, GO The signal is output to the inverse VLC circuit 38.

Reference numeral 38 denotes an inverse VLC circuit, which outputs a request signal from the signal line 107 to the memory control circuit 12 at a predetermined timing in accordance with the GO signal input from the image area detection circuit 39 and outputs an encoded code from the image memory. read out. Next, the encoded AC component input from the DC component separation circuit 37 is decoded and output to the inverse quantization circuit 41.

Reference numeral 41 denotes an inverse quantization circuit, which is the decoded A
The C component is converted into a quantized representative value, and the scan conversion circuit 43
Output to.

Reference numeral 43 is a scan conversion circuit, which converts the AC component converted into the quantized representative value into a block scan, and inverse D
Output to the CT circuit 44.

Reference numeral 44 converts the DC component and AC component input by the inverse DCT circuit into original image data, and outputs the signal line 111.
Output more.

As described above, in the image storage device of the third embodiment, not only the same effect as the second embodiment is obtained, but also the DC component separated by the encoding is stored in the block gray scale memory. Therefore, it is not necessary to encode the DC component in the encoding circuit 28, the encoding circuit 28 and the decoding circuit 29 are simplified, and at the same time, the encoding efficiency is improved and, as a result, the image quality is also improved. Further, since the DC component stored in the block gray scale memory holds the same number of bits as the depth of the block gray scale memory, block distortion does not occur in principle.

Although the determination result of the drawing pixel detection circuit 27 is used for controlling the switch 40 of the decoding circuit 29 in the third embodiment, the switch is performed only when the DC component is detected by the DC component separation circuit 37. 40 is a DC component separation circuit 3
It may be configured to switch to the DC component output side of 7. In this case, the drawing pixel detection circuit 27 is unnecessary and the configuration is further simplified.

<Fourth Embodiment> FIG. 6 shows a fourth embodiment according to the present invention.
3 is a block diagram showing a configuration example of the image storage device of FIG. It should be noted that the same processes as those in the third embodiment are denoted by the same reference numerals as those in FIG. 3, and the description thereof will be omitted.

In FIG. 6, reference numeral 45 is a background color detection circuit,
The drawing gradation data of the block processed by the character / line drawing extraction circuit 22 is read from the block gradation memory 26, and when the drawing gradation data is the background color, a bitmap invalid signal is output to the character / line drawing extraction circuit 22. To do.

In the fourth embodiment, the block gradation memory 26 is assumed to be initialized to the background color in advance. Therefore, the drawing gradation data of the block in which the bitmap data is not stored is not updated and remains the background color. Therefore, by checking whether the drawing gradation data is the background color, the bitmap memory 24 The usage status of can be detected. In order to prevent a malfunction in the synthesizing circuit 17, writing of the bitmap data whose drawing gradation is the background color into the bitmap memory 24 is prohibited. Also,
In order to improve the utilization efficiency of the block gradation memory 26, the drawing gradation data of the block in which all the bitmap data in the block is “0” is not updated. That is, the drawing gradation data is stored in the block gradation memory 2 only in the block having the drawing pixel.
Write to 6.

Reference numeral 46 denotes a decoding circuit which, when the block has no DC component, performs decoding using the DC component input to the block gradation memory 26 and outputs the decoded image data to the rasterization circuit 18.

Next, the decoding circuit 46 will be described in detail.

FIG. 7 is a block diagram showing a configuration example of the decoding circuit 46. The same processes as those in the third embodiment are designated by the same reference numerals as those in FIG. 5, and the description thereof will be omitted.

In FIG. 7, reference numeral 47 denotes a DC component separation circuit, which checks the identification code added by the packing circuit 36 from the coded code input through the signal line 106, and when the identification code is detected, next. Subsequent DC component data is separated and output to the switch 40, and the switch 47 is controlled to output the DC component to the inverse quantization circuit 42. The AC component data is output to the inverse VLC circuit 38.

Reference numeral 48 is a switch, and when it is determined that there is no DC component in the processing block according to the detection result of the DC component separation circuit, the data of the signal line 108 (that is, the DC component read from the block gradation memory 26). When it is determined that the processing block has a DC component, the DC component separation circuit 3
The DC component output from the output terminal 7 is selected, and the inverse quantization circuit 42 is selected.
Output to.

As described above, the image storage device of the fourth embodiment has the same effect as that of the third embodiment, and the drawing gradation data stored in the block gradation memory 26 has the background color. Since the usage state of the bitmap memory 24 is detected by checking whether or not there is,
The circuit is simplified.

The present invention may be applied to a system composed of a plurality of devices such as a scanner, a host computer, a formatter or the like, or to an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0091]

As described above, according to the image storing method and apparatus of the present invention, the block average value (DC component) of the image data is stored in the extracted gradation memory even in the block having no extracted pixel. ) Is stored separately, so that the extraction gradation memory is not wasted. Further, in the encoding means, since the block average value (DC component) is separated, it is not necessary to encode the block average value (DC component), the encoding efficiency is improved, and as a result, the image quality is improved. Further, since the block average value (DC component) stored in the extracted grayscale memory holds the same number of bits as the depth of the block grayscale memory, almost no block distortion is detected and a high quality image can be held. .

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an image storage device according to a first exemplary embodiment.

FIG. 2 is a block diagram illustrating a schematic configuration of an image storage device according to a second embodiment.

FIG. 3 is a block diagram illustrating a schematic configuration of an image storage device according to a third embodiment.

FIG. 4 is a block diagram illustrating a configuration example of an encoding circuit according to a third exemplary embodiment.

FIG. 5 is a block diagram illustrating a configuration example of a decoding circuit according to a third exemplary embodiment.

FIG. 6 is a block diagram illustrating a schematic configuration of an image storage device according to a fourth exemplary embodiment.

FIG. 7 is a block diagram illustrating a configuration example of a decoding circuit according to a fourth exemplary embodiment.

FIG. 8 is a block diagram of an image storage device according to a conventional image recording method.

[Explanation of symbols]

 2 Data Separation Circuit 3 Blocking Circuit 4 Character / Line Drawing Extraction Circuit 5 Extraction Pixel Replacement Circuit 6 Average Value Separation Circuit 7 Selector 8 Encoding Circuit 9 Extraction Judgment Memory 10 Memory Control Circuit 11 Extraction Grayscale Memory 12 Memory Control Circuit 13 Image Memory 14 Decoding Circuit 15 Average Value Determining Circuit 16 Average Value Composing Circuit 17 Composing Circuit 18 Rasterizing Circuit 21 Data Separation Circuit 22 Character / Line Drawing Extracting Circuit 23 Drawing Pixel Detecting Circuit 24 Bitmap Memory 25 Memory Control Circuit 26 Block Grayscale Memory 27 Drawing pixel detection circuit 28 Encoding circuit 29 Decoding circuit 45 Background color detection circuit 46 Decoding circuit

Claims (8)

[Claims] 1. Blocking means for cutting out image data into predetermined blocks, predetermined pixels are extracted from the blocked image data, and position information of the extracted pixels is stored in a first storage means. Extracting means for storing the gradation data of 1. in the second storage means, a replacing means for replacing the pixels extracted by the extracting means with predetermined data, and an average of blocks having no pixels extracted by the extracting means. A mean value separating means for separating the values and storing the average value in the second storage means, and a code for encoding the image data of which the average value has been separated by the mean value separating means and storing in the third storage means And an image storage device. 2. A first storage means for storing bitmap data, a second storage means for storing a drawing gradation (color) of the bitmap data, and a blocking means for cutting out image data into predetermined blocks. Extracting means for extracting a predetermined pixel from the blocked image data, storing position information of the extracted pixel in a first storage means, and storing gradation data of the extracted pixel in a second storage means, A replacement unit that replaces the pixel extracted by the extraction unit with predetermined data, and an average value of a block having no pixel extracted by the extraction unit is separated, and the average value is stored in the second storage unit. An image storage device comprising: an average value separating means; and an encoding means for encoding the image data whose average value has been separated by the average value separating means and storing the encoded image data in a third storage means. . 3. The extracting means extracts a predetermined pixel from the blocked image data when there is no drawing pixel in the bitmap data corresponding to the blocked image data, and the position of the extracted pixel is extracted. 3. The image storage device according to claim 2, wherein the information is stored in the first storage unit and the gradation data of the extracted pixel is stored in the second storage unit. 4. Blocking means for cutting out image data into predetermined blocks, predetermined pixels are extracted from the blocked image data, and position information of the extracted pixels is stored in the first storage means. Extracting means for storing the gradation data of 1. in the second storage means, replacing means for replacing the pixels extracted by the extracting means with predetermined data, and converting means for orthogonally transforming the replaced image data. The DC component of the converted image data of the block having no pixels extracted by the extracting unit is stored in the second storage unit, the image data other than the DC component is encoded, and stored in the third storage unit. An image storage device comprising: 5. A blocking step of cutting out image data into a predetermined block, extracting a predetermined pixel from the blocked image data, and storing position information of the extracted pixel in a first storage means. A step of storing the gradation data of 1. in the second storage means, a step of replacing the pixels extracted by the extraction step with predetermined data, and an average value of blocks having no pixels extracted by the extraction step. And an average value separation step of storing the average value in the second storage means, and an encoding step of encoding the image data of which the average value has been separated by the average value separation step and storing the encoded image data in the third storage means. An image storage method, comprising: 6. A first storing step of storing bitmap data, a second storing step of storing a drawing gradation (color) of the bitmap data, and a blocking step of cutting out image data into predetermined blocks. An extraction step of extracting a predetermined pixel from the blocked image data, storing position information of the extracted pixel in a first storage step, and storing gradation data of the extracted pixel in a second storage step, A step of replacing pixels extracted by the extracting step with predetermined data, and an average value of a block having no pixels extracted by the extracting step is separated, and the average value is stored in the second storing step. An image storing method comprising: a value separating step; and an encoding step of encoding image data whose average value is separated by the average value separating step and storing the encoded image data in a third storing step. 7. The extracting step extracts a predetermined pixel from the blocked image data when there is no drawing pixel in the bitmap data corresponding to the blocked image data, and the position of the extracted pixel is extracted. 7. The image storing method according to claim 6, wherein the information is stored in the first storing step, and the gradation data of the extracted pixel is stored in the second storing step. 8. A block forming step of cutting out image data into a predetermined block, extracting a predetermined pixel from the blocked image data, and storing position information of the extracted pixel in a first storing step. An extraction step of storing the gradation data of No. 2 in a second storage step, a step of replacing the pixels extracted by the extraction step with predetermined data, a conversion step of orthogonally converting the replaced image data, The DC component of the converted image data of the block having no pixels extracted by the extraction step is stored in the second storage step, the image data other than the DC component is encoded, and stored in the third storage step. An image storage method comprising: an encoding step.