JPH077365B2 - Information processing equipment - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to an atomic update instruction method that supports a multiprocessor configuration in a virtual memory environment.

[Prior Art] With the development of computer systems, not only high-speed processing but also high-level processing is required of computers. Microprocessor that applies semiconductor technology (MP
U) is also required in the field of advanced processing, especially in the field called 32-bit MPU, the tendency is remarkable.

One of the advanced processes is a multiprocessor system consisting of multiple MPUs. In this system, multiple processors operate simultaneously and perform processing, so processing performance can be improved (load balancing), and by connecting different types of MPUs, processing can be outsourced to an MPU suitable for the problem. There are advantages such as (function distribution). In this kind of multiprocessor environment, contention may occur when the MPU accesses the resource. For example, one in the system
When you have only one CRT device, multiple processors can
If you issue an output request to the RT, an image with the output of multiple processors superimposed will be displayed on the screen. At this time, a mechanism for serializing a plurality of requests is required. Normally, to achieve serialization in a multiprocessor environment,
Instructions with interlock such as test and set (TASI) instructions are provided. These instructions realize read-modify-write (abbreviated as RMW) access to the contents of a certain memory area as a single atomic access, even if multiple processors try to access this area at the same time. , So that the correct result (serialized result) can be obtained. For example, the TASI lock_byte instruction makes an RMW access to the information in the memory named lock_byte in an atomic manner without allowing the intervention of other processors. The instruction implements the three steps of reading the lock byte, comparing with 0, and writing a constant (eg 0xff) with interlock. Needless to say, it is necessary to provide such an inseparable mechanism in serialization processing in a multiprocessor environment, but it is also important that the processing time is short. In particular, since the frequency of serialization processing increases as the number of processors increases, high-speed serialization processing is required. On the other hand, in recent MPUs, those incorporating a virtual memory management mechanism (for example, a paging method) have appeared. By adopting a virtual memory management mechanism, programs can be created regardless of the size of the real memory (virtual memory), and by holding an area containing data that is rarely used in secondary memory, There are advantages such as effective utilization, and safe system running (runtime security guarantee) due to the access protection mechanism peculiar to the virtual memory management mechanism. The virtual memory management mechanism frequently rewrites the address translation table which is the information in the memory. This is because when a page is flushed to secondary storage, it is noted that the page is no longer in real memory, when it changes access information (whether it was referenced or rewritten), or which This is the case, for example, when recording the frequency of references to eject a page. At this time, when the operating system (OS) finds out and rewrites the contents of the address translation table, it is convenient if the address can be accessed in the virtual space. It accesses the address translation information (page table entry; abbreviated as PTE) of a page containing a virtual address, and the hardware automatically finds the PTE according to the architecture-defined address translation path. Therefore, the software is faster than the program can find it.

[Problems to be Solved by the Invention] In the multiprocessor environment as described above, serialization processing is frequently performed because these address conversion tables themselves are system resources in the main memory. In particular,
When rewriting the contents of the address translation table, inevitable RMW access is required. In general MPU, the atomic RMW instruction related to the virtual memory management mechanism is not provided, and every time virtual memory management is performed, the entry of the address translation table must be searched and the atomic access must be performed. Then, there was a problem that the speed of the inseparable operation that frequently occurs was reduced.

Therefore, an object of the present invention is to improve the operating speed of the central processing unit.

[Means and Actions for Solving Problems] The present invention relates to an address translation mechanism for implementing a virtual memory system, an instruction implementation unit capable of executing an indivisible update instruction for controlling access to a memory, and a virtual address to a real address. In an information processing apparatus including a plurality of central processing units each including an address conversion unit that enables conversion to the central processing unit, a control line that enables exclusive access of each central processing unit to the memory is provided. The address conversion unit of the processing device has a second address conversion table corresponding to the first address conversion table in the memory that is referred to when the address is converted from the virtual address to the real address, and the first address conversion table is the virtual address. Has an entry in the translation table that holds the relationship between the Performs the exclusive access to the memory by activating the control line when executing the atomic update command for the entry in the translation table, and the entry in the translation table of the second address translation table corresponding to the entry in the translation table of the memory. And an entry in the conversion table of the memory are also updated.

Embodiments First Embodiment The present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the system configuration in the first embodiment of the present invention. In FIG. 1, 100 indicates one MPU. Reference numeral 101 is a bus interface unit that controls communication with the system bus. An address translation unit 102 translates a virtual address into a real address during execution in the virtual address mode. An instruction decoder 103 decodes an instruction to be executed. 104 is an instruction execution unit that realizes an instruction function to be executed. 105 is a system bus common to the systems. 106 is a data bus between the MPU 100 and the system bus 105. 107 is an address bus from the MPU 100 to the system bus 105. Reference numeral 108 is a control signal line for controlling exclusive access to the system bus 105, that is, indivisible access to the memory. 109
Is another MPU in a multiprocessor configuration. The structure of this MPU is exactly the same as the MPU100. There are multiple, but the representative is 109. 110 is a signal line for exclusive control between the MPU 109 and the system bus, and performs the same function as the exclusive control signal 108 for the MPU 109. 111 is a main memory device that holds data common to the system.

In this figure, the MPU 100 has instructions in the main memory 111 for the system bus 105, the data bus 106, and the address bus 10.
7. Fetch via the bus interface unit 101 or the like. The instruction decoder unit 103 decodes the fetched instruction,
The processing of the actual command function is delegated to the execution unit 104. if,
When the instruction requires exclusive atomic access to system resources, exclusive control is performed so that other MPUs 109 do not interrupt or preempt access to data for common resource control in main memory 111. Exclusive control is realized using the signal line 108. At this time, if the MPU 100 is executing in the virtual address mode, the virtual memory is translated into the real address using the address translation unit 102 so that the main memory 111 is accessed by the real address. In order to perform address translation at high speed, this part is usually realized by a high-speed translation buffer mechanism (abbreviated as TLB).

FIG. 2 shows how a virtual address is converted to a real address in this embodiment. In FIG. 2, 200 is a virtual address. 201 is a virtual address 200
Of these, the information specifies an entry (segment table entry; abbreviated as STE) 206 in the segment table. Information 202 designates an entry (page table entry; abbreviated as PTE) 208 in the page table of the virtual address 200. 203 is information designating an in-page offset of the data 211 to be accessed. 2
04 is a register that points to the root of the address translation table. It is called a table route register (abbreviated as TRR). In this case, the base address of the segment table 205 is held. 205 is a segment table. It is the first stage of the address translation table. The TRR register 204 holds its base address. 206 is the STE specified by 201. 207 is a page table. This is the second stage of the address conversion table. STE206 specifies its base address. 208 is a PTE designated by 202. 209 is a main memory. 210 is a page frame in the main memory, and the PTE 208 specifies its base address.
211 is the data to be accessed. Position on page 2
03 specifies.

As shown in FIG. 2, address conversion from a virtual address to a real address is performed by referring to a two-stage table. The first row is called the segment table and the second row is the page
Call it a table. Each table consists of table entries. An entry in the segment table is called a segment table entry (STE), and an entry in the page table is called a page table entry (PTE).

In the conventional method, exclusive access to the address conversion table in the case of the multiprocessor configuration is processed in a two-step process. As an example, consider the case of exclusive RMW access to PTE. In the first stage, in order to find the PTE, the same means as the procedure for address conversion is followed by software according to FIG. 2 to specify the PTE. The next stage is PTE
Rewrite with locks using atomic operations to update its contents.

However, in this method, not only the performance is lowered because the translation procedure is followed by software, but the contents of the address translation table (segment table entry) in the first stage are rewritten by another processor at the same time. If the correct PT when following the conversion procedure by software
E may be inaccessible. Therefore, exclusive access to the PTE must be done after first locking the STE and securing the right to access the entire page table.

In this embodiment, exclusive access to the PTE is realized according to the following steps. First, as the instruction function, an instruction called TASPIV va, mask is prepared. TASPIV is Test and set PT
This is an abbreviation for E interlocked with Virtual address access, and this instruction has the functions of exclusive access to the PTE and rewriting. There are two operands. The first operand is an operand that specifies a virtual address for identifying the PTE, and the PTE that is referenced when converting the virtual address specified by va is the target that is actually locked. The second operand is the operand that specifies the mask pattern and is PT
Specify the bit to be rewritten in E. For example if P
If TE is 32 bits long, the mask is also 32 bits long.

The process by which this instruction is executed is as follows. FIG. 3 shows the instruction execution flow.

(1) An exclusive access right to the main memory 111 is obtained by the exclusive control line 108 for exclusive access.

(2) The operand data specified by the first operand va is regarded as the virtual address 200, and the address conversion process shown in FIG. 2 is followed, TRR204, segment table 20.
6. Access the page table and identify the PTE 208.

(3) Read out the contents of the specified PTE208, remove the mask, and rewrite. Instruction function is TMP ← PTE; PTE fetch comparison ← (OXFFFFFFFF and (not mask)) − (TMP
and (not mask)); PTE ← TMP and (not mask)); PTE that is compared with the pattern of all 1s with a mask is updated. Here, PTE is the page table entry 208 itself, and mask is the data of the mask pattern specified by the second operand.

(4) Since exclusive access ends after writing the result to the PTE208 location, the exclusive control line 108 causes the main memory 1
End exclusive access to 11.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings.

In the first embodiment, the two-stage conversion table is accessed to access the PT
When E is updated by atomic operation, access to the segment table is locked and prohibited until all PTEs are processed, so multiple MPUs update multiple PTEs in the same page table at the same time. Even if it tries, there is a problem that only one PTE can be updated at a time. That is, access to the entire two-stage conversion table is inseparable. In the meantime, even if another MPU tries to steal (briemption), it cannot be done.

What will be described below as a second embodiment is a method of permitting pre-emption during two-stage access.

FIG. 4 is a block diagram of the system configuration in the second embodiment of the present invention. In FIG. 4, 400 indicates one MPU. 401 is a bus interface unit that controls communication with the system bus. Reference numeral 402 is an address translation unit that translates a virtual address into a real address during execution in the virtual address mode. An instruction decoder 403 decodes an instruction to be executed. An instruction execution unit 404 performs an instruction function to be executed. 405 is a system bus common to the systems. 406 is a data bus between the MPU 400 and the system bus 405. 407 is an address bus from the MPU 400 to the system bus 405. Reference numeral 408 is a control signal line for controlling exclusive access to the system bus 405, that is, indivisible access to the memory. 40
9 is another MPU in a multiprocessor configuration. The structure of this MPU is exactly the same as the MPU400. There are multiple, but the representative is 409. Reference numeral 410 is a signal line for exclusive control between the MPU 409 and the system bus, and performs the same function as the exclusive control signal 408 for the MPU 409. Reference numeral 411 is a main memory device that holds data common to the system.

FIG. 5 shows how a virtual address is converted to a real address in this embodiment. In FIG. 5, 500 is a virtual address. 501 is a virtual address 500
Of these, the information specifies an entry (segment table entry; abbreviated as STE) 506 in the segment table. 502 is information that specifies an entry (page table entry; abbreviated as PTE) 508 in the page table of the virtual address 500. Reference numeral 503 is information designating an in-page offset of the data 511 to be accessed. Five
04 is a register that points to the root of the address translation table. It is called a table route register (abbreviated as TRR). In this case, the base address of the segment table 505 is held. 505 is a segment table. It is the first stage of the address translation table. The TRR register 504 holds its base address. 506 is an STE designated by 501. 507 is a page table. This is the second stage of the address conversion table. STE506 specifies its base address. 508 is a PTE designated by 502. 509 is the main memory. 510 is a page frame in the main memory, and the PTE 508 specifies its base address.
Reference numeral 511 is data to be accessed. Position on page 5
03 specifies. In the second embodiment, follow the steps below:
Achieve exclusive access to the PTE. First, the instruction function TASPIV2 va, mask is prepared. TASPIV2 is Test and Set P
TE interlocked with Virtual address access, pa
This command is an abbreviation for rt2, and this instruction has the functions of exclusive access to the PTE and rewriting. The function of the operand is the same as in the first embodiment.

The difference between the second embodiment and the first embodiment is that the conversion table
When accessing, preemption is allowed on the way without making the access indivisible. However, in order to prevent a logical inconsistency, the segment table entry is provided with a usage counter, and it is noted whether it is in use, and if so, how many processes are using it. The counter is 0 when not in use. To update the STE, use the PTE
Since the access to the STE must be prohibited, the STE in use status is indicated by a value of -1 in the usage counter.
In the case of updating the PTE, if the usage counter of the STE is -1, access is not possible and the processing ends abnormally.

The execution flow of this instruction is shown in FIG.

[Advantages of the Invention] By adopting the above method, (1) exclusive read-modify-write RMW) access to a page table entry (PTE) can be performed with one instruction (2) exclusive access time The effect is that the can be shortened.

That is, in the conventional MPU, there is only an indivisible RMW instruction for the data in the memory that must be serialized and accessed, and the entry in the address translation table is accessed by the virtual address, and It did not provide the function of performing RMW. However, the present invention enables exclusive read-modify-write to the page entry table with one instruction.

[Brief description of drawings]

FIG. 1 is a block diagram showing the system configuration of a multiprocessor configuration and the configuration of each central processing unit in the first embodiment of the present invention, and FIG. 2 is the correspondence between virtual addresses and real addresses in the first embodiment of the present invention. FIG. 3 is a block diagram showing the first embodiment of the present invention, and FIG. 4 is a flow chart showing the procedure of processing an instruction for inseparably updating the conversion table in the first embodiment of the present invention.
FIG. 5 is a block diagram showing the system configuration of a multiprocessor configuration and the configuration of each central processing unit in the second embodiment of the present invention, and FIG. 5 shows the correspondence between virtual addresses and real addresses in the second embodiment of the present invention. A block diagram and FIG. 6 are flowcharts showing a procedure of processing of an instruction for inseparably updating the conversion table in the second embodiment of the present invention. 100,400 ... Microprocessor, 101,401 ... Bus interface section, 102,402 ... Address conversion section, 103,403 ... Instruction decoder section, 104,404 ... Execution section, 105,405 ... System bus, 106,406 ... Data bus, 107,407 ... Address bus , 108,408 …… Exclusive control line, 109,409 …… Microprocessor, 110,410 …… Exclusive control line, 111,411 …… Memory.

Claims (2)

[Claims] 1. An address translation mechanism that implements a virtual memory system, an instruction implementation unit that can execute an atomic update instruction that controls access to a memory, and an address translation unit that enables translation from a virtual address to a real address. In an information processing apparatus including a plurality of central processing units, each of which has a control line that enables each central processing unit to have exclusive access to a memory, and the address conversion unit of each central processing unit converts a virtual address to a real address. It has a second address conversion table corresponding to the first address conversion table in the memory that is referred to when the address is converted into an address, and the first address conversion table is in the conversion table that holds the relationship between the virtual address and the real address. The instruction execution unit of one central processing unit has an entry When the divisible update instruction is executed, the control line is activated to perform exclusive access to the memory, update the entry in the translation table of the second address translation table corresponding to the entry in the translation table of the memory, and An information processing device characterized by also updating an entry in a conversion table of a memory. 2. The information processing apparatus according to claim 1, wherein an entry in the conversion table of the memory is addressed based on a virtual address designated by an operand of the atomic update instruction.