JPH0773188B2 - Digital filter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used in an oversampling type analog-digital converter.

2. Description of the Related Art Conventionally, as a digital filter for obtaining a PCM signal from a delta-modulated signal, a storage device that uses a data string extracted from a predetermined tap as an address so that a low-pass filter characteristic for preventing aliasing can be obtained (example If RO
M, hereinafter referred to as ROM), predetermined data is stored, sampled at a desired sampling frequency and output is taken out. FIG. 2 shows a block diagram of a conventional example, which will be described below with reference to the drawing.

In FIG. 2, 11 is an input terminal of a delta modulation signal, 12 is an output terminal of a processed PCM signal, 13 is a shift register, 1
4 is a ROM and 15 is a sampling device. The delta modulation signal input from the input terminal 11 is set to 1 by the shift register 13.
Updated every clock. The data string extracted from the predetermined tap of the shift register 13 is used as the address data of the ROM 14, and the signal data corresponding to the address data is
It is output from ROM13. The ROM 13 stores data such that the digital filter as a whole has the characteristics of a low-pass filter.

Problems to be Solved by the Invention However, in the conventional digital filter, the number of taps required to obtain sufficient cutoff characteristics for preventing aliasing, that is, the ROM address length, increases, and the ROM capacity increases. Had.

The present invention has been made in view of the above problems, and performs processing in units of one tap or several taps, and repeats the processing for the number of times of the ratio of the sampling frequency of the delta modulation signal to the sampling frequency of the final data. Is provided to obtain output data, thereby providing an excellent digital filter capable of reducing the ROM capacity.

Means for Solving the Problems To achieve this object, a digital filter according to the present invention comprises a shift register for inputting a delta-modulated data sequence, a control device for transmitting an operation timing signal of the device, and the control device. Corresponding to a multiplexer for extracting delta modulation data one by one from a plurality of taps taken out from a predetermined position of the shift register according to a timing signal sent from the device, and a tap position of the shift register sent from the control device. A storage device which outputs predetermined filter coefficient data according to the address signal, and a predetermined process for the output data of the multiplexer,
For example, when the output data is "1", the output data of the storage device is output, and when the output data is "0", the output data of the storage device is multiplied by -1 to output the data. And an integrator with reset for accumulating output data of the data processing device, and a sampling device for resampling the output data of the integrator at a sampling frequency slower than the sampling frequency of delta modulation. It is a digital filter characterized in that an output signal is taken out.

Action The present invention can reduce the ROM capacity and the circuit scale by the above-mentioned configuration.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a digital filter according to an embodiment of the present invention.

In FIG. 1, 1 is an input terminal for a delta modulation signal, 2 is an output terminal for a processed PCM signal, 3 is a shift register,
Reference numeral 4 is a multiplexer, 5 is a control device for controlling the digital filter, 6 is a storage device (hereinafter referred to as ROM), 7 is a data processing device for performing a predetermined process on the output signal of the ROM 6 according to the output signal of the multiplexer 4, and 8 is An integrator with reset, 9 is a sampling device.

The delta modulation signal input from the input terminal 1 is updated by the shift register 3 for each sample of the delta modulation signal. Among the taps taken out from the shift register 3, the multiplexer 4 sequentially selects from the output taps of the register in which the oldest data is stored, and inputs them to the control input terminal of the data processing device 7.

On the other hand, the address signal corresponding to the data output tap position of the shift register 3 selected by the multiplexer 4 is output by the control device 5, and the coefficient data of the digital filter stored in the address location is output from the ROM 6. The coefficient data is input to the data input terminal of the data processing device 7. For example, when the data processing device 7 processes one tap at a time, the logic of the delta modulation signal is "1".
In the case of, the output data of the ROM 6 is output as it is, and in the case of "0", it is multiplied by -1 and output. If the coefficients are symmetrical, select two taps in order from both ends. When it is "11", the output of ROM6 is unchanged, when it is "01" or "10", the numerical value is 0, and when it is "00" Outputs the data obtained by multiplying the output of ROM6 by -1.

The data thus obtained is sequentially accumulated by the integrator 8 with reset, re-sampling is performed every time the final data is sampled, and the output is taken out. The shift register 3
Is updated every sampling cycle of the delta modulation signal, so taps to be taken out must be shifted according to the order.

Advantageous Effects of Invention The present invention provides a multiplexer that inputs a delta-modulated data string to a shift register, and selects taps taken out from a predetermined position of the shift register one by one according to a timing signal sent from a control device, and a control unit. A storage device that outputs predetermined data in response to an address signal sent from the device; and a data processing device that performs predetermined processing on the output of the storage device according to the data from the multiplexer,
It has an integrator with reset that accumulates the output data of the data processing device and a sampling device that samples the output data of the integrator at a sampling frequency slower than the sampling frequency of delta modulation, and is configured to extract the output signal from the sampling device. By doing so, the ROM capacity can be reduced and the circuit scale can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a digital filter in an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional digital filter. 1 ... input terminal, 2 ... output terminal, 3 ... shift register, 4 ... multiplexer, 5 ... control device, 6 ... RO
M, 7 ... Data processing device, 8 ... Integrator with reset, 9 ... Sampling device.

Claims (1)

[Claims] 1. A shift register for inputting a delta-modulated data sequence, a control device for transmitting an operation timing signal of the device, and a predetermined position of the shift register according to a timing signal transmitted from the control device. A multiplexer for extracting delta modulation data one by one from a plurality of taps; a storage device for outputting predetermined filter coefficient data by an address signal sent from the control device, the address signal corresponding to the extraction tap position of the shift register; , A data processing device that performs a predetermined process on the output data of the device, an integrator with a reset that accumulates the output data of the data processing device, and the output data of the integrator is resampled at a sampling frequency slower than the sampling frequency of delta modulation. A sampling device Digital filter, characterized in that with Bei, they were taken out of the output signal from said sampling device.