JPH0772237A - Radar equipment - Google Patents

Abstract

PURPOSE:To enhance the distance-measuring capability of radar equipment by discriminating a weak reflected signal from an external noise. CONSTITUTION:A pulse-shaped signal is output periodically from a pulse-signal sending means 5a. Then reflected pulses from an object target are received continuously by a reflected-pulse-signal reception means 5b, and they are binary-copied by a binary- coding means. Then, a sampling means 6A samples binary-coded signals at a definite one sampling point or a plurality of sampling points after the sensing timing of the sending means 5a, sampled value at 0 or 1 are obtained, and the values are given to an addition and storage means 6B which corresponds to the individual sampling points. Then, the addition and storage means 6B adds the sampled values at 0 or 1 by every portion of the prescribed number of sensing operations of the signal by the sending means 5a. When the addition and processing operation of the portion of the prescribed number has been finished, a judgment means 7 divides the added values at the addition and storage means 6B by the number of addition operations, it compares the obtained normalized added values with a prescribed threshold value, is judges, on the basis of the comparison result, the existence of a reflected signal from an object target at the outside, and it judges, on the basis of its judgment, whether the object target at the outside exists or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention aims to determine the presence or absence of a target with a very inexpensive and simple structure by binarizing a received wave and increasing the sensitivity by addition statistical processing or integral statistical processing, And a radar device capable of detecting a weak reflected signal, and secondly, an output signal from a similar radar device mounted in an oncoming vehicle. Thirdly, the present invention relates to a radar device that detects and removes the interference wave. Also, thirdly, by obtaining the distance from the distance corresponding to the sampling interval to the target, accurate target determination and measurement can be performed even if the pulse transmission timing cycle is wide. The present invention relates to a radar device capable of distance, and fourth, to a vehicle radar device capable of increasing speed, improving durability and reliability.

[0002]

2. Description of the Related Art A conventional vehicle radar device is shown in FIG.
The device shown in FIG. 9 is known. This device calculates the inter-vehicle distance based on the measurement result of the time from when a pulse signal such as a radio wave or a laser beam is transmitted in front of the own vehicle until the pulse signal reflected from the preceding vehicle is received. Is.

The pulse signal sending means 1 sends a pulse signal such as a radio wave or a laser beam to the vehicle ahead, and the reflected pulse signal receiving means 2 receives the pulse signal reflected from the vehicle ahead. Convert to electrical signal. Further, the control unit 3 controls the pulse signal transmission timing, and the time measuring unit 4 counts and measures the time from the pulse transmission timing to the reception of the reflected pulse based on the command of the control unit 3.

FIG. 90 is a timing chart of various signals, and the trigger signal (1) is a signal which is repeatedly output at a constant cycle for each predetermined interval Tr. The sending pulse signal (2) is a signal output from the pulse signal sending means 1 controlled by the control means 3, and is output in synchronization with the trigger signal (1). The received pulse signal (3) is a signal received by the reflected pulse signal receiving means 2 by being reflected from an external target. When the amplitude of the received pulse signal (3) exceeds a predetermined threshold value Vth, the reflected pulse signal (3) is received. The detection signal is output by the signal receiving means 2. Meanwhile, clock pulse (4)
Is a signal for counting the time from when the pulse signal (2) is sent out to when the detection signal is output by the time measuring means 4, and is output at intervals Δt for a certain period.

[0005]

However, such a conventional radar apparatus has the following problems. That is, the received signal of the reflected pulse usually contains internal noise and external noise, and the threshold value for detecting the reflected pulse is set to a relatively high value so as to prevent erroneous detection due to the influence of such noise. There is a need to. Generally, noise can be regarded as random noise that follows a Gaussian distribution, and assuming that the instantaneous amplitude of noise is n, its probability distribution P (n) has a mean value of zero and a Gaussian distribution of variance σ ² as shown in FIG. It is a probability density constant to be exhibited. Where σ is the standard deviation. The probability density function P (n) at this time is represented by Formula (1).

[0006]

[Equation 1] In the above equation (1), σ ² corresponds to noise power, and σ corresponds to its effective value. The probability density function P (ns) when the above noise is added to the signal of the amplitude s is given by the mathematical expression (2).
It is represented by.

[0007]

[Equation 2] Therefore, now, the reflected pulse from the desired distance is 99,
In order to detect correctly with a probability of 85%, the threshold value is set to 3σ as shown in FIG. 40, and the signal amplitude is 3σ higher than the threshold value, that is, 6 times the effective value σ of noise (SN
The pulse signal output to be sent may be set so as to obtain a peak signal having a high ratio of 15, 6 dB. However, in the case of radar, it is known that the level of the received signal is attenuated in proportion to the fourth power of the distance according to the so-called radar equation, and in order to increase the distance (detection) distance, a large output and extremely high cost are required. A highly specialized oscillator or light emitting device is required. Also, in order to increase the reception intensity instead of increasing the output, it is necessary to increase the aperture area or the light receiving area of the antenna, which increases both the shape and weight of the radar head. If this is attempted, there is a problem that the vehicle mountability is extremely poor. Further, from the viewpoint of ensuring safety when irradiated to the human body, the output is limited to the safety standard or less, so it is difficult to obtain a desired detection capability.

On the other hand, as a means for greatly improving the receiving sensitivity for detecting a weak signal, Japanese Patent Publication No. 1-46034,
A method as shown in Japanese Examined Patent Publication No. 2-2106 has been proposed. This is to convert a received signal having a constant repetition period such as the Loran C signal into a binarized signal indicating whether the signal is positive or negative, sample the signal, and repeat it in a RAM memory for a certain time by a microcomputer. After the addition and storage are performed, the presence or absence of a signal, the SN ratio and its time position are detected from the memory contents. The detectable SN ratio can be significantly improved by addition, and the detection of a weak received signal can be performed. It will be possible.

However, the configuration of this conventional example is suitable when the Loran C signal has a relatively long repetition period and the time required for signal detection may be relatively long.
There are the following problems when applied to the reception of radar signals.

That is, since the reception intensity of the radar signal is attenuated in proportion to the fourth power of the distance as described above, it is necessary to improve the sensitivity 16 times in order to double the detection distance. However, since the amount of sensitivity improvement by calculation is proportional to the 1/2 power of the number of additions, it is necessary to increase the number of additions to 16 ² = 256 times in order to improve the sensitivity 16 times. The transmission pulse transmission repetition cycle must be made as short as possible, but in the conventional method, since the RAM memory is controlled by the microcomputer for addition and storage, the time required for sampling and addition is determined by the clock time and instruction cycle of the microcomputer. As a result, the transmission repetition cycle of the transmission pulse is limited, and there is a limit to the improvement in high sensitivity by greatly increasing the number of additions.

Further, when the above-mentioned radar device is applied to a rear-end collision warning device of an automobile, the following problems occur.
That is, when an oncoming vehicle equipped with the same radar device sends out the signal to and from the oncoming vehicle, the pulse signal sent from the own vehicle and the pulse signal sent from the oncoming vehicle interfere with each other, and normal distance measurement can be performed. You may not be able to.

It is to be noted that not only the pulse signal of the oncoming vehicle but also the noise caused by the spark noise of the engine of the own vehicle and the noise caused by turning on / off the power of electric components such as headlights, air conditioners and wipers are not the only factors that impair normal distance measurement. Alternatively, noise may be caused by a change in power supply voltage, a change in sunshine, an environmental change such as entering a tunnel, or the like. That is, these noises of the host vehicle may resonate with noises from the outside, for example, to increase the detection level and exceed a preset threshold value, and may be mistaken as a reflection pulse of a target that does not actually exist.

On the other hand, the applicant of the present invention has filed Japanese Patent Application No. 3-171.
As shown in 380, when an alarm is issued according to the proximity situation to a vehicle ahead, not only the inter-vehicle distance but also the relative speed is required. There's a problem. That is, in general, the pulse radar can measure only the distance to the target, so it is necessary to increase the distance measurement accuracy and measure the time change rate in order to accurately obtain the relative velocity. If it is attempted to increase the pulse width, it is necessary to shorten the transmission pulse width and increase the sampling points. However, for example, 130 sampling points are required for each 1 m in order to obtain the distance measuring accuracy of 1 m in the range of 130 m, and the addition process takes a very long time. Also, the transmission pulse width is several ns
Since it is necessary to adjust the degree, the sending section becomes complicated and expensive, and there is a problem that the characteristics of the conventional example are impaired.

On the other hand, when the pulse signal transmitting means 1 is driven, the duty ratio of the pulse becomes low in order to secure the durability and reliability of the light emitting element, so that the repetition time of the transmitting pulse is limited. Naturally, shortening the repetition time of the sending pulse to speed up the distance measurement lowers the durability and reliability of the light emitting element, and conversely, increasing the repetition time of the sending pulse impairs the speedup of the distance measurement. Be done.

The present invention has been made in view of the above problems, and a first object thereof is to perform a series of processes of sampling, adding or integrating and storing a received signal with a low cost, a small size and a simple structure. The purpose is to increase the speed and detect the presence or absence of a target and the distance to the target at high speed even with a weak reflection pulse.

A second object is to speed up a series of processes of sampling, addition or integration, and storage of a received signal with a low cost, small size, and simple structure, thereby increasing the number of additions or integrations, presence or absence of a target, and It is to improve the sensitivity and accuracy of the detection of the distance to the target.

A third object is to increase the detection distance (distance-measuring distance) of the target while ensuring safety to the human body with low cost, small size, simple structure, and low level signal.

A fourth object is to reduce (reduce) the interference with the output pulse of the oncoming vehicle with a low cost, small size, and simple structure, and improve the safety and reliability of the target detection (ranging). That is.

[0019]

In the radar apparatus of the first aspect of the invention, the transmitting means periodically outputs a pulsed signal to the outside. The receiving means continuously receives the signal from the direction in which the transmitted signal is reflected on the target, and the instantaneous value of the signal received by the receiving means exceeds or does not exceed a certain signal level by the binarizing means. Binarize depending on Then, the sampling means samples the binarized signal at each sampling point at which one or a plurality of fixed times after the sending timing of the sending means are different to obtain a sampling value of 0 or 1, and this is sampled at each sampling point. To the adding means corresponding to. Therefore, the adding means adds the sampled value of 0 or 1 for each predetermined number of times of sending of the signal by the sending means.

When the addition processing for the predetermined number of times is completed, the determination means compares the normalized addition value obtained by normalizing the addition value of each addition means with a predetermined threshold value, and based on the magnitude, reflection from an external target object is performed. It is determined whether or not there is a signal, and based on this, the presence or absence of an external target is determined.

Here, when there is no external target and the receiving means receives only noise, the probability that 0 appears as a binarized signal because the signal level of the noise signal appears evenly on both the positive and negative sides, Also, the probability that 1 appears is constant. Therefore, the normalized addition value (= a / m) obtained by adding only the noise at a certain sampling point a predetermined number of times and dividing the addition value a by the addition number m shows a substantially constant value 0.5. .

On the other hand, since the reflected signal in which the pulsed transmitted signal is reflected by the external target is biased in either positive or negative direction, the reflected signal is binarized and becomes 0 as a result. The probability and the probability of becoming 1 are not constant depending on the waveform of the received signal. Therefore, if the signal reflected from the target exists in the binarized signal at a certain sampling point, the normalized addition value for the addition value at that sampling point will be different from that for the background noise. Will be shown.

Therefore, the presence or absence of the target is accurately determined by setting a fixed threshold value in the determination means and determining that the target exists outside when a sampling point indicating a normalized addition value exceeding the threshold is found. To detect.

According to a second aspect of the present invention, in the radar apparatus according to the first aspect, the distance calculating means is further provided, and when the judging means judges that there is a reflection signal from an external target, the transmitting means is used. After transmitting the signal, calculate the distance that the signal propagates within the time to the sampling point corresponding to the adding means that shows the normalized addition value larger than the predetermined threshold, and automatically calculate the distance to the external target. .

The invention of claim 3 relates to claim 1 and claim 2.
Unlike the radar device of (1), one addition unit and one sampling unit are provided, but a feature is that a sampling timing switching unit is newly provided to switch sampling points.

That is, the sending means periodically outputs a pulsed signal to the outside. Whether the signal from the direction in which the transmitted signal is reflected by the target is continuously received by the receiving means and the instantaneous value of the signal received by the receiving means by the binarizing means exceeds or does not exceed a certain signal level. Binarize by. Then, the sampling means samples the binarized signal at each predetermined sampling point set by the sampling timing switching means after the sending timing of the sending means to obtain a sampling value of 0 or 1, and supplies this to the adding means. Therefore, the adding means adds the sampling value of 0 or 1 for the predetermined number of times of sending of the signal by the sending means, and stores the added value together with the sampling point information.

The sampling timing switching means switches to another sampling point when addition processing for a predetermined number of times is completed at one sampling point, and the sampling means also performs binary processing at this switched sampling point in the same manner. The converted signal is sampled to obtain a sampling value of 0 or 1, and the sampling value is given to the adding means. The adding means adds the sampling value of 0 or 1 for a predetermined number of times of sending of the signal by the sending means, and the added value Are stored together with the sampling point information.

In this way, when the sampling timing switching means completes the sampling and addition processing of the binarized signal with respect to all of the plural kinds of sampling points having different preset times, the judging means adds the sampling points. The normalized addition value obtained by normalizing the value is compared with a predetermined threshold value, and it is determined whether or not there is a reflection signal from an external target based on its magnitude, and based on this, the presence or absence of an external target. To judge. The principle of this determination means for determining the presence / absence of an external target is the same as that of the radar device according to claim 1.

When the judging means judges that the reflection signal from the external target exists, the distance calculating means, after the signal is sent by the sending means, up to the sampling point showing the normalized addition value larger than the predetermined threshold value. The distance that the signal propagates in time is calculated, and the distance to the external target is automatically calculated.

According to a fourth aspect of the present invention, in the radar apparatus according to any one of the first to fourth aspects, further, an interference wave detecting means for detecting an interference wave included in a reflected signal received by the receiving means, And interference wave removing means for removing the interference wave detected by the interference wave detecting means.

Therefore, a similar signal is transmitted from the radar device mounted on the vehicle of the other party, which is an external target, and the reception means of the vehicle receives the reflected pulse reflected by the vehicle of the other party. When the transmitted signal is received and interference is occurring, the interference wave detecting means detects the interference wave, the influence of the interference wave is removed by the interference wave removing means from the calculation result by the adding means, and then an external object The presence or absence of a target is determined and the distance to the target is calculated.

According to a fifth aspect of the invention, in the radar apparatus according to any one of the first to fourth aspects, further, a sampling value for noise received by the receiving means during each period when the transmitting means does not transmit a signal is sampled at each sampling point. It is characterized in that it comprises another one or a plurality of addition means for adding a predetermined number of times, and the determination means uses each normalized addition value obtained by normalizing each addition value of the other addition means as the threshold value for each sampling point. To do.

Therefore, even if the noise level is different at each sampling point, the influence can be reliably removed, the presence or absence of the target can be accurately determined, and the distance to the target can be accurately calculated.

According to a sixth aspect of the present invention, in the radar apparatus according to any of the second to fifth aspects, by further providing an approximating means and a peak detecting means, a normalization addition corresponding to a plurality of sampling points as a determination result by the determining means. When the value is larger than a predetermined threshold value, an approximation curve is obtained by connecting the plurality of normalized addition values by a predetermined approximation expression by the approximation means, and the peak detection means corresponds to the peak position of the approximation curve. The time delay from the signal transmission timing is obtained and given to the distance calculating means.

In this way, even if the interval between the sampling points is converted into a distance and is rough such as every 10 m, the target exists at the intermediate position between the adjacent sampling points from the detection of the peak position of the approximate curve. Even in such a case, the distance to the target can be calculated more accurately by calculating the distance to the target corresponding to the peak position.

According to a seventh aspect of the present invention, in the radar apparatus according to any of the first to sixth aspects, an upper limit for determining whether or not the normalized addition value of any of the sampling points exceeds a predetermined upper limit value. By providing the determining means, the lower limit determining means for determining whether or not the normalized addition value of any of the sampling points exceeds the predetermined lower limit value, and the sensitivity adjusting means, the upper limit determining means can determine whether any of the sampling points When it is determined that the normalized addition value of exceeds the upper limit value, the sensitivity adjusting unit adjusts the sensitivity of the device to be lowered, and conversely, the lower limit determining unit sets the lower limit value of the normalized addition value of any sampling point. When it is determined that the value does not exceed the limit, the sensitivity adjusting unit adjusts to increase the sensitivity of the device.

In this way, by always maintaining the level of the normalized addition value at an appropriate level, it is possible to accurately determine the presence or absence of the target and to stably calculate the distance to the target.

According to the radar apparatus of the present invention, as the sensitivity adjusting means, by using the output adjusting means for adjusting the output signal output of the sending means so that the normalized addition value falls within the upper and lower limit values, the upper limit determination is made. When the means determines that the normalized addition value of any of the sampling points exceeds the upper limit value, the output adjusting means makes an adjustment to reduce the output signal output of the transmitting means, and conversely, the lower limit determining means determines which sampling point. When it is determined that the normalized addition value of does not exceed the lower limit value, the output adjusting means adjusts the output signal output of the sending means to increase the sensitivity so that the normalized addition value falls within the upper and lower limit values. .

In this way, by always maintaining the level of the normalized addition value at an appropriate level, it is possible to accurately determine the presence or absence of the target and to stably calculate the distance to the target.

In the radar apparatus of the ninth aspect of the invention, as the sensitivity adjusting means, by using the gain adjusting means for adjusting the reception gain of the receiving means so that the normalized addition value falls within the upper and lower limit values, the upper limit determining means is obtained. When it is determined that the normalized addition value of any of the sampling points exceeds the upper limit value, adjustment is made to reduce the reception gain of the receiving means, and conversely, the lower limit determination means determines that the normalized addition value of any sampling point When it is determined that the lower limit value is not exceeded, the gain adjusting means adjusts the receiving gain of the receiving means so that the normalized addition value falls within the upper and lower limit values.

In this way, by always maintaining the level of the normalized addition value at an appropriate level, it is possible to accurately determine the presence or absence of the target and to stably calculate the distance to the target.

In the radar apparatus according to the tenth aspect of the present invention, as the sensitivity adjusting means, by using the addition number adjusting means for increasing / decreasing the addition number of the adding means, the addition number of the necessary minimum number is always kept at a sufficient SN ratio. It is automatically set so that the reflected signal can be detected, so that the presence or absence of the target or the distance measuring operation can be performed in a short time.

According to the radar apparatus of the eleventh aspect of the present invention, the transmitting means periodically outputs the pulsed signal to the outside.
Whether the signal from the direction in which the transmitted signal is reflected by the target is continuously received by the receiving means, and the instantaneous value of the signal received by the receiving means exceeds or does not exceed a certain signal level by the binarizing means. Binarize by. Then, the sampling means samples the binarized signal for each sampling period in which a fixed one or a plurality of time zones after the sending timing of the sending means are different, and gives it to the integrating means. Therefore,
The integrating means integrates the binarized signal for each predetermined number of times the signal is sent by the sending means.

When the integration process for a predetermined number of times is completed, the determining means compares each of the integrated values for each integrating means with a predetermined threshold value and compares the normalized integrated value with an external target based on the magnitude. It is determined whether or not there is a reflection signal of, and the presence or absence of an external target is determined based on this.

Here, when there is no external target and the receiving means receives only noise, the probability that 0 appears as a binarized signal because the signal level of the noise signal appears evenly on both the positive and negative sides, Also, the probability that 1 appears is constant. Therefore, only the noise in a certain sampling period is integrated a predetermined number of times, and the normalized integrated value obtained by normalizing the integrated value shows a substantially constant value.

On the other hand, since the reflection signal in which the pulsed transmission signal is reflected to the external target is biased in either the positive or negative direction, it becomes 0 when the reflection signal is received and binarized. The probability or the probability of becoming 1 is not constant depending on the waveform of the received signal. Therefore, if there is a reflection signal reflected from the target in the signal during a certain sampling period, the normalized integral value obtained by normalizing the integral value during that sampling period will have a large value different from that for the above noise. Will be shown.

Therefore, the presence or absence of the target is accurately determined by setting a certain threshold value in the determining means and determining that the target exists outside when a sampling period showing a normalized integral value exceeding the threshold is found. To detect.

According to a twelfth aspect of the present invention, in the radar apparatus according to the eleventh aspect, the distance calculating means is further provided, and when the judging means judges that there is a reflection signal from an external target, the transmitting means is used. After transmitting the signal, calculate the distance that the signal propagates within the time until the sampling period corresponding to the integrating means that gives a normalized integral value larger than a predetermined threshold value, and automatically calculate the distance to the external target. .

In the thirteenth aspect of the invention, unlike the radar apparatus of the eleventh and twelfth aspects, the integrating means and the sampling means are of one type, but a sampling timing switching means is newly provided to switch the sampling period. It is characterized by

That is, the sending means periodically outputs a pulsed signal to the outside. Whether the signal from the direction in which the transmitted signal is reflected by the target is continuously received by the receiving means, and the instantaneous value of the signal received by the receiving means exceeds or does not exceed a certain signal level by the binarizing means. Binarize by. Then, the sampling means samples the binarized signal for each predetermined sampling period set by the sampling timing switching means after the sending timing of the sending means, and gives it to the integrating means. Therefore, the integrator integrates the binarized signal for each predetermined number of times of sending of the signal by the sending unit, and stores the integrated value together with the sampling period information.

The sampling timing switching means switches to another sampling period when the integration processing for a predetermined number of times is completed in a certain sampling period, and the sampling means also performs binary processing in this switching another sampling period. The binarized signal is sampled and given to the integrator, and the integrator integrates the binarized signal for each predetermined sampling number of times of the signal by the transmitter,
The integrated value is stored together with the sampling period information.

In this way, if the sampling timing switching means completes the sampling and integration processing of the binarized signal for all of the plurality of types of sampling periods in which the preset time zones are different, the judging means will determine each sampling period. Each integrated value is normalized and each normalized integrated value is compared with a predetermined threshold value, and it is determined whether or not there is a reflection signal from an external target based on its magnitude, and based on this, the external object is determined. Determine the presence or absence of the mark. The principle of this determination means for determining the presence or absence of an external target is the same as that of the radar device according to claim 11.

When the judging means judges that there is a reflection signal from the external target, the distance calculating means, after the signal is sent by the sending means, up to the sampling point showing the normalized integral value larger than the predetermined threshold value. The distance that the signal propagates in time is calculated, and the distance to the external target is automatically calculated.

According to a fourteenth aspect of the present invention, in the radar apparatus according to any one of the eleventh to thirteenth aspects, further, an interference wave detecting means for detecting an interference wave included in a reflected signal received by the receiving means, and an interference wave And interference wave removing means for removing the interference wave detected by the wave detecting means.

Therefore, a similar signal is transmitted from the radar device mounted on the vehicle of the other party, which is an external target, and then the receiving means of the own vehicle and the reflected pulse reflected by the vehicle of the other party. If the interference signal is received and the interference is generated, the interference wave detecting means detects the interference wave, the interference wave removing means removes the influence of the interference wave from the calculation result by the integrating means, and then the external wave The presence or absence of the target is determined and the distance to the target is calculated.

According to a fifteenth aspect of the present invention, in the radar apparatus according to any one of the eleventh to fourteenth aspects, the receiving means receives the signal as a threshold for each sampling period used by the determining means during a period in which the transmitting means does not transmit a signal. It is characterized in that each normalized integral value obtained by normalizing each integral value of the integrating means for integrating the binarized signal for noise a predetermined number of times in each sampling period is used.

Therefore, even if the noise level differs for each sampling period, the influence can be reliably removed to determine the presence or absence of the target, and the distance to the target can be calculated.

According to a sixteenth aspect of the present invention, in the radar apparatus according to any one of the twelfth to fifteenth aspects, by further providing an approximating means and a peak detecting means, a normalizing integration corresponding to a plurality of sampling periods as a result of the judging by the judging means. When the value is larger than a predetermined threshold value, an approximation curve is obtained by connecting the plurality of normalized integral values by a predetermined approximation expression by the approximation means, and the peak detection means corresponds to the peak position of the approximation curve. The time delay from the signal transmission timing is obtained and given to the distance calculating means.

In this way, even if the intervals of the sampling periods are converted into distances and are rough such as every 10 m, the target exists at the intermediate position between the adjacent sampling periods from the detection of the peak position of the approximate curve. Even in this case, by calculating the distance to the target corresponding to the peak position, the distance to the target can be determined more finely, for example, in steps of 1 m.

According to a seventeenth aspect of the present invention, in the radar apparatus according to any one of the eleventh to sixteenth aspects, an upper limit discriminating means for discriminating whether or not the normalized integral value of any of the sampling periods exceeds a predetermined upper limit value. By providing a lower limit discriminating means for discriminating whether or not the normalized integrated value of any sampling period exceeds a predetermined lower limit value, and a sensitivity adjusting means, the upper limit discriminating means is provided for normalizing the sampling period. When it is determined that the chemical integration value exceeds the upper limit value, the sensitivity adjusting means makes an adjustment to reduce the sensitivity of the device,
On the contrary, when the lower limit determination means determines that the normalized integrated value of any sampling period does not exceed the lower limit value, the sensitivity adjustment means performs adjustment to increase the sensitivity of the device.

In this way, by always maintaining the level of the normalized integral value at an appropriate level, it is possible to accurately determine the presence or absence of the target and to stably calculate the distance to the target.

In the radar apparatus of the eighteenth aspect of the present invention, as the sensitivity adjusting means, by using the output adjusting means for adjusting the output signal output of the sending means so that the normalized integral value falls within the upper and lower limit values, the upper limit determination is made. When the means determines that the normalized integral value of any sampling period exceeds the upper limit value, the output adjusting means makes an adjustment to lower the output signal output of the transmitting means, and conversely, the lower limit determining means determines which sampling period. When it is determined that the normalized integral value of does not exceed the lower limit value, the output adjusting means adjusts the output signal output of the sending means to increase the sensitivity so that the normalized integral value falls within the upper and lower limit values. .

Thus, by always maintaining the level of the normalized integral value at an appropriate level, it is possible to accurately determine the presence or absence of the target and to stably calculate the distance to the target.

In the radar apparatus of the nineteenth aspect of the present invention, as the sensitivity adjusting means, by using the gain adjusting means for adjusting the reception gain of the receiving means so that the normalized integral value falls within the upper and lower limit values, the upper limit determining means is obtained. When it is determined that the normalized integral value of any sampling period exceeds the upper limit value, adjustment is made to reduce the reception gain of the receiving means, and conversely, the lower limit determining means also determines the normalized integral value of any sampling period. When it is determined that the lower limit value is not exceeded, the gain adjusting means adjusts the receiving gain of the receiving means so that the normalized integral value falls within the upper and lower limit values.

In this way, by always maintaining the level of the normalized integral value at an appropriate level, it is possible to accurately determine the presence or absence of the target and to stably calculate the distance to the target.

In the radar apparatus according to the twentieth aspect of the present invention, the number of integration times adjusting means for increasing or decreasing the number of integration times of the integrating means is used as the sensitivity adjusting means. It is automatically set so that the reflected signal can be detected, so that the presence or absence of the target or the distance measuring operation can be performed in a short time.

[0067]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall configuration diagram showing the configuration of a common embodiment of the inventions of claims 1 and 2. The radar head 5 has a pulse signal transmitting means 5a for transmitting a pulse signal.
And reflected pulse signal receiving means 5b for receiving the reflected pulse.
It is configured with. The arithmetic storage means 6 is roughly classified into a sampling means 6A for sampling the signal received by the reflected pulse signal receiving means 5b and a storage means 6 for sequentially adding and storing the sampling results at each sampling point.
It is configured with B. The judging means 7 is mainly provided with a function of judging the presence or absence of a reflected pulse from the content of the data stored in the storage means 6B. The control means 8
The radar apparatus as a whole is provided with a function of controlling the drive of the pulse signal transmitting means 5a, a function of controlling the activation of the sampling means 6A and the storage means 6B of the arithmetic storage means 6, and a function of controlling the activation of the determination means 7. Has been done.

FIG. 2 is a block diagram showing a concrete structure of the first embodiment. First, the pulse signal sending means 5a
More specifically, a drive circuit 5a-1 that is driven according to a trigger signal output from a trigger generation circuit 8c described later, a light emitting element 5a-2 such as an LED or a laser diode that emits light in response to the drive of the drive circuit 5a-1, and light emission. Element 5a-2
It is composed of a lens 5a-3 which condenses the emitted light of (3) toward a target. Further, the reflected pulse signal receiving means 5b focuses the incident light from the outside, that is, the reflected light reflected from the target toward the inside (that is, the light receiving surface such as a photodiode) while focusing the lens 5b-1, Lens 5b-1
The light receiving element 5b-2 such as a photodiode that converts the light that passes through and is condensed into an electric signal is appropriately amplified while the electric signal output from the light receiving element 5b-2 and the light receiving element 5b-2 is corresponded to positive and negative. The limiter amplifier 5b-3 for converting the binarized signal (phase signal or code signal) ("1", "0") and the electric signal amplified by the limiter amplifier 5b-3 to a logic level (for example, 5V and 0V). It is composed of a zero-cross comparator 5b-4.

The arithmetic storage means 6 specifically takes in the clock signal output from the clock oscillator 8a and measures the timing of starting the sampling of the reflected pulse, and the sampling pulse output from the sampling pulse generating circuit 8d. Sampling addition circuit 6b for sampling, adding and storing the zero-cross signal output from the zero-cross comparator 5b-4 according to
It consists of

The determination circuit 7 takes in the addition data stored in the addition storage circuit 6b and the drive function of outputting a signal (start pulse) for driving the light emitting element 5a-2 to emit light a predetermined number of times, and adds the addition data to this addition data. It is provided with a determination function for determining whether or not a reflection pulse from the target is included. Details will be described later.

On the other hand, the control means 8 has a clock transmitter 8a.
A start pulse generation circuit (addition number setting circuit) 8b that takes in the clock signal output from the device, outputs a start pulse, and sets the number of additions to be repeated in one distance measuring operation,
The clock signal is fetched, the start pulse is received from the start pulse generation circuit 8b, the trigger generation timing is recognized, and the trigger signal is output to the drive circuit 5a-1 at regular intervals. While recognizing the timing, a sampling pulse generating circuit 8d is provided for recognizing the sampling start timing and the sampling termination timing according to a command from the start pulse generating circuit (addition number setting circuit) 8b and controlling the sampling operation of the arithmetic storage unit 6. Is configured.

FIG. 3 is a timing chart of various signals, and the trigger signal (1) is a pulse signal repeatedly output from the trigger generation circuit 8c at predetermined intervals, for example, every 4 μs. The transmission pulse signal (2) is generated by the trigger generation circuit 8c.
And a pulse signal output from the light emitting element 5a-2 controlled by the drive circuit 5a-1 toward an external target, and output in synchronization with the trigger signal (1). Received signal (3)
Is an instantaneous signal received by the limiter amplifier 5b-3 via the lens 5b-1 and the light receiving element 5b-2, and the zero-cross comparator 5b- determines whether the amplitude exceeds or does not exceed a predetermined threshold Vth (for example, 0V). 4 and the instantaneous value of the signal is output as a binarized signal. A reflected pulse appears in the reception signal (3) at a position delayed by a delay time Td proportional to the distance from the transmission timing to the target at each transmission timing of the transmission pulse signal (2) together with the noise signal.

The sampling pulse (4) is a sampling pulse output from the sampling pulse generating circuit 8c every time the trigger signal (1) is output, and its cycle is Δ.
The number t is n (for example, 14,128). Then, the binarized instantaneous value of the received signal (3) is sampled by the sampling addition circuit 6b at each timing of each sampling pulse and added at each sampling point, and a transmission pulse is received until an end pulse is received from the sampling pulse generation circuit 8c. The sampling and addition are repeated by the set number of times Na.

The above-mentioned sampling addition circuit 6b is provided with n memories M1 to Mn corresponding to the sampling pulses 1 to n (for example, n = 14).
If 1 is the value sampled at the first sampling point is "1", it is added to the stored value up to then, and the memory M2 is 1 if the value sampled at the second sampling point is 1 is added to the stored value of No. 1, and this process is continuously performed up to the memory Mn corresponding to the nth sampling pulse, and the above addition and storage processes are performed a predetermined number of times Na in response to a command from the addition number setting circuit 8b. Be seen.

The judging means 7 reads the added value of each memory when the addition and storage processing is completed a predetermined number of times, and whether the received signal (3) does not include the reflected pulse for the transmitted pulse (2). And the time delay from the sending pulse sending timing to the sampling point where the reflected pulse is detected is measured based on the sampling pulse period Δt. That is, the time Td = m · Δt (when the reflection pulse is detected at the m-th sampling point) until the reflection pulse is detected is calculated.

The principle of determining a target by this method and calculating the distance to the target is as follows. The signal received by the receiving means 5b includes random noise, but when the received pulse does not include reflected pulses but only random noise as background, the received signal is output by the high-gain limiter amplifier 5b-3 of FIG. If it is set to convert to a square wave and output "1" when the input is positive and output "0" when the input is positive by the zero-cross comparator 5b-4,
The probability that "1" appears and the probability that "0" appears are equal. Therefore, it is known that the probability distribution of the added value when such binary noise is repeatedly sampled and the binary data (“1” or “0”) is added exhibits a binomial distribution. That is, under the same conditions, Na is repeatedly used.
In an independent trial (corresponding to sampling Na times) performed once, the number of occurrences of a certain event (an event whose sampling value is “1”) is k (corresponding to the addition value being k), The probability distribution of k is the following (3), (4)
It can be expressed by a formula.

[0078]

[Equation 3]

[Equation 4] Here, p is the probability that "1" appears in one sampling, q is the probability that "0" also appears, and p = q = 0.5 in the case of only noise.

FIG. 4 shows the probability distribution of the added value k expressed by the equation (3) as p = q = 0.5, Na = 26, 32, 64, 12
The results calculated for each of 8 are shown. The horizontal axis uses the addition value k / Na normalized by Na. Normalized addition value k
The distribution range of is narrowed around 1/2 as the number of additions increases. The expected value k ′ of the added value and the variance V thereof when the noise having the above probability distribution is added to the signal are expressed by the following equations (5) and (6).

[0080]

[Equation 5]

[Equation 6] p and q are calculated by the equations (7) and (8) using the equation (2).

[0081]

[Equation 7]

[Equation 8] Since σ ² represents noise power, s / σ is equal to S / N. Therefore, p, q, k ', and V are uniquely determined by the SN ratio. Moreover, if k ′ is normalized with Na,
From equation (5), k '/ Na = p = 0.5, which is constant regardless of Na. Also, since the standard deviation V ^1/2 is given by (Na · p · q) ^1/2 from the equation (6), this is Na
When normalized with, (Na · p · q) ^1/2 / Na = (p ·
q / Na) ^1/2 with a standard deviation of 1 compared to when Na = 1
/ Na ^1/2 . This means that the larger the number of additions, the smaller the standard deviation due to noise, and the easier it is to separate the noise-only signal from the noise-superimposed signal.

Next, the details of the addition process will be specifically described. It should be noted that, for convenience of description, the specific configurations of various circuits forming the control means 8 will be described.

FIG. 5 is a block diagram showing the structure of the start pulse generating circuit (addition number setting circuit) 8b. The start pulse generating circuit (addition number setting circuit) 8b is composed of an RS flip-flop 8b-3, a divider 8b-4 and a counter 8b-6. First, the RS flip-flop 8b-3 receives the external start signal of the determination means 7 on the one hand, and the AND input of the external clear signal and the count end signal of the counter 8b-6 via the AND gate 8b-2 on the other hand. , The state of the output Q1b is switched depending on the relationship between the two. The divider 8b-4 has a control signal j obtained by inverting the output of the clock oscillator 8a, an external clear signal by the inverter 8b-1, and an output Q of the RS flip-flop 8b-3.
Receives 1b input and outputs Q2a according to the relationship of these signals
Is output. The output Q2a is inverted by the inverter 8b-5 and becomes a start pulse. The counter 8b-6 is
The input of the output Q2a of the divider 8b-4 is received, the addition count is executed, and the count continuation signal is sent to the inverter 8b-
Inverted by 7 and transferred to AND gate 8b-2,
An addition state signal is output according to the counting status.

That is, the number-of-addition setting circuit 8b sets the output Q1b of the RS flip-flop 8b-3 to "L" by the external start signal to release the inhibit of the clock input of the divider 8b-4 and outputs the 15 MHz clock signal to 3
The frequency is divided by 2 and a start pulse of 4 μs cycle is output. The number of start pulses is, for example, 8192. 819
Counter 8b-6 to which the second start pulse is input
Causes the output of the 14th bit to go to "H", resetting the RS flip-flop 8b-3 and stopping the operation of the divider 8b-4. The output of the counter 8b-6 becomes "L" when the start pulse is being output, becomes "H" after outputting 8192 pieces, and is transmitted to the judging means 7.

FIG. 6 is a block diagram showing the structure of the trigger generation circuit 8c. The trigger generation circuit 8c is composed of a plurality of JK flip-flops 8c-3 and 8c-5. The JK flip-flop 8c-3 receives the start pulse and the AND input of the output Q2b of the JK flip-flop 8c-5 through the AND gate 8c-1, and the JK flip-flop 8c through the AND gate 8c-2. -3 output Q1a and JK flip-flop 8c
Upon receiving the AND input of the output Q2a of -5, the states of the outputs Q1a and Q1b are switched according to the relationship between them. Then, the output Q1a becomes a drive pulse, and the output Q1b is taken out as a trigger pulse. JK flip-flop 8c-5
Through the gate 8c-4 to the JK flip-flop 8c
-3 output Q1a and the NOR input of the start pulse are received, and the states of the outputs Q2a and Q2b are appropriately switched according to the relationship between them.

FIG. 7 is a block diagram showing the structure of the sampling pulse generating circuit 8d. The sampling pulse generating circuit 8d is composed of an RS flip-flop 8d-2 and a 4-bit counter 8d-4. On the other hand, the RS flip-flop 8d-2 receives the input of the trigger pulse,
On the other hand, it receives an AND input of an external clear and an end pulse via the AND gate 8d-1, and switches the states of the outputs Q1a and Q1b according to the relationship between them. And output Q1
a is NANDed with the clock signal via the NAND gate 8d-3 and converted into a sampling pulse. On the other hand, the NAND output is a 4-bit counter 8
It is also output to d-4. The 4-bit counter 8d-4 is
Counts the sampling pulse and bit 2 at the 14th pulse
When the outputs QB, QC and Qd of 4 to 4 simultaneously become "H", the 3-input NAND gate 8d-5 becomes "L", the RS flip-flop 8d-2 is reset and the NAND gate 8d is reset.
-3 output is stopped. Also, 3-input NAND gate 8d
The output of -5 is output as an end pulse indicating the end of the sampling pulse.

FIG. 8 is a block diagram showing the configuration of the addition clock generation circuit 6a-a which is a component of the timing circuit 6a. Although the configuration of the addition clock generation circuit 6a-a is substantially the same as the configuration of the sampling pulse generation circuit 8c, the sampling pulse generation circuit 8c outputs the sampling pulse in response to the input of the trigger pulse, whereas the addition clock generation circuit 6a -A is different in that an added clock is output according to the input of the end pulse.

FIG. 9 is a block diagram showing a structure of a control pulse generating circuit 6a-b which is another component of the timing circuit 6a. The control pulse generation circuits 6a-b are two J
It comprises K flip-flops 6a-11, 6a-14, a plurality of NAND gates 6a-15, 6a-16, ... And an exclusive OR gate 6a-21. The JK flip-flop 6a-11 receives the input of the output Q2b of the JK flip-flop 6a-14 on the one hand, the input of the addition clock on the other hand, and outputs the output Q1a according to the relation between them.
Switch the state of Q1b. JK flip-flop 6a-
Reference numeral 14 denotes the NAND output of the input obtained by the NAND gate 6a-13, that is, the addition clock obtained by the NAND gate 6a-12 and the output Q2a of the JK flip-flop 6a-14 and the output Q1b of the JK flip-flop 6a-11. A NAND input switches the states of the outputs Q2a and Q2b.

The NAND gate 6a-15 receives the output Q1b of the JK flip-flop 6a-11, the addition clock, and J.
The control signal e (address counter) is controlled according to the output Q2b of the K flip-flop 6a-14. The NAND gate 6a-16 includes the output Q1b of the JK flip-flop 6a-11, the addition clock, and the JK flip-flop 6a.
The control signal f (addition counter) is controlled according to the output Q2b of -14. The NAND gate 6c-17 includes an output Q1a of the JK flip-flop 6a-11, an output Q2a of the JK flip-flop 6a-14, and an inverter 6a-1.
Control signal g according to the inverted signal of the addition clock via 8
(Count up) is controlled.

The exclusive OR gates 6a-21 are connected to the NAN.
The addition clock through the D gate 6a-19, the output Q1a of the JK flip-flop 6c-11, the AND-not input of the output Q2a of the JK flip-flop 6a-14, and the inverted signal of the addition clock through the NAND gate 6a-20, JK. Output Q1 of flip-flop 6a-11
The control signal h (memory input / output switching) is controlled according to the AND-NOT input of the output Q2b of the a, JK flip-flop 6a-14. The NAND gate 6a-22 controls the control signal i (memory write pulse) according to the output Q1a of the JK flip-flop 6a-11, the addition clock, and the output Q2a of the JK flip-flop 6a-14.

FIG. 10 is a timing chart of various signals of the control pulse generating circuit 6a-b. The output Q1a of the JK flip-flop 6a-11 is used as the output signal QA, and JK
The output Q2a of the flip-flop 6a-14 is output to the output signal Q.
Explain as B. The control signal e becomes "L" when the added clock is "H", the output signal QA is "L", and the output signal QB is "L". The control signal f becomes "L" when the added clock is "H", the output signal QA is "H", and the output signal QB is "L". The control signal g becomes "L" when the added clock is "L", the output signal QA is "L", and the output signal QB is "H". The control signal h becomes "L" when the output signal QA is "L" and the output signal QB is "H". As for the control signal i, the addition clock is “H”, the output signal Q
It becomes "L" when A is "L" and the output signal QB is "H".

FIG. 11 is a block diagram showing the structure of the sampling / adding circuit 6b. Sampling / adding circuit 6
b is an 8-bit shift register 6b-2, 6b-3, an address setting preset counter 6b-6, a memory 6b.
-8, 6b-9, multiple bidirectional buffers 6b-11-6
b-14 and a plurality of addition preset counters 6b-1
7 to 6b-20. The 8-bit shift registers 6b-2 and 6b-3 are connected in cascade, and the OR gate 6b-1 for the sampling pulse c and the control signal e ′ is used.
The output of the limiter amplifier 5b-3 is sampled in synchronization with the sampling pulse c according to the input to the, and the sampled data is stored while being shifted.

Address setting preset counter 6b-
Reference numeral 6 denotes an input of the control signal d and the control signal 8 of the judging means 7 to the OR gate 6b-4, and a control signal e and the judging means 7
The addresses of the memories 6b-8 and 6b-9 are set according to the input of the control signal 9 of 1 to the OR gate 6b-5. The memories 6b-8 and 6b-9 switch between the read mode and the write mode according to the input of the control signal i and the control signal 11 of the judging means 7 to the OR gate 6b-7. Bidirectional buffer 6
The initial states of b-11 to 6b-14 are the read mode (that is, the data of the memories 6b-8 and 6b-9 are output), and the data loading direction is determined according to the control signal h and the control signal 10 of the determination means 7. To switch. That is, in the read mode, the stored contents of the memories 6b-8 and 6b-9 are loaded into the addition preset counters 6b-17 to 6b-20, and in the write mode the addition preset counters 6b-17 to 6b-17.
The stored contents of 6b-20 are loaded into memories 6b-8 and 6b-9. Preset counter for addition 6b-17 to 6b
-20 is in accordance with the output of the 8-bit shift register 6b-3 and the control signal g that is inverted and output via the inverter 6b-15, is input to the AND gate 6b-16, and further is controlled by the control signal f and the control signal d '. Increment the loaded content.

FIG. 12 is a timing chart showing the addition processing operation. When the end pulse d indicating the end of the output of the sampling pulse c is output from the sampling pulse generation circuit 8d, the address setting preset counter 6b
Each bit of −6 is preset to “H”, the addition preset counters 6b-17 to 6b-20 are cleared, and further, in synchronization with the end pulse d, the addition clock generation circuit 6c-a outputs, for example, 42 clocks. The added clock is output.

Control signal e of control pulse generation circuit 6c-b
By this, the address setting preset counter 6b-6 is incremented, and the memories 6b-8 and 6b-9 which are in the read mode in advance on the address bus 6b-66.
$ 00 for selecting the zero address of is output, and the memory output D
The memory contents at address 0 are output from 0 to D7. At the same time, the control signal e is the 8-bit shift register 6b-2,
Since it is also input to the clock terminal of the addition preset counter 6b-17, the 8-bit shift register 6b-
The storage content of 2 is shifted by 1 bit and AND gate 6b
It is output to -16.

Next, by outputting the control signal f, the memory 6b-
The contents of 8, 6b-9 are preset counters for addition 6b-
17-6b-20. Control signal j is "H"
Then, the control signal g is the addition preset counter 6b-1.
7 to 6b-20 are incremented, and if the control signal j is "L", the addition of the control signal g is not output to the other input of the AND gate 6b-16 for inputting the addition preset counter 6b-17, so that the addition is not executed. .

The control signal h is the bidirectional buffer 6b-11.
6b-14 are switched to the input / output direction and the contents of the addition preset counters 6b-17 to 6b-20 are stored in the memory 6b-.
8,6b-9. Control signal i is OR gate 6b
When it is input to -7, the memories 6b-8 and 6b-9 are set to the write mode, and the contents of address 0 are rewritten to the contents of the addition preset counters 6b-17 to 6b-20.

As described above, since the reading, addition and writing of the contents of the memory address corresponding to one bit of the 8-bit shift registers 6b-2 and 6b-3 are completed in 3 cycles of the addition clock, it takes 14 cycles in 42 cycles. The addition processing for one bit is completed, and such processing is performed 8192 times to obtain the addition value.

On the other hand, the judging means 7 outputs 81 by the output (13) of the start pulse generating circuit (addition number setting circuit) 8b.
The end of 92 additions is detected, and the memories 6b-8 and 6b-9 of the sampling / adding circuit 6b and the bidirectional buffer 6 are detected.
b-11 to 6b-14 by controlling the memories 6b-8 and 6b
The added value stored in -9 is read, the presence or absence of the reflected pulse is detected, and the distance is obtained.

FIG. 13 is a flow chart showing the operation of the judging means 7. First, in step 131, the output of the determination means 7 is initialized, and the operation storage means 6 is accordingly initialized.
Is initialized and the OR gates 6b-4, 6b-5, 6b-7, 6b-10 of FIG. 11 are initialized.
Each control signal 8, 9, 10, 11 to be input to is initialized. Then, in step 132, the determination means 7 causes the start pulse generation circuit (addition number setting circuit).
8b divider 8b-4, sampling / adding circuit 6b
The address setting preset counter 6b-6 and the addition preset counters 6b-17 to 6b-20 are cleared. Further, in step 133, the internal counter of the control means 7 is cleared.

Thereafter, the addition memory clear routine is entered, and at step 134, the control signals 9, 10, 11 are entered.
To output OR gates 6b-5, 6b-7, 6b.
The output signal is output from -10. Then, step 1
At 35, increment the address counter,
In step 136, the increment value is $ 10
To determine whether or not. As a result, the increments of the 8-bit preset counters 6b-2 and 6b-3 and the input / output directions of the bidirectional buffers 6b-11 to 6b-14 are switched to the memories 6b-8 and 6b-9, and the memories 6b-
8, 6b-9, the addition preset counter 6b-17
Write the cleared output of ~ 6b-20 (eg, $ 00). This operation is performed by the 8-bit shift register 6b-2,
Similarly, while incrementing 6b-3, the contents of addresses $ 00 to $ 10 of the memory are cleared.

Thus, if it is determined in step 136 that the increment value has not reached $ 10, the process returns to step 134, but if it is determined that the increment value has reached $ 10, Step 137
Then, the external start pulse is transferred to the start pulse generating circuit 8b, and the series of addition processing described above is performed.

Thereafter, in step 138, it is determined whether or not the addition state signal of the start pulse generating circuit (addition number setting circuit) 8b is "H". If the addition state signal is not "H", the process of step 138 is repeated again, but if the addition state signal is "H", it is considered that the addition process is completed, and the process proceeds to step 139, and the address setting preset counter 6b-6 is cleared. To do. And step 14
At 0, the internal counter of the judging means 7 is cleared.

After that, of the addition data in the addition memory,
The so-called addition memory read mode for reading the upper 8 bits is set, and in step 141, the OR gate 6
The control signal 9 is output to b-5 to increment the address setting preset counter 6b-6. continue,
In step 142, the address counter is incremented, and in step 143, the memories 6b-8,
It is determined whether or not the contents read in 6b-9 are $ 10. If it is determined in step 143 that the increment value has not reached $ 10, the process returns to step 141. However, if it is determined that the increment value has reached $ 10, the process proceeds to step 144. Calculate the distance from the content of the added value to the target, and calculate the calculated distance by CRT.
Etc. (including alarm).

FIG. 14 shows the probability distribution of the added value k when Na = 128, S / N = + 3, -6, -15, -∞ (-
∞ is the case of only noise), and the data addition of Na = 128 times is repeated 2000 times by carrying out for each SN ratio, and the frequency distribution (probability distribution) of the added value is obtained and plotted. The right half of the figure (k / Na is 0.5 to 1.
0) is a plot of the actual values when the phase of the signal is positive, and the left half of the figure (k / Na is 0.0 to 0.
5) is a plot of actual values when the phase of the signal is negative.

As shown in the figure, the measurement result of S / N = -∞ dB of FIG. 14 and the calculation result of FIG. 4 (Na = 128) are in good agreement. In the conventional radar device, signals and noises of 99.
While an SN ratio of 15.6 dB was required to identify with an accuracy of 85%, a significant improvement effect of the SN ratio can be obtained by adding the phase sampling results 128 times in the present embodiment. It can be seen that even a signal of about -6 dB can be identified. The time required for discrimination is 4 μs as the required addition time because the pulse repetition period is 4 μs from FIG.
s × 128 = 512 μs, which is extremely short.

FIG. 15 shows the added value k when Na = 8192.
It shows the normalized expected value k ′ / Na of ′ and the calculation result in the range of 3σ. In this case, if Na is further increased, the width of the probability distribution is narrowed in proportion to (Na) ^1/2 .
The required addition time is 4 μs × 8192 = 32 ms,
This is a sufficiently short time as the inter-vehicle distance measurement time of the automotive radar. In the case of FIG. 15, it has been confirmed by an experiment similar to that of FIG. 14 that a signal of −20 dB or less can be distinguished from the case of only noise, and the sampling of the phase of the received signal and the simple addition as in the present embodiment are performed. An extremely large effect of improving the SN ratio can be obtained by a simple operation and arithmetic processing, which is performed only. Note that all the circuits used for the addition processing can use general logic circuits, and can be configured with one IC chip by a gate array or the like.

In this embodiment, paying attention only to the positive and negative phases of the reflected pulse of the radar, binarization of the received signal for phase detection, phase sampling and storage are performed at high speed, and a large amount of addition processing is performed accordingly. By doing so, a weak reflected pulse can be detected at high speed by a small output signal, and the sensitivity of reflected pulse detection can be increased. on the other hand,
Desired detection (ranging) with an extremely simple configuration as described above
It is possible to secure a distance, reduce size and weight, and achieve safety.

Although a memory is used for the addition process in this embodiment, a counter for counting the number of additions is provided for each bit of the shift register for sampling, and each bit of each bit is sampled every time sampling is completed. The same effect can be obtained by incrementing the counter according to "H" or "L".

Further, in the present embodiment, if the sampling result is "H", 1 is added and if it is "L", addition is not performed. However, if this is "H", 1 is added, and if "L", 1 is added. May be subtracted. In this case, the addition and subtraction results have the probability of appearance of "H" and "L" of 0.5 only with noise, so the average value is zero, and the average value is 1 when the SN ratio is sufficiently high. .

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 16 is a block diagram showing the configuration of another embodiment common to the inventions of claims 1 and 2. In the figure, those parts which are the same as those corresponding parts of the first embodiment shown in FIGS. 1 and 2 are designated by the same reference numerals, and a description thereof will be omitted. The radar head 5 of this embodiment is configured to include two pulse signal transmitting means 5a and 5a 'having exactly the same configuration. That is, the second drive circuit 5a′-1, the light emitting element 5a′-2, and the lens, which have exactly the same configuration as the pulse transmission system of the first drive circuit 5a-1, the light emitting element 5a-2, and the lens 5a-3. 5a'-3 pulse transmission system.

The switching circuit 51 receives the input of the trigger signal output from the trigger generation circuit 8c, recognizes the timing of outputting the pulse signal to the outside, and determines the transfer destination of the trigger signal as the first transfer destination.
The drive circuit 5a-1 and the second drive circuit 5a'-1 are alternately switched.

FIG. 17 is a timing chart of this embodiment. When the start pulse signal is output via the control means 8, the trigger signal (1) is output at regular intervals. The transmission pulse (2) includes the first trigger signal (1), is output at every odd-numbered trigger signal output, and the transmission pulse (2)
′) Includes the second-time trigger signal (1), and is output every time the even-numbered trigger signal (1) is output. For example, 14 sampling pulses (4) are output during the trigger cycle, and the time interval Δt between sampling pulses is equivalent to 10 m in terms of distance. Then, the sampling value "0" or "1" is read at the corresponding sampling point for each sampling pulse, and is added and stored in each memory while the addition storage signal (5) is on.

In the case of the present embodiment, the switching circuit 51 alternately switches the transfer destination of the trigger signal to the first drive circuit 5a-1 and the second drive circuit 5a'-1.
Can be halved by driving the light emitting element 5a′-2, and thus the light emitting element 5a− has a simple structure.
2. It is possible to double the life of the light emitting element 5a'-2. Therefore, the light emitting element 5a-2 and the light emitting element 5a '
-2 has improved durability and reliability in use.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 18 is a block diagram showing the overall configuration of a common embodiment of the inventions of claims 1, 2 and 4. In the figure, the same parts as in the first embodiment, that is, the radar head 5, the calculation storage means 6, the determination means 7, and the control means 8 are shown.
Are denoted by the same reference numerals as in the first embodiment, and description thereof will be omitted.
The interference detection means 9 calculates the relative speed with respect to the target from the passage of time for detecting the presence or absence of the reflected pulse.
a and the first interference wave detecting means 9A including the relative speed abnormal value detecting means 9b for detecting an abnormal value of the calculation result of the relative speed calculating means 9a, and further, the offset of the added value of the calculation storing means 6 is detected to cause interference. The second interference wave detecting means 9B is composed of an offset detecting means 9c for determining the presence or absence of a wave.

FIG. 19 is an explanatory view for explaining a concrete example of the detection of the reflected pulse and the calculation of the relative speed by the relative speed calculation means 9a. When the sending pulse (2) is radiated to the outside, the receiving means (5b) continuously receives the sending pulse (2) from the sending timing of the sending pulse (2) for a predetermined time (the sending pulse (2) is an external target). After the elapse of a time period (between the reflection and the arrival at the receiving means 5b), the reflected pulse Rf accompanied by noise is detected. The transmission of the transmission pulse (2) and the detection of the reception signal (3) are performed in synchronization with sampling.

The time interval Δt between adjacent sampling pulses (4) is again 6 which corresponds to a distance of 10 m, for example.
6.7 ns, 0 to 130 at 14 sampling points
Distance shall be measured in steps of 10 m up to m. The added value (5) corresponding to each sampling point is stored in the memories M1 to M14. This addition value (5) has a distribution of width ΔM according to the number of additions. Therefore, if the added value (5) stored in each memory exceeds the threshold TH, it is determined that the reflected pulse is detected, and if it is equal to or less than the threshold TH, it is determined that there is only noise. Therefore, as shown in FIG. 19, for example, when the added value of the memories M8 and M9 exceeds the threshold value TH and the reflected pulse Rf is detected from all the added values of the memories M1 to M14, the side of the memory M8 having a short distance is detected. The calculation of the distance from the distance corresponding to the sampling point of 1 to the target (70 m in this case) is executed.

Next, the method of calculating the relative speed will be described. The reflected pulse Rf is detected in the memories M8 and M9 with respect to the received signal (3), and the time detected at the short distance M8 is t1.

When a target such as a vehicle ahead approaches the radar device (the distance is narrowed), the reflected pulse Rf moves in the direction of arrow a, and the first distance measurement time point t1. The reflected pulse Rf in the memories M8 and M9.
Is detected once or several times after the distance measurement time t
2 is detected by the memories M7 and M8, the time difference between these t1 and t2 is the sampling pulse interval Δt of the reflection pulse Rf (here, 1 in terms of distance).
Since it is the time required to shift (corresponding to 0 m), the relative speed is obtained as the approach speed 10 / (t2-t1) (m / s).

On the other hand, when the reflection target is moving away from the radar device, the reflection pulse Rf moves in the direction of the arrow b, and the added value of the memory M8 becomes less than the threshold value TH at a certain distance measuring time t3. , The added value of the memory M9 is also the threshold value TH at time t4 after the reflection pulse Rf is erased.
If the disappearance of the reflection pulse Rf is observed, the time difference between t4 and t3 is the same as the reflection pulse Rf.
Is the time taken to shift one sampling pulse interval, here 10 m, so the separation speed is 10 /
The relative speed is calculated as (t4-t3) (m / s).

For example, when approaching or leaving a stationary target at a speed of 100 (km / h), the relative speed is about 28 (m / s) and the moving time of 10 m is 10/28.
= 0.36s (= 360ms), but the reflected pulse R
As described above, the time required to detect f is 32 ms in the case of adding 8192 times, which is 1/10 or less of the moving time.
s). If the relative speed is smaller than 28 (m / s), the moving time for 10 m is larger than 0.36 s, and the error becomes smaller.

FIG. 20 is a flowchart showing a specific example of the relative speed calculation. That is, first, the added value of each memory is checked in the order of the shortest distance, and it is checked whether or not the reflected pulse is detected (step 171). If the reflected pulse is detected, the detection point is set to Mn, and the detection time t1 is stored (step 172).

Next, at the next detection time, it is checked whether or not the reflection pulse is detected in the memory Mn-1 which is one before the memory Mn (step 173). If it is detected, the detection time t2 at that time is determined and the approach is made. Speed Vr1 is 10 / (t2-
It is obtained by t1) (step 174) and output (step 175).

If the reflected pulse is not detected in the memory Mn-1 in step 173, it is checked whether or not the reflected pulse in the memory Mn has disappeared. If not, step 1
Returning to step 73, the same operation is repeated at the next detection time (step 176).

At step 176, the memory Mn
If the reflected pulse of is disappeared, the detection time t3 at that time is detected.
Is stored (step 177).

Subsequently, it is checked in the memory Mn + 1 whether or not the reflected pulse has disappeared. If not, step 1
Returning to step 73, the same operation is repeated at the next detection time (steps 173-178).

If the reflected pulse disappears also in the memory Mn + 1 at a certain detection time, the time t4 at that time is calculated,
The withdrawal relative speed Vr2 is obtained by 10 / (t4−t3) and is output (steps 178 to 180).

In this relative velocity detection processing, since only the detection and disappearance of the reflected pulse at the sampling point (memory point) having the shortest distance are observed, the requirements for the transmission pulse (pulse signal irradiated to the outside) are Although it is necessary to make the rising edge sharp, it is not necessary to make the pulse width short, but rather it is desirable to make it longer than the width of the sampling pulse.

That is, even in the case of only noise, the probability of exceeding the threshold value TH for reflected pulse detection is not zero, and there is a possibility of false detection at a certain value. Therefore, at two or more (including continuous) sampling points at the same time. By always confirming that it is detected, the probability of false detection due to noise can be reduced.

This is equivalent to adding additional values, and when two additional values are used, if the thresholds are the same, then 3
Equivalent to getting a dB margin. Further, if the same false detection probability as that of detecting a reflected pulse at only one sampling point is considered, the detection threshold value can be lowered and the detection sensitivity can be improved by 3 dB.

Next, the operation of the relative velocity abnormal value detecting means 9b and the offset detecting means 9c for detecting the presence or absence of the interference wave by detecting the offset of the addition result will be described. First,
The state of interference when the same transmission pulse transmitted from an oncoming vehicle is received will be described. Considering the conditions to detect a stationary target by receiving a pulse signal from an oncoming vehicle that is also equipped with the same radar device when the own vehicle equipped with the radar device is stopped, The frequency of the reference clock signal used in the radar device is exactly the same, and the pulse signal from the oncoming vehicle is mixed within the time corresponding to the distance when the radar device of the own vehicle sends the pulse signal and measures the distance. This is the case.

However, since a crystal oscillator or the like having a normal frequency error is used for the reference clock signal, it is observed as a transmission pulse with a synchronization shift corresponding to the frequency error with respect to the pulse signal of the own vehicle. As a result, the measurement result of the radar device and the contents of the added value are affected by the magnitude of the frequency error as follows.

That is, when the frequency error is 2 × 10 ⁻⁷ or less (see FIG. 21), the relative velocity is 2 × 10 ⁻⁷ × 3 × 10.
^From the relationship of ⁸ (here, 3 × 10 ⁸ is the speed of light), 60 (m /
s) It is observed as a moving target of (216 km / h) or less. In this case, it is determined whether it is a false detection due to interference or whether the target is actually moving at the observed relative speed. If this radar device is applied to a rear-end collision warning device of an automobile, a false alarm may occur.

However, the frequency error is 2 × 10 ⁻⁷ or more,
When 4.16 × 10 ⁻⁶ or less, the relative speed is 60 (m
/ S) (216 km / h) or more is observed as a moving target, and the speed is unthinkable as the actual vehicle speed, so it is possible to distinguish the relative speed as an abnormal value. Therefore, erroneous detection due to the interference wave can be prevented by monitoring the relative speed, and when the relative speed calculated by the relative speed calculation means 9a is 60 (m / s) or more, the relative speed abnormal value detection means 9b. Produces an output indicating an outlier.

The frequency error is 4.16 × 10 ^-6 or more and the sampling processing period / addition time or less (4 μs in the above example).
/32ms=1.25×10 ⁻⁴ or less) (see FIG. 22), when the frequency error is 4.16 × 10 ⁻⁶ or more, the interference wave is generated during the time 32 ms required for one distance measuring process. 4.1
Since 6 × 10 ^-6 × 0.032 = 133 ns or more is moved, the relative velocity is calculated by observing only the detection and disappearance of the reflection pulse at the sampling point where the reflection pulse from the target is the closest. Using the method described above, the relative speed cannot be calculated, and no false alarm is issued as long as an alarm logic having two parameters of distance and relative speed is used.

Further, since it is observed over three or more sampling pulses having a sampling pulse period of 66.7 ns, the influence of the interference wave gradually appears in the entire sampling pulse as the frequency error increases, and the sampling process is performed. In the period / addition time, that is, 1.25 × 10 ⁻⁴ , assuming that the interference wave is synchronized at the start of addition, 1.25 × 10 ⁻⁴ × 0.032 = ⁴ μs 32 ms after the addition of 8192 times is completed. Pulse width is 1 because it moves for a time equal to the repetition cycle of
It is always observed at all sampling points at a time rate of 133 ns / 4 μs = 3.33% for 33 ns. This is 8 in 8192 times if the SN ratio of the interference wave is sufficiently high.
An offset of the added value of 192 × 0.0333 = 273 is generated. The threshold value for signal detection in the case of 8192 times addition is the normalized addition value, which is about the average value of noise 0.5 plus about 0.02. Therefore, this offset corresponds to the threshold value, that is, 8
It is a value larger than 192 × 0.02 = 163.

When a uniform offset occurs at all sampling points, it can be identified as an interference wave by monitoring the added value and checking whether a uniform offset has occurred. If the frequency error is 1.25 × 10 ^-4 or less, it may not be said that the part is offset, etc. and it will not be uniform, and if there are multiple targets, observation will be made at three or more sampling points. Therefore, the interference wave cannot be accurately detected from the offset of the added value.

If the frequency error is equal to or greater than the sampling processing period / addition time (= 1.25 × 10 ^-4 ) (see FIG. 23), a uniform offset of the added value is always observed, so that the offset detection means 9c detects the offset. It is possible to identify the presence of an interference wave by the output and detect it when the added value due to the reflected pulse from the target to be originally detected is equal to or more than the offset, and the distance can be measured even when the interference is received. Is.

As described above, in order to detect the influence of the interference wave and eliminate it, it is effective to monitor the relative velocity and to monitor that the added value has no offset. In the former case, if the frequency error of the reference clock is at least 2 × 10 ⁻⁷ or more, the presence of the interference wave can be detected by the magnitude of the relative speed, and the false alarm can be prevented.

In the latter case, since the offset detection depends on the frequency error of the reference clock signal, in order to reliably detect the interference wave, the frequency error must be detected in advance, that is, the frequency error is sampled. By setting the period / addition time (= 1.25 × 10 ⁻⁴ ) or more, the influence of the interference wave can be distinguished while being dispersed over the entire sampling point, and at the same time the target can be detected. That is, in this case, a signal larger than the offset is detected, but the magnitude of the offset is 0.
Assuming that the threshold is 0333, the average of noise and the threshold of 0.5
The sum of 2 and 0.5 is added to 0.5533, which is -17d.
Signals up to B can be detected. This is 3 dB when the signal detection level when there is no interference wave is -20 dB, for example.
However, when converted to the detection distance, the sensitivity is 0.91 times as compared with the case where there is no interference wave, or 6 dB as the sensitivity decrease is 0.84 times, and the influence of the interference wave can be made extremely small. .

By thus setting the frequency error of the reference clock signal so as to disperse the influence of the interference wave over the entire sampling points, extremely large interference wave detection / removal can be obtained.

In the present embodiment, it is possible to eliminate the adverse effect of the interference wave by detecting the presence or absence of the interference wave from the contents of the memory in which the calculation result of the relative speed and the added value are stored. By appropriately selecting the frequency and its error, it is possible to control so as to minimize the adverse effect of the interference wave, and it is possible to minimize the false detection caused by the interference wave. Therefore, by using this, it is possible to realize an application system such as an inter-vehicle distance warning device for an automobile which is extremely highly reliable.

The reference clock signal 1 as in the conventional example
If the frequency is 5 MHz, the period of 66.7 ns corresponds to a distance of 10 m in the radar, but if the distance measurement error of 1% is allowed (1 m error in 100 m), the frequency error is 10 ^-2 or less, that is, the frequency range is 14.85MHz to 1
5.15 MHz is allowed. Frequency error is 1.25x
14.85MHz to 15.15 for higher than 10 ^-4
15 × 10 ⁶ × 1.25 × between 300 MHz of MHz
It suffices to allocate the frequencies so that every 10 ⁻⁴ = 1875 Hz has 160 lines.

The reference clock signal is not always 15M.
It need not be in Hz, and more frequency allocation is possible.

Next, a modification of the third embodiment of the present invention will be described with reference to the drawings. FIG. 24 is a block diagram showing the configuration of another embodiment common to the inventions of claim 1, claim 2 and claim 4. In the figure, the same parts as in the first embodiment, that is, the radar head 5 and the arithmetic storage means 6 are
The same reference numerals as in the embodiment of FIG. The determination means 7'has basically the same configuration as the determination means 7 of the first embodiment, but when the reflection pulse from the target is sampled, whether or not the detection point of the reflection pulse has moved, That is, a relative speed detecting counter 12, an erroneous detection preventing means 13, and a relative speed calculating means 14, which will be described in detail later, based on the relative speed fluctuation determining function and the relative speed fluctuation determining function for determining whether or not the relative speed has changed. It is configured with a control function for controlling the operation of. The control means 8'has basically the same configuration as that of the control means 8 of the first embodiment shown in FIG. 2, but has a width of at least two consecutive sampling points or more with respect to the pulse signal sending means 5a. It is configured to have a function of outputting its own transmission pulse signal.

The relative speed detecting counter 12 counts the number of times the trigger signal output from the trigger pulse generating circuit 8c is output, and notifies the judging means 7'or the relative speed calculating means 14 of the object. The count value is cleared when the relative velocity with the target is calculated.
The erroneous detection prevention means 13 is configured to have a function of confirming that the reflected pulse is detected at at least two consecutive sampling points according to the setting of the control means 8 ′ within one distance measurement processing period. , If continuous detection is not confirmed, it is regarded as noise detection. The relative speed calculation means 14 calculates the multiplication of the time of the output interval of the trigger signal, that is, 4 μs, and the count value of the number of times the trigger signal is output, and calculates the multiplied value by the distance in the distance measurement of one sampling pulse interval ( In the present embodiment, similar to the first embodiment, 10 m) is divided to calculate the relative speed with respect to the target, that is, the approaching speed or the leaving speed.

Also in the case of this modification, when the sending pulse is irradiated to the outside, a reflected pulse accompanied by noise is detected after a lapse of a predetermined time (time until the sending pulse is reflected from an external target and returns). The sending of the sending pulse and the detection of the reflected pulse in the received signal are carried out in synchronization with the sampling pulse. That is, the sampling pulse interval is 66.7 ns, which corresponds to a distance of 10 m, for example.
Then, it is assumed that the distance is measured up to 130 m with 14 pulses. The added value of the sampling data is stored in the memories M1 to M14 corresponding to each sampling point. Then, when the added value continuously exceeds the threshold value TH at any two arbitrary sampling points, the reflected pulse is detected, and when the added value is equal to or less than the threshold value TH, it is determined that only noise.

In the method of calculating the relative velocity of this modification, the sampling point is forward by one point with respect to the time point at which a new reflection pulse is sampled (in the first embodiment, the direction of arrow a (see FIG. 19)). The period (time) until moving to (1) is counted, or the period (time) before moving to one backward (in the first embodiment, the direction of arrow b (see FIG. 19)) is counted to obtain the target. Calculate the relative speed of.

That is, when the reflection target approaches the radar device, the detection time of the reflection pulse becomes short, so the detection point of the reflection pulse moves one position forward from the reference point. During this period, the number of times the trigger signal is output is counted, and this count value k and the repetition period T (= 4 μ of the trigger signal) are counted.
s) is performed. Since this multiplication value is the time required for the reflected pulse to move through one sampling interval (10 m in this case as well), the relative speed is obtained as the proximity speed 10 / (k × T).

On the other hand, when the reflection target is leaving the radar device, the detection time of the reflection pulse becomes long, so the detection point of the reflection pulse moves one position backward from the reference point. During this period, the number of times the trigger signal is output is counted, and the count value k is multiplied by the repetition period T (= 4 μs) of the trigger signal. Since this multiplication value is the time required for the received signal to travel one sampling interval (again, 10 m), the relative speed is obtained as the departure speed 10 / (k × T).

25 and 26 are flowcharts showing the operation of this modification. First, in step 231, it is determined whether or not a trigger signal is output. When it is determined in step 231 that the trigger signal is output, the process proceeds to step 232, the relative speed detection counter 12 is incremented, and then step 233 is performed.
Then, it is determined whether or not the front portion of the reflected pulse is detected. That is, in this modification, the pulse signal transmitting means 5
Since the width of the sending pulse output by a is set to be the width of two sampling points, when detecting the reflected pulse, the front part of the reflected pulse is first synchronized with the sampling pulse. To detect.

When it is determined in step 233 that the front portion of the reflected pulse is detected, the process proceeds to step 234, and it is determined whether or not the rear portion of the reflected pulse is detected. The reason why the rear part of the reflected pulse is detected is that the regular reflected pulse has a width of two sampling pulses or more as described above, and thus erroneous detection can be prevented.

If it is determined in step 234 that the rear part of the reflection pulse is not detected, the process returns to step 213, but if it is determined that the rear part of the reflection pulse is detected, the normal reflection is performed. Considering that the pulse is detected, the process proceeds to step 235, where the sampling point Mn at the time when the front portion of the previous reflected pulse is detected is M.
After converting to m, the process further proceeds to step 236, where the sampling point M at the time of detecting the front part of the current reflection pulse is converted to Mn.

Thereafter, in step 237, is the sampling point Mn at the time of detecting the front portion of the current reflection pulse different from the sampling point Mm at the time of detecting the front portion of the previous reflection pulse? Determine whether or not. If it is determined that there is no difference, it is determined that the relative speed with the target is substantially zero, and the process returns to step 231, but if it is determined that there is no difference, the relative speed with the target is determined. It is considered that the speed fluctuates to cause the approaching speed or the leaving speed with respect to the target, and proceeds to the next step 238.

At step 238, it is judged whether or not the front portion of the current reflection pulse is detected at the sampling point Mm-1. If it is determined that the front part of the current reflection pulse is not detected at the sampling point Mm-1, the process proceeds to step 242, but the front part of the current reflection pulse is detected at the sampling point Mm-1. If it is determined that the proximity speed has occurred, it is determined that the proximity velocity has occurred, and step 239
Proceeding to, the proximity velocity Vr1 is calculated according to the following formula (11).

Vr1 = 10 / (k × T) (11) Here, k is the count value of the relative speed detecting counter 12, and T is the repeating period of the trigger signal of 4 μs.

Subsequently, in step 240, when the proximity velocity Vr1 is output, the process proceeds to step 241, the count value of the relative velocity detecting counter 12 is cleared, and then the process returns to step 231.

On the other hand, when it is determined in step 238 that the front part of the current reflection pulse is not detected at the sampling point Mm-1, the process proceeds to step 242, and the front part of the current reflection pulse is sampled at the sampling point Mm-1. It is determined whether or not it has disappeared. When it is determined in step 238 that the front part of the current reflection pulse does not disappear at the sampling point Mm, the process returns to step 231, but the front part of the current reflection pulse disappears at the sampling point Mm. If it is determined to be true, the process proceeds to step 243, and it is determined whether or not the front part of the current reflected pulse is detected at the sampling point Mm + 1.

When it is determined in step 243 that the front part of the current reflection pulse is not detected at the sampling point Mm + 1, the process returns to step 231, but the front part of the current reflection pulse is sampled. Point M
When it is determined that m + 1 is detected, it is determined that a departure speed has occurred, the process proceeds to step 244, and the departure speed Vr2 is calculated according to the following mathematical expression (12).

Vr2 = 10 / (k × T) (12) Here, k is the count value of the relative speed detection counter 12, and T is the repetition period 4 μs of the trigger signal.

Subsequently, at step 245, when the separation speed Vr2 is output, the routine proceeds to step 246, where after the count value of the relative speed detecting counter 12 is cleared, the routine returns to step 231.

As described above, when the relative velocity is once calculated and then a new reflected pulse is detected, the moving time on the reflected pulse sampling point is counted with reference to the reflected pulse sampling point at this time. In order to calculate the relative speed, it is necessary to make the rise sharp as a requirement for the transmission pulse, but it is not necessary to shorten the pulse width,
Rather, it is desirable to make it longer than the width of the sampling pulse.

Also in this case, the probability of exceeding TH of the reflected pulse detection is not zero even in the case of only noise, and there is a possibility of erroneous detection at a certain value, but it is detected at two or more consecutive sampling points at the same time. It is possible to reduce the probability of false detection due to noise by always confirming that there is noise.

This is also equivalent to adding the additional value, and when two additional values are used, if TH is the same, 3
Equivalent to getting a dB margin. Further, if the same false detection probability as that of detecting a reflected pulse at only one sampling point is taken into consideration, TH of detection can be lowered and detection sensitivity of 3 dB can be improved.

In this modified example, paying attention to the fact that sampling constitutes a kind of distance gate, the result of counting the detection time intervals or disappearance time intervals of the reflection pulse at each sampling point based on the trigger signal, and the sampling By obtaining the relative speed from the distance corresponding to the interval, it is possible to obtain the relative speed with high accuracy even if the pulse width is wide and the sampling interval is rough. Further, by making the pulse width wider than the sampling interval and always confirming that two or more sampling points are simultaneously detected, it is possible to reduce the false detection probability and improve the detection sensitivity of the reflected pulse.

When the reflected pulse is detected, for example, immediately before the reflected pulse that continues for two sampling points, TH
There may be cases where noise exceeding 1 is detected. in this case,
After the noise is detected at the position one sampling pulse before in step 233, the front part of the regular reflection pulse is continuously detected in step 234, so that the rear part of the reflection pulse is detected subsequently, Although the relative speed is actually zero, the calculation of the proximity distance is executed according to the configuration of the flowchart. However, in this case, when the detection of the reflected pulse continues for three times or more, if a determination step such as, for example, postponing the calculation of the relative speed is provided, an erroneous detection is caused only by a time delay of one trigger signal. It is possible to avoid it. Also in this case, if noise is detected twice or more in succession, erroneous detection can be avoided by considering the distance from the sampling reference point, that is, the distance that cannot be measured.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 27 is a block diagram showing a configuration of a common embodiment of the inventions of claims 1, 2 and 5. In the figure, the same parts as those in the first embodiment, that is, the radar head, the sampling means, etc., are designated by the same reference numerals as those in the first embodiment shown in FIG.
The first addition storage means 6B stores the sampling results sampled by the sampling means 6A after being driven by the pulse signal sending means 5a by sequentially and repeatedly adding the sampling results at each sampling point, and stores the addition results of the first embodiment. The configuration is exactly the same as that of the storage means 6B, but the second addition storage means 6 is used.
C stores the sampling results sampled by the sampling means 6A when the pulse signal sending means 5a is not driven, by sequentially and repeatedly adding and storing each sampling point, and only by adding and storing only noise.

The determination means 7 "takes in the sampling data stored in the first addition storage means 6B in response to the command from the control means 8", and reflects the target in the sampling data stored in the first addition storage means 6B. The function of determining whether a pulse is included (similar to the first embodiment), the function of calculating the relative speed of the target (similar to the second embodiment), and the control means 8 ″. In response to a command, the noise sampling data stored in the second addition storage means 6C is fetched,
It is configured to have a function of detecting a noise level at each sampling point within one distance measurement period and using the noise level as a threshold value TH for determining a reflection pulse of a target.

The control means 8 "determines whether or not the reflection pulse of the target is included, and further calculates the relative velocity of the target, the radar head 5, the sampling means 6A, the first means.
The function of controlling the operations of the addition storage means 6B and the determination means 7 ″ (similar to the first embodiment) and the detection of the noise level at each sampling point during the stop period in which the sending means 5a does not send a signal. In order to do so, the radar head 5, the sampling means 6A, the second addition storage means 6C, the determination means 7 ″
And a function of controlling the operation of the drive control means 20.

The drive control means 20 comprises the sampling means 6
It has a function of instructing A and the second addition storage means 6C to sample noise, and ending it.

28 and 29 are flow charts showing the operation of the fourth embodiment. First, in step 281, the counter is reset to N = 0. Step 28
2 and 283, the pulse signal sending means 5a is instructed to send a pulse signal to send a sending pulse (2), and at the same time, the signal received by the pulse signal receiving means 5b is sampled by the sampling means 6A. . The first sampling result is obtained in steps 284 and 285.
To the addition storage means 6B to execute the addition storage, and when the addition storage of each time is completed, the completion is notified to the determination means 7 ″.

Thereafter, in step 286, the control means 8 ″ stops the operation of the sending means 5a, and at the same time, outputs a noise sampling instruction to the drive control means 20, and in steps 287 and 288, the sampling means 6A and the sampling means 6A are connected to each other. The noise received by the receiving unit 5b is sampled by the second addition storage unit 6C, the sampling results are added and stored, and when the storage is completed, the completion of storage is notified to the determination unit 7 ″ in step 289.

Thereafter, in step 290, the counter is incremented to N = N + 1, and in step 291, it is determined whether or not the number of reflection pulse sampling times and the number of noise sampling times have reached a predetermined 8192 times.

In this step 291, N <819
If it is determined to be 2, the process returns to step 282 and the above-described processing is repeated, but the predetermined number of times is 8192.
If the number of times has been reached, the process proceeds to step 292 and the sampling result of the reflected pulse and the sampling result of the noise are transferred to the judging means 7 ″.

At step 293, the noise level at each sampling point is recognized from the noise sampling result and the threshold value TH for detecting the reflected pulse is set. That is, the level of each noise becomes the threshold TH as it is.

At the next steps 294 and 295, the noise sampling result, that is, the noise level and the reflection pulse sampling result are compared to determine whether or not there is a reflection pulse larger than the threshold value TH.

If it is determined in this step 295 that there is no reflected pulse larger than the threshold value TH,
In step 296, it is determined that there is no reflection pulse of the target, the process returns to step 281, and the above processing is repeated. However, if it is determined that there is a reflection pulse larger than the threshold value TH, step 297. The process proceeds to step 281 and it is determined that there is a reflection pulse of the target, and the process returns to step 281.

When it is determined that there is a reflection pulse of the target, the distance from the sampling result of the reflection pulse to the target and the relative speed with respect to the target are used to determine the first embodiment, The calculation is performed by the same procedure as in the second embodiment, and the calculation result is displayed (including an alarm) on the CRT or the like.

In the present embodiment, when the reflection pulse of the target is sampled, as shown in FIG. 30, for example, in the first and second embodiments, a reception level exceeding the uniform threshold value TH is detected at the sampling point M6. Therefore, although it is determined that there is a target at this sampling point, in this embodiment, the individual noise level is measured and set as shown by the curve CTH for each sampling, and the sampling point is set. Since the noise level N6 of M6 tends to be high, it is possible to effectively avoid erroneous detection due to noise without determining the received signal level M6 as a reflected pulse.

Note that the noise detected here is noise peculiar to the environment. For example, weather caused by sunlight, temperature, humidity, etc., noise caused by mechanical parts such as the engine and alternator when installed in a vehicle, and power supply voltage fluctuations. Due to noise.

Further, in the third embodiment, the noise level is measured immediately after each distance measuring process of the target object, but the gist of the present invention is not limited to this, and the steps are not limited to this. 819 instead of N ≧ 8192 in 291
The configuration may be such that an integral multiple of 2 is set.

Furthermore, in this case, the second addition storage means 6C may not be provided, and the first addition storage means 6B may be alternately used for the detection of the reflected pulse and the detection of the noise. In addition, the noise sampling timing may be set arbitrarily by controlling the control means 8 ″ or the drive control means 20 with an external signal.

Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 31 is a block diagram showing the configuration of another embodiment common to the inventions of claim 1, claim 2 and claim 5. In the figure, the same parts as those in the fourth embodiment shown in FIG. 27, that is, the radar head 5, the operation storage means 6, the determination means 7 ″, and the control means 8 ″ are designated by the same reference numerals as those in the third embodiment. The description is omitted. Drive control means 20 '
Is a function of instructing the sampling means 6A to sample noise, and counts the number of noise level detections performed after sampling the reflected pulse (for example, 819).
(2 times), a function of ending the detection of the noise level from the count result of the number of times of detecting the noise level, and the number of times of outputting the trigger signal output from the trigger generation circuit 8c shown in FIG. Is provided with a function of suspending the driving of the pulse signal transmitting means 5a for each number of output times, and is similar to the configuration of the third embodiment, but starts the detection of the noise level according to the command of the external control circuit 31 described later. , Or the function of instructing the end of detection is also different.

The external control circuit 31 includes drive control means 20 '.
A notification circuit 31-1 for notifying the start timing of noise sampling (outputting a noise sampling start signal), an illuminance sensor 31-2 for measuring the ambient illuminance, a temperature for measuring the ambient temperature and the temperature of the radar main body. A sensor 31-3, a wiper switch 31-4 that monitors the operation of the wiper, a raindrop sensor 31-5 that measures the presence or amount of raindrops, a timer 31-6 that measures time, and an ignition that activates various operations of the vehicle. Switch 31-7 and manual switch 3
It is configured to include 1-8.

In the external control circuit 31 having this configuration, the measured value change signal from the various sensors 31-2, 31-3, 31-5, the time-up signal of the timer 31-6, or the various switches 31-4, 31-. The ON switching signals of 7 and 31-8 are output to the notification circuit 31-1, and the notification circuit 31-1 receives one of these signals and notifies the drive control means 20 ′ of the start timing of noise sampling (noise. A notification signal for outputting a sampling start signal) is output, and the drive control means 20 'receives this notification signal and, as in the third embodiment, the sampling means 6A and the second addition storage means 6C.
Instruct to sample noise. Here, various sensors 31-2, 3 are provided to the notification circuit 31-1.
1-3, 31-5, a threshold for determining the presence or absence of the output of the timer 31-6 is set, and various switches 31-4, 31
A function of recognizing ON-OFF of -7, 31-8 may be set, but this is performed by various sensors 31-2, 31-3, 3
1-5, timer 31-6 and various switches 31-4, 3
It may be set to the 1-7, 31-8 side.

32 and 33 are flow charts showing the operation of the external control circuit 31 of the fifth embodiment. First,
In step 321, it is determined from the signal of the illuminance sensor 31-1 whether the illuminance has changed. If it is determined in step 321 that the illuminance has changed, step 3
In step 29, the notification circuit 31-1 outputs a noise sampling start signal to the drive control unit 20 ′ to execute noise sampling, and then returns to step 321, but when it is determined that the illuminance does not change. In step S322, it is determined whether the temperature has changed. When it is determined in step 322 that the temperature has changed from the signal of the temperature sensor 31-3, the process proceeds to step 329, a noise sampling start signal is output to perform noise sampling, and then the process returns to step 321. However, if it is determined that the temperature does not change, the process proceeds to step 323, and it is determined whether or not the wiper switch 31-4 is turned on.

If it is determined in step 323 that the wiper switch 31-4 is turned on, step 32
9, the noise sampling start signal is output to execute noise sampling, and then the process returns to step 321, but if it is determined that the wiper switch 31-4 is not turned on, the process proceeds to step 324. It is determined whether raindrops have been detected.

In step 324, the raindrop sensor 31
If it is determined that a raindrop is detected by the signal from −5, the process proceeds to step 325, and it is determined whether or not the wiper switch 31-4 is turned off. However, if it is determined that the raindrop is not detected, the step is performed. Proceed to 326. Step 3
25, when it is determined that the wiper switch 31-4 is turned off, the process proceeds to step 329, the noise sampling start signal is output to execute the noise sampling, and then the process returns to step 321. If it is determined that -4 is not turned off, the process proceeds to step 326.

Thus, in step 326, it is determined by the signal of the timer 31-6 whether or not a fixed time has elapsed. When it is determined in step 326 that the fixed time has passed, the process proceeds to step 329, the noise sampling start signal is output to execute the noise sampling, and then the process returns to step 321. However, the fixed time does not pass. When it is determined that the ignition switch 31-7 is turned on, the process proceeds to step 327.

If it is determined in step 327 that the ignition switch 31-7 is turned on, the process proceeds to step 329, where a noise sampling start signal is output to execute noise sampling, and then step 32.
Although it returns to 1, if it is determined that the ignition switch is not turned on, the process proceeds to step 328,
It is determined whether or not the manual switch 31-8 is turned on. In step 328, the manual switch 31-8
When it is determined that the switch is turned on, the process proceeds to step 329, the noise sampling start signal is output to perform noise sampling, and then the process returns to step 321. However, it is determined that the manual switch 31-8 is not turned on. If so, the process directly returns to step 321.

Thus, in this embodiment, the drive control means 20 'for controlling whether or not noise sampling is executed.
As an external control circuit 31 for controlling the illuminance sensor 31-
2. Since the temperature sensor 31-3, the wiper switch 31-4, the raindrop sensor 31-5, the timer 31-6, the ignition switch 31-7, and the manual switch 31-8 are provided, the weather conditions such as sunshine, temperature, and rain can be reduced. Change, vehicle engine,
Changes in the operating states of mechanical parts such as alternators and changes in power supply voltage may cause changes in the noise state resulting from them. The threshold TH can be changed by measuring the noise level when sampling the reflected pulse of the target. Therefore, the normal reflected pulse of the target can be always captured, and error-free distance measurement and relative velocity of the target can be calculated.

Next, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 34 is a block diagram showing the configuration of still another embodiment common to the first, second and fifth inventions. In the figure, the same parts as those of the fourth embodiment, that is, the radar head 5, the arithmetic storage means 6, the determination means 7 ″, and the control means 8 ″ are designated by the same reference numerals as those of the third embodiment shown in FIG. The description is omitted. Drive control means 2
0 ″ may be an internal command of the control means 8 ″, but the sampling time of noise is recognized by the command of the external signal such as the signal from the external control circuit 31 shown in the fourth embodiment, The operation (opening / closing) of the shutter 41 described later is controlled.

The shutter 41 is composed of, for example, a liquid crystal shutter and a mechanical shutter, and has drive control means 20 ″.
The opening / closing of the pulse signal is controlled by the command to control the irradiation of the pulse signal from the pulse signal transmitting means 5a to the outside.

35 to 37 are flowcharts showing the operation of the sixth embodiment. First, in step 351, it is determined whether or not a noise sampling start signal is output. When it is determined in step 351 that the noise sampling start signal is output, the process proceeds to step 352, and after resetting the counter value to zero,
Proceeding to step 353, the shutter 41 is driven (ON) to be closed.

Subsequently, in step 354, the pulse signal sending means 5a sends a pulse signal, but since the shutter 41 is closed, sending to the outside is blocked. In step 355, the reflected pulse signal receiving means 5b is driven to take in noise, and noise is sampled. In step 356, the noise sampling result is added to the storage value of the second addition storage means 6C and stored. In step 357, the value of the counter is incremented to N + 1. In step 358, it is determined whether or not the value of the counter is 8192 times or more, which is set as the number of sampling times required for one noise measurement process in this case.

If the value of the counter is less than 8192 in step 358, the process returns to step 354 and the above noise level sampling is repeated. However, if it is determined that the value of the counter is 8192 or more,
In step 359, the shutter 41 is driven (OFF)
And let it open.

In step 360, the value of the counter is reset to zero, and then the process proceeds to step 361, in which the pulse signal sending means 5a sends a pulse signal. This pulse signal is sent to the outside because the shutter 41 is open.

At step 362, the reflected pulse signal receiving means 5b is driven to take in the received signal containing the reflected pulse of the target and sampling is performed. Step 363
In, the sampling result of the received signal is added to the storage value of the first addition storage means 6B and stored. Step 36
In step 4, after incrementing the counter value to N + 1, the routine proceeds to step 365, where it is determined whether or not the counter value is 8192 times or more set as the number of sampling times required for one distance measuring process.

If it is determined in step 365 that the counter value is less than 8192, step 361
The procedure is returned to and the above-mentioned processing is repeated, but if it is determined that the counter value is 8192 or more, it means that a series of noise level measurement and distance measurement operation to the target object have been completed. Then, the noise sampling data and the target reflection pulse sampling data are transferred to the judging means 7 ″.

Thereafter, in step 367, the noise level is detected from the noise sampling data, and the threshold TH for detecting the received signal is set for each sampling point. In step 368, the threshold value TH for each sampling point set this time is compared with the sampling data of the received signal. In step 369, it is determined whether or not there is a sampling point at which a value exceeding the threshold TH indicating the noise level exists in the data at each sampling point of the received signal. If it is determined in step 369 that there is no sampling point showing a value exceeding the threshold value TH among the sampling data of the received signal, the process proceeds to step 370, it is determined that there is no reflected pulse, and the process returns to step 351. When it is determined that there is a sampling point having a value exceeding the threshold value TH in the sampling data of the signal, the process proceeds to step 371, the presence of the reflected pulse is determined, and the process returns to step 351.

In this embodiment, the shutter 41 which is opened and closed by the input of an external signal, for example, is provided in front of the pulse signal transmitting means 5a, and noise is detected when the shutter 41 is closed. Therefore, weather conditions such as sunshine, temperature, and rain can be detected. Change, operation change of mechanical parts such as engine and alternator when installed in the vehicle, and further fluctuation of power supply voltage, and remeasure the noise level when any of these changes occur, The threshold value TH at each sampling point when sampling the reflected pulse can be changed. Therefore, the normal reflected pulse of the target can be always captured, and error-free distance measurement and relative velocity of the target can be calculated.

Note that, for example, step 358, step 3
The processing of each of the 65 is not limited to the determination of N ≧ 8192, and if an appropriate integer s, k times is selected for these, the noise level is s.
It is possible to configure the distance measurement processing to be performed k times after performing the measurement once, and it is possible to realize arbitrary accuracy, and by increasing the values of s and k, it is possible to achieve high accuracy of distance measurement. It can also be achieved.

Next, a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 38 shows a common embodiment of the inventions of claims 3-5. The characteristic part of the seventh embodiment is the configuration of the operation storage means 6 ', and the operation storage means 6 in each of the first to sixth embodiments is replaced with the operation storage means 6'in FIG. As a result, the radar device of this embodiment is constructed.

The operation storage means 6'receives the sampling pulse signal from the sampling pulse generating circuit 8d and outputs a gate command only to a predetermined sampling point, and a gate timing switching circuit 6'-1 and a trigger generating circuit 8c. A counter 6′-2, which outputs a sampling timing switching signal when a predetermined number of trigger signals are counted by counting the trigger signals, and a binary signal for each gate timing input from the gate timing switching circuit 6′-1. An input gate circuit 6'-3 for inputting and an addition storage circuit 6'-4 for sequentially adding and storing the binarized signals at predetermined sampling points input by the input gate circuit 6'-3 are provided. An output gate circuit 6'-5 that receives the signal from the counter 6'-2 and outputs the stored addition value of the addition storage circuit 6'-4 and the storage of the addition value for each of 14 sampling points at different times. And a memory switching circuit 6'-7 for switching and storing the added value output from the output gate circuit 6'-5 to the memory address corresponding to the designated sampling point in the memory 6'-6. Is equipped with.

Next, the operation of this arithmetic addition means 6'will be described with reference to the timing charts of FIGS. First, the operation principle will be described. The counter 6'-2 gives a gate timing switching signal to the gate timing switching circuit 6'-1 every time the trigger signal is counted by a predetermined number m, and the counter 6'-2 outputs the gate timing switching signal to the addition storage circuit 6'-4. A memory clear signal is given, an output signal is given to the output gate circuit 6'-5, and a memory address switching signal is given to the memory switching circuit 6'-7.

The gate timing switching circuit 6'-1 receives the signal from the counter 6'-2 and switches the number of sampling pulse input gate signal to be applied to the input gate circuit 6'-3 in each sampling. Each time the input gate circuit 6'-3 receives the input gate signal from the gate timing switching circuit 6'-1, the gate is opened to input the binarized signal to the addition storage circuit 6'-4, and the addition storage circuit 6'-4 is supplied. The circuit 6'-4 additionally stores the binarized signal input from the input gate circuit 6'-3.

The output gate circuit 6'-5 is a counter 6'-
2 outputs the storage addition value of the addition storage circuit 6'-4, and transfers it to any address of M1 to Mn on the memory 6'-6 designated by the memory switching circuit 6'-7. , Addition memory circuit 6'-4 is cleared.

Therefore, as shown in the timing charts of FIGS. 39 and 40, in the first m samplings (m = 8192 times in one detection process in each of the above-described embodiments). Only the binarized signal input at the timing of the first sampling pulse is added and stored m times,
When the counter 6'-2 counts m trigger signals and gives an output command to the output gate circuit 6'-5, the stored addition value of the addition storage circuit 6'-4 is output and the memory 6'-6 of the memory 6'-6 is output. Transfer to M1 address.

Next, the gate timing switching circuit 6'-1
Switches the gate timing so as to output the input gate signal in synchronization with the second sampling pulse of each sampling, and the input gate circuit 6′-3 changes the input timing of the second sampling pulse in each sampling. Each time the gate is opened and the binarized signal is input to the addition storage circuit 6′-4, the addition storage is repeated m times, and after the addition storage is performed m times, the storage addition value is stored in the memory 6
Transfer to address M2 of -6.

Thereafter, in the same manner, every time m trigger signals are counted, the timing of opening the input gate is shifted by 1 sampling pulse period Δt, and the memory addition values obtained by sampling m times are sequentially stored in the memories 6'-6. M
3, M4, ... Transfer to address. Finally, only the binarized signal input to the n-th sampling point in each sampling is added and stored m times, and this is stored in Mn.
It will be transferred to the address and the sampling of the received signal at each of a series of n sampling points will be completed.

When the sampling is completed in this way, the contents stored in the memory 6'-6 are judged by the judging means 7, 7'or 7 ".
The detection of the reflection pulse Rf and the calculation of the distance from the sampling point where the reflection pulse Rf is detected to the target are executed in the same manner as in each of the above-described embodiments.

As a modified example of this embodiment, another same memory is prepared together with the memory 6'-6, and the series of operations described above is executed during the suspension period of the pulse sending means and the other memory is If it is stored in each address, the noise level is detected at each sampling point and used as a threshold for determining the reflection pulse Rf, as in the fourth to sixth embodiments shown in FIGS. 27 to 37. This enables more accurate distance measurement of the target.

Further, in each of the first to seventh embodiments, sampling is performed for each of a plurality of sampling points which are temporally different from the transmission timing of the transmission pulse, the sampling values are added, and the addition value is added by the number of additions. If there is a sampling point where the divided normalized added value exceeds a predetermined threshold value TH, the distance corresponding to that point is calculated and used as the distance to the target. If it is simply to determine whether or not there is any obstacle behind, for example, to determine whether or not there is an obstacle 1 m away from the host vehicle, binarize at the sampling point corresponding to that. The signals are added a predetermined number of times, and the normalized addition value is compared with a predetermined threshold value TH or a noise level measured separately, and if the received signal level is high, it is determined that there is an obstacle, and The emitted or may be configured to perform output processing or view.

Furthermore, as a modification of the seventh embodiment described above, the number of times of addition can be set to be different for each sampling point. That is, a signal received by a long-distance target has a low SN ratio and requires a large number of additions, but a signal received by a short-distance target has a high SN ratio and requires a small number of additions. The number of additions of the corresponding sampling points is set small, and the number of additions of the sampling points corresponding to the long distance is set large. This can be realized by operating the output timing of the end pulse output from the start pulse generation circuit 24b through the sampling pulse generation circuit 24d.

Next, an eighth embodiment of the present invention will be described with reference to the drawings. FIG. 41 shows a common embodiment of the inventions of claims 2 to 6, and in this embodiment, the same parts as the circuit configuration of the first embodiment shown in FIGS. 1 and 2 are the same. It is shown with reference numerals. That is, the radar head 5, the arithmetic storage unit 6 that samples the binarized signal from the radar head 5 and adds and stores the sampled signal at each sampling point, and the sampling point that indicates the stored added value that exceeds the threshold value TH are specified and corresponded. The determination means 7 for calculating the distance to the target and the control means 8 for controlling the operation of each part have the same configuration. In addition, the radar head, the calculation storage means, the determination means, and the control means are shown in FIGS.
7, FIG. 31, FIG. 34, etc. can also be used. And the feature of this eighth embodiment is that
The peak detection means 1 is provided between the calculation storage means 6 and the determination means 7.
5 is provided.

The peak detecting means 15 forming this characteristic portion is a processing function additionally incorporated as a software program of a computer constituting the judging means 7, and the arithmetic storage means 6 stores each sampling point obtained by repeating sampling. The added value is compared with the threshold value TH to identify a sampling point that exceeds the threshold value TH, and when a plurality of sampling points are found, the peak point is estimated by the approximation process described later from the magnitude relationship of the stored added value between the sampling points. Then, the process of passing the information to the determination means 7 is performed.

The operation of the peak detecting means 15 will be described with reference to the timing chart of FIG. 42, the flowchart of FIG. 43 and the graph of FIG. From the pulse signal sending means 5a, a sending pulse (2) having a width of at least the sampling pulse cycle Δt (for example, 66.7 ns is used in each of the above embodiments) is sampled (in each of the above embodiments, a sampling pulse). The reflected pulse signal receiving means 5b continuously receives the signal (3) from the outside, converts it into a binarized signal, and outputs it to the arithmetic storage means 6.

Therefore, after the sending pulse (2) output from the sending means 5a is reflected by the reflecting target, it enters the receiving means 5b as a reflected pulse Rf with a time delay Td corresponding to the distance, but the arithmetic storage means 6 outputs a predetermined number of, for example, 14 sampling pulses (4) for each trigger period, adds the binarized signal as sampling for each sampling point, and stores it. Number of samplings for one distance measurement operation (number of outputs of trigger signal (see FIG. 3) =
The number of times of sending the sending pulse) is, for example, 8 in the above embodiments.
When the addition and storage processing is performed a predetermined number of times, the sampling addition output (8) is obtained for each memory corresponding to each sampling point.

Then, this sampling addition output (8)
In addition, since the pulse width of the transmission pulse (2) is wider than the sampling pulse period Δt, the reflected pulse is detected at a plurality of sampling points.

Therefore, the peak detecting means 15 receives the sampling addition output (8) from the operation storing means 6 and outputs (9)
The peak detection processing as shown in (1) is executed, and the time delay T from the transmission pulse transmission timing corresponding to the peak point is passed to the determination means 7.

The peak detection processing procedure is shown in the flowchart of FIG. 43 and the graph of FIG. 44, and is as follows. First, the addition data S of all sampling points Xi
i is sequentially read, and the sampling points p1 and p2 are specified by setting the largest added value for the data exceeding the threshold value TH as the first peak value a1 and the next largest added value as the second peak value a2 (step 401). ~ 40
4). Here, as shown in FIG. 44, the first peak point p1
(The position of Xn as the sampling point) is the second peak point p
It is assumed that the position is farther than 2 (the position of Xn-1 as the sampling point), and their added values Sn and Sn-1 are shown as a1 and a2 to show that they are peak values.

Next, the distance between the sampling points p1 of the first peak and the sampling points p2 of the second peak is judged (step 405) to determine the first peak point p.
When 1 is longer than the second peak point p2 at the corresponding distance, the addition value a1 (= of the first peak point p1 (= Xn)
Sn) and the added value Sn + 1 of the sampling points Xn + 1 whose distance is one step farther than that are connected by a straight line A1 (step 406a), and similarly, the second peak point p2 (= X
The added value a2 (= Sn-1) of n-1) and the added value Sn-2 of the sampling point Xn-2 corresponding to the distance a2 (= Sn-1) are connected by a straight line A2 (step 407a).

The sampling point p1 of the first peak is determined to be the sampling point p of the second peak by the judgment in the above step 405.
If the distance is shorter than 2 in the corresponding distance, conversely, the added value a1 of the first peak point p1 and the added value of the sampling points corresponding to the distance closer than that by one step are connected by a straight line (step 406b). , Similarly, the second peak point p2
Is added to the added value a2 of the sampling point whose distance is one step farther than that, and is connected by a straight line (step 40).
7b).

Next, the intersection point a of the two straight lines A1 and A2 obtained by these processes is obtained as the peak position of the added value data, and the time p corresponding to this intersection point a is reflected pulse from the transmission pulse transmission timing. It is calculated as the time T required until reception (step 408).

In this way, the peak detecting means 15 approximates the received waveform of the reflected pulse Rf by the tangents on both sides near the peak point, and obtains the time T of the peak point by the approximation method of estimating the peak point by the intersection of the tangents. , And outputs this to the determination means 7. As a result, the determination means 7 calculates the distance corresponding to the time T, outputs it as necessary, and issues an alarm. Here, for example, if the distance corresponding to the time interval Δt between the sampling points is 10 m, the distance is calculated as the distance L = 10 · T / Δt (m) (step 409).

Regarding the operation of this judging means 7,
Any of the above embodiments may be used. It can also be used to detect relative speed. Also, this 8th
In the embodiment of the present invention, the approximation method of the peak detecting means is not limited to the above example, and various methods used as a quadratic curve approximation in which the time is the X axis and the added data is the y axis and other approximation methods are used. Widely available.

In this way, the peak detection means can find the actual peak position of the received signal shape in the middle of the sampling points, and the ranging accuracy can be improved without making the sampling points fine. . For example, in FIG.
Reference numeral 5 shows a distance measurement result when a target is measured with a radar device having sampling points set at 10 m intervals at 2 m intervals within a 10 m range of 30 to 40 m. It can be seen that the distance can be measured, and the measurement accuracy is improved without reducing the sampling pulse period.

Next, a ninth embodiment of the present invention will be described with reference to the drawings. FIG. 46 shows a common embodiment of the inventions of claims 1-9. The feature of this embodiment is that when it is determined that the normalized addition value of any sampling point of the arithmetic storage unit 6 exceeds the upper limit value, the sensitivity of the apparatus is adjusted to be lowered, and vice versa. When it is determined that the normalized addition value of the sampling points does not exceed the lower limit value, the sensitivity adjusting means 16 for increasing the sensitivity of the device is provided, and other parts are the same as those of the radar device of FIG. Are denoted by the same reference numerals.

FIG. 47 shows the circuit structure of the ninth embodiment in more detail. In the radar apparatus shown in FIGS. 2 and 16, the pulse signal transmitting means 5a of the radar head 5 is used.
Is added to the drive circuit 5a-1 forming the output signal output control circuit 5a-4, and the limiter amplifier 5b-3 forming the reflected pulse signal receiving means 5b is added to the output control circuit 5a-4. On the other hand, a gain control circuit 5b-5 that performs a variable gain control function (so-called AGC function) is added, and an output gain adjustment circuit 17 configured by a microcomputer is added as sensitivity adjustment means 16 to these radar devices. It is prepared for the purpose. In addition,
The output gain adjusting circuit 17 can be an independent circuit, but can also be configured to be incorporated as a software program in the computer forming the judging circuit 7.

As the output control circuit 5a-4 for automatically controlling the output of the output pulse, the output of the drive circuit 5a-1 is adjusted in order to adjust the current or the voltage applied to the light emitting element 5a-2 such as a laser diode. For example, a circuit such as a potentiometer is used which automatically adjusts the resistance value of the resistor of the stage according to a signal from the outside. Further, as the gain control circuit 5b-5 for automatically adjusting the gain of the limiter amplifier 5b-3, for example, a widely used AGC circuit can be used.

Next, the operation of the ninth embodiment will be described. The output gain adjusting circuit 17 divides the addition value for each sampling point stored by the sampling addition circuit 6b of the operation storage means 6 by the number of additions to obtain a normalized addition value of 1
A check is made each time the distance measurement operation is completed, and if the normalized addition value at any of the sampling points exceeds the preset upper limit value A, a command for lowering the output signal output, or /
And a command for suppressing the gain of the received signal is output, and on the contrary, the normalized addition value at each sampling point is checked, and any normalized addition value has a lower limit value B (usually, use the threshold value TH as this lower limit value. If it is less than the value of (1), the command to increase the output of the transmission signal and / or the command to increase the gain of the reception signal are output.

On the other hand, when the output control circuit 5a-4 receives an instruction to increase or decrease the output, the output control circuit 5a-4 activates the output variable control function to output the output of the drive circuit 5a-1 step by step at preset intervals. The output is increased or decreased, and the intensity of the transmitted pulse is increased or decreased step by step and output.

When the gain control circuit 5b-5 receives a command to increase or decrease the gain, the gain control circuit 5b-5 operates the variable gain control function to increase or decrease the gain of the limiter amplifier 5b-3 step by step at a preset step. Then, the strength of the received signal is increased or decreased step by step and output.

Even when the distance measuring operation executed after this one-time output adjustment and / or gain adjustment is completed, if the normalized addition value still exceeds the upper limit value A, further output is performed. Is repeatedly adjusted to lower the gain and / or the gain is decreased. Conversely, if the normalized addition value is still below the lower limit value B, the adjustment to further increase the output and / or the adjustment to increase the gain are repeated to detect the reflected pulse. The normalized addition value at the sampling point is set to fall between the upper and lower limit values A and B.

The procedure of the automatic sensitivity adjustment processing by the above series of output gain adjustments will be described with reference to the flowchart of FIG. First, the maximum gain and the maximum output are set to prevent excessive gain increase or output increase (step 420). After this, step 4 is performed for each normal distance measuring operation.
The processing from 21 onward is repeated.

When one distance measuring operation is completed (step 4
21, 422), the output gain adjustment circuit 17 scans the added value at each sampling point of the sampling adder circuit 6b, and determines whether or not the normalized added value obtained from these added values exceeds the upper limit value A. (Step 42
3). Here, if there are sampling points (for example, sampling points Xi + 1, Xi + 2) indicating the normalized addition value exceeding the upper limit value A as shown in FIG. A decrease or / and a gain decrease command is output to reduce the output of the output pulse by one step or / and the gain of the received signal is decreased by one step, and the next distance measuring operation is performed (step 424).

When the normalized addition value exceeding the upper limit value A is not found in the judgment of the step 423, it is then determined whether or not there is a sampling point showing the normalized addition value larger than the lower limit value B (step 425). Here, as shown in FIG. 50, the lower limit value B (here, it is set to the threshold value TH)
If there is no normalized addition value that exceeds, the sensitivity is too low, so the above-described output increase or / and gain increase command is output to increase the output of the output pulse by one step, and / or the gain of the received signal is increased by one step. Then, the next distance measuring operation is performed (step 426).

In the above steps 421 to 426, the normalized addition value of any sampling point does not exceed the upper limit value A, and the normalized addition value of any sampling point is the lower limit value B.
The above process is repeated until the distance measuring sensitivity is automatically adjusted.

When the automatic adjustment of the sensitivity is completed by the above procedure, the determination circuit 7 thereafter executes the original distance calculation processing (step 427).

By performing the automatic sensitivity adjustment in this way, it becomes possible to achieve both distance measurement of a reflection target at a long distance and distance measurement of a reflection target at a short distance. For example, if a large output signal output corresponding to the distance measurement of a long-distance reflective target and a large gain are fixed and an attempt is made to measure a short-distance reflective target, sampling points Xi + 1, Xi in FIG. The normalized addition value of +2 exceeds the upper limit value and reaches the saturation value S, which makes it impossible to accurately measure the target position. On the other hand, if the output of a small transmission signal corresponding to the distance measurement of a reflecting target at a short distance and the small gain are fixed and the distance of a reflecting target at a long distance is measured, the sampling point Xj + of FIG.
Like the normalized addition value of 1 and Xj + 2, the threshold value TH cannot be exceeded even though the target is actually detected, and the detection cannot be performed. Therefore, if the sensitivity adjustment function is activated according to the procedure described above, the reflected pulse can always be received and distance-measured at the optimum reception intensity regardless of whether the target object is in the near or far position. The reliability can be improved.

The automatic sensitivity adjusting function is not limited to the above-mentioned embodiment, and the procedure of performing the first several steps of the sensitivity adjusting by the gain control, and if it is still insufficient is performed by the output control. , Or vice versa. Further, in order to simplify the circuit structure, the sensitivity can be adjusted only by the gain control function or the output control function.

As a modification of the ninth embodiment,
The configuration shown in FIG. 51 can also be used. That is, FIG.
The radar apparatus having the peak detecting means 15 of the eighth embodiment shown in FIG. 1 is further provided with the above-mentioned sensitivity adjusting means 16.

By doing so, as shown in FIG. 52A, when the sensitivity adjusting means 16 is not provided, the normalized addition value at any one of the sampling points Xi reaches the saturation value S, According to this modified example, when the peak position p is detected by the peak detection means 15, there is a deviation from the peak position r of the actual received signal.
As shown in (b), the normalized addition value at any sampling point can be set to the upper limit value A or less by the sensitivity automatic adjustment, and the peak position p can be accurately detected.
The ranging accuracy can be further improved.

Next, a tenth embodiment of the present invention will be described with reference to the drawings. FIG. 53 shows a common embodiment of the inventions of claims 1 to 7 and claim 10. The feature of this embodiment is that when it is determined that the normalized addition value at any sampling point of the operation storage means 6 exceeds the upper limit value set in advance for adjusting the number of additions, the operation storage means 6 is detected. When it is determined that the normalized addition value of any sampling point does not exceed the lower limit value set in advance for adjustment of the number of additions, the number of additions of the arithmetic storage unit 6 is changed. Sensitivity adjusting means for automatically setting the number of additions to the necessary minimum number by increasing the number of adjustments and reducing the time required for one distance measurement to perform distance measurement with a sufficient SN ratio. 18 is provided, and the other portions are the same as those of the radar device of FIG. 1 and are denoted by the same reference numerals.

FIG. 54 shows a more specific circuit configuration of the tenth embodiment. In addition to the radar apparatus shown in FIGS. 2 and 16, an addition number adjustment circuit 19 composed of a microcomputer is provided. The sensitivity adjusting unit 18 is additionally provided. It should be noted that this addition count adjustment circuit 19
Can also be configured to be incorporated as a software program in the computer configuring the determination circuit 7.

The operation of the adder number adjusting circuit 19 will be described. The sampling adder circuit 6 of the arithmetic storage means 6 is explained.
The normalized added value obtained by dividing the added value for each sampling point stored in b by the number of additions is checked every time the distance measuring operation is completed, and the normalized added value at any sampling point is set in advance. If the upper limit value A'is exceeded, the number of times of addition Na is repeated in one distance measuring operation (in the above-described embodiments, the number of times of addition is 8192).
Is output, and the normalized addition value for each sampling point is checked on the contrary. If any of the normalized addition values is below the lower limit value B ', the number of additions repeated in one distance measurement operation Is output to the sampling pulse generating circuit 8d of the control means.

On the other hand, the sampling pulse generating circuit 8d counts the number of trigger signals received from the trigger generating circuit 8c to a preset count number (this is the same as the variably set number of additions). When it reaches, the output timing of the output end pulse is adjusted to be decreased or increased step by step. As a result, the number of times of addition of the sampling and adding circuit 6b is adjusted to be increased or decreased, and the stored addition value at the sampling point where the reflected pulse is detected is adjusted to be increased or decreased according to the number of times of addition.

Even when the distance measuring operation executed after the adjustment of the number of additions is completed, if the normalized addition value still exceeds the upper limit value A ', adjustment to further decrease the number of additions is performed. Repeatedly, on the contrary, if the normalized addition value is still below the lower limit value B ′, the adjustment to increase the number of additions is repeated, and the required minimum number of additions is sufficient for S.
It is possible to determine the presence or absence of a target with N ratio and to perform distance measurement operation. Especially, the distance measurement at a short distance where the SN ratio is originally large. It is necessary to provide various responses), and the distance can be measured with a small number of additions, and the processing speed can be increased.

The procedure of the automatic sensitivity adjustment processing by the series of addition times adjustment will be described with reference to the flowchart of FIG. First, the number of additions Na is set to a standard number, for example,
As illustrated in each of the above examples, 0 to 130 m
The sampling points are set to 14 points in order to perform sampling at intervals of 10 m, and when the sending cycle of the sending pulse is 4 μs and the sampling pulse cycle Δt is 66.7 ns, the number of additions is set to 8192 times (step 430).

When a certain distance measuring operation is completed (steps 431 and 432), the addition number adjustment circuit 19 scans the added value at each sampling point of the sampling adder circuit 6b, and the normal value obtained from those added values. It is determined whether or not there is a sampling point at which the addition value exceeds the upper limit value A '(step 433). Here, as shown in FIG. 56, if there are sampling points (for example, sampling points Xi + 1, Xi + 2) indicating the normalized addition value exceeding the upper limit value A ′,
A command for advancing the output timing of the end pulse by one step is output to the sampling pulse generating circuit 8d to decrease the number of additions of the sampling adding circuit 6b by one step, and the next distance measuring operation is performed (step 434).

If the normalized addition value exceeding the upper limit value A'is not found in the judgment of step 433, then the lower limit value B '
It is determined whether there is a sampling point showing a larger normalized addition value (step 435). Here, FIG.
If there is no normalized addition value that exceeds the lower limit value B ', as shown in, the command for delaying the output timing of the end pulse by one step is output to the sampling pulse generation circuit 8d, and the addition count of the sampling addition circuit 6b is set to 1 The number of steps is increased, and the next distance measuring operation is performed (step 436).

In the above steps 431 to 436, the normalized addition value of any sampling point does not exceed the upper limit value A ',
Further, it is repeated until the normalized addition value of any sampling point becomes equal to or higher than the lower limit value B ', whereby the target can be discriminated and the distance measurement operation can be performed with a sufficient SN ratio with the minimum required number of additions. Is adjusted automatically.

When the automatic adjustment of the sensitivity is completed by the above procedure, the determination circuit 7 thereafter executes the original distance calculation processing (step 437).

By automatically adjusting the number of additions in this way, it is possible to determine the presence / absence of a target with a sufficient SN ratio with a necessary minimum number of additions, and to perform a distance measurement operation. In particular, the SN ratio is originally large. In distance measurement (in short distances, it is necessary to shorten the distance measurement time as much as possible so that a quick response can be made), distance measurement can be performed with a small number of additions and processing speed is increased. You will be able to speed up.

As a modification of the tenth embodiment, the structure shown in FIG. 58 may be used. That is,
In the radar apparatus including the peak detecting means 15 of the eighth embodiment shown in FIG. 41, the sensitivity adjusting means 1 described above is further added.
8 is provided.

By doing this, as shown in FIG.
First, by performing the distance measurement after automatically adjusting the optimum number of additions and performing the peak detection by the peak detection means 15, the peak position p can be accurately detected and the speed can be increased.

As an embodiment in which the ninth embodiment and the tenth embodiment are combined, an automatic sensitivity adjusting function,
It is also possible to have a configuration in which automatic adjustment of the number of additions is provided together with automatic adjustment of the output of the output signal and automatic adjustment of the amplification gain of the received signal.

The processing procedure in this case will be described below. First, perform sampling addition processing of 1024 times,
If there is a sampling point exceeding the upper limit value A at that time, the gain of the receiving means is reduced, and / or the transmission output of the transmitting means is reduced. In addition, when the addition value at any sampling point does not exceed the lower limit value at the time of sampling addition for 1024 times, increase the gain of the receiving means, or
Or / and increase the transmission output of the transmission means. This allows
The optimum SN ratio can be obtained.

When the sampling addition value falls within the range between the upper limit value and the lower limit value, the addition value is set to 8192 times so that the addition value with a small variation can always be obtained. The normal operation for determining the presence / absence is performed. Note that the number of additions is set to 7
It may be 168 times (= 8192-1024).

In this way, first, the gain adjustment control and the output adjustment control are performed with a small number of additions, which is a fraction of the predetermined number of additions (8192), so that the gain is adjusted in a short time. It becomes possible to optimize the output and the output, and as a whole, it becomes possible to accurately determine the presence or absence of the reflected signal and to perform the distance measuring operation in a short time and with high accuracy.

Also, in the above, if sampling addition is performed 1024 times and the added value at any sampling point exceeds the upper limit value at that point, the gain of the receiver is lowered or / and the transmitter is sent. If the added value at any sampling point does not exceed the upper limit value, directly set the number of additions to 8192 so that the added value with less variation is always obtained. After that, the normal operation of determining the presence / absence of the reflected signal is performed. The number of times of addition may be set to 7168 (= 8192-1024).

Also in this case, first, the gain adjustment control and the output adjustment control are performed by a small number of additions, which is a fraction of the predetermined number of additions (8192), so that the gain is adjusted in a short time. It becomes possible to optimize the output and the output, and as a whole, it becomes possible to accurately determine the presence or absence of the reflected signal and to perform the distance measuring operation in a short time and with high accuracy.

Next, an eleventh embodiment of the present invention will be described with reference to the drawings. FIG. 60 shows a common embodiment of the inventions of claims 11 and 12. The radar device of this embodiment is different from the first to tenth embodiments in that the function of the calculation storage means 6 is different. That is,
In the tenth to tenth embodiments, the binarized signal from the radar head 5 is sampled at each of the 14 sampling points in the arithmetic storage means 6 shown in FIGS. Is repeated a fixed number of times, each normalized addition value is compared with a threshold value, and if there is a sampling point exceeding the threshold value, the distance from the time delay Td corresponding to the sampling point to the target is calculated. However, in the radar device of the eleventh embodiment, the binarized signal 213 from the radar head 21 is converted into a plurality of n range blocks (that is,
Although it corresponds to the sampling points in each of the first to tenth embodiments, particularly in the following embodiments, the process of integrating every period of the sampling pulse period Δt, that is, corresponding to the sampling period) is performed a fixed number of times m. The calculation circuit 23 compares each of the normalized integrated values with a threshold value, and if there is a range block (sampling period) exceeding the threshold value, the distance from the time delay corresponding to the range block to the target is calculated. Characterize.

The structure of the eleventh embodiment will be described. As shown in FIG. 60, the radar device is broadly divided, and the transmission pulse signal 210 is repeatedly transmitted a plurality of times at a predetermined cycle toward an external target, and the reflected pulse is reflected from the target and returned from the outside. 2 after receiving signal 212 and amplifying
A radar head 21 that binarizes and outputs the binarized reception signal 213, an integration circuit 22 that integrates the binarized reception signal 213 for each of a plurality of range blocks, and repeats the integration for a predetermined m times, and the integration circuit. If there is a range block that exceeds the threshold value by comparing the integrated value 214 for each of the 22 range blocks with the threshold value, the distance corresponding to the range block is calculated, and the presence or absence of the target object and the distance to the target object are measured data. And a control circuit 24 that controls the operation of each of these circuits 21 to 23 and outputs control signals such as a trigger signal 216, an input timing signal 217, and an output timing signal 218. There is.

The radar head 21 has almost the same configuration as that of the embodiment shown in FIG. 2, receives the trigger signal 216 from the control circuit 24 a predetermined number of times at a constant cycle, and outputs the pulse signal in synchronization with each trigger signal. A transmitter 21a that outputs a transmission pulse signal 211 such as light, an ultrasonic wave, or an electromagnetic wave, a receiver 21b that receives in response to a signal 212 from the outside that is the same as this transmission pulse signal 211, and a weak reflection buried in noise. A high-gain limiting amplifier (AMP) 21c for limiting the reception signal 219 of the receiver 21b including noise in order to detect a pulse.
A zero-crossing comparator (CM) as a binarizing circuit that binarizes by discriminating whether the instantaneous value of the received signal amplified by c is larger or smaller than a predetermined reference value, for example, 0V.
P) 21d, and this comparator 21
The binarized reception signal 213 is output from d to the integration circuit 22.

The integrating circuit 22 has the structure shown in FIG.
The binarized received signal 213 is repeated m times for each of a plurality of n range blocks (sampling period) to convert the binarized received signal 213 into the range block Δt.
N input analog switches 22a-1 to 22a-n, and the binarized reception input from each of these input analog switches 22a-1 to 22a-n at their on-time. N to integrate the signal 213
N RC integrators 22b-1 to 22b-n and n for outputting the integrated value of each of these integrators 22b-1 to 22b-n
The output analog switches 22c-1 to 22c-n are provided. Input analog switch 22a-1 to 2
Each of 2a-n is switched on / off by an input timing signal 217 from the control circuit 24, and the output analog switches 22c-1 to 22c-n are switched on / off by an output timing signal 218 from the control circuit 24. It is like this.

As shown in FIG. 62, the control circuit 24 includes a clock oscillator 24a, a start pulse generating circuit 24b, a trigger generating circuit 24c and a sampling pulse generating circuit 24.
d. Each of these circuits has the same configuration as the control circuit 8 shown in FIG. However, the control circuit 24 inputs the sampling pulse signal from the sampling pulse generation circuit 24d and the trigger signal from the trigger generation circuit 24c and outputs the input timing signal 217, and the n-bit shift register 24e and the sampling pulse generation circuit 24d. An n-bit shift register 24f that outputs an output timing signal 218 in response to the end pulse signal 220 and the sampling pulse signal.

Next, the operation of the radar apparatus of the 11th embodiment will be described. Upon receiving a start command from the arithmetic circuit 23, the control circuit 24 causes the start pulse generating circuit 24
b gives the start pulse of the trigger generation circuit 24c, and the trigger generation circuit 24c repeats the trigger signal 21 m times (for example, 8192 times) at a constant cycle of, for example, 4 μs.
6 is output to the transmitter 21a of the radar head 21, and the transmitter 21a outputs a pulsed transmission signal 211 as shown in FIG. 64 each time the trigger signal 216 is input.

At the same time, the receiver 21b sends the output signal 21
1 is continuously received in response to an external signal 212 of the same kind as that of 1, and the received signal 219 is given to a limiter amplifier 21c to amplify a weak signal including noise, and further, a zero cross comparator 21d binary-receives it. The signal 213 is converted and output. That is, the zero-cross comparator 21d discriminates whether the instantaneous value of the received signal 219 is larger or smaller than a predetermined reference value, for example, 0V, and if it is smaller than the reference value, it is 0V (= "0"). If 5V (=
It is converted into a binary signal 213 of "1") and output. At this time, if the received signal 212 is only noise, the appearance probability of each of the binary values “0” and “1” is 0.5, and the probability that the value is larger than the reference value is 0. It is distributed between 5 and 1. The SN ratio and the probability of being larger than the reference value correspond one-to-one.

Further, the sampling pulse generating circuit 24d of the control circuit 24, for the n-bit shift register 24e for transmitting the input timing signal 217, synchronizes with the input of each trigger signal from the trigger generating circuit 24c.
n (eg, 14) periods of t (eg, 66.7 ns) period
Number of sampling pulses are output, the “H” state of the output terminals of Q1 to Qn is sequentially shifted for each input of each sampling pulse, and this is given to the integrating circuit 22 as an input timing signal 217.

Therefore, as shown in FIG. 63, the integrating circuit 22
Each of the input analog switches 22a-1 to 22a-n is turned on when the signal corresponding to its own switch by the input timing signal 217 is the "H" signal, and turned off when it is switched to "L" to turn on. Meanwhile, the binarized reception signal 213 is output to the integrator of the corresponding range block of the integrators 22b-1 to 22b-n, and the binarized reception signal 213 is integrated by the sampling period Δt by charging with the capacitor. To do.

Then, n input analog switches 22a
-1 to 22a-n are turned on / off once, and once one integration operation is completed, the next integration operation is repeated in synchronization with the next trigger signal, and the above integration operation is repeated by the trigger signal. Repeat for the input m times.

The sampling pulse generating circuit 24d counts the number of trigger signals, and outputs the end pulse 220 to the n-bit shift register 24f for output timing control when a predetermined m times of integration operation is completed.
The shift register 24f inputs the sampling pulse of the same period .DELTA.t from the sampling pulse generating circuit 24d to sequentially shift the "H" state of each of the output terminals Q1 to Qn, and this is output timing signal 218 as the integrating circuit 22. Give to.

Output analog switch 22 of integrating circuit 22
Each of c-1 to 22-n is turned on when the signal corresponding to its own switch in the output timing signal 218 becomes "H", and turned off when it is switched to "L". Integrated value 2 of the integrator connected to its own switch
14 are sequentially output to the arithmetic circuit 23.

When the arithmetic circuit 23 receives the integrated values of all the n integrators 22c-1 to 22c-n,
After normalizing this with the saturation voltage value of the integrator, for example, 5V, set to 1, scanning is performed for a range block that exceeds a predetermined threshold TH for identifying a noise level.

By normalizing here, if there is only noise, it becomes 0.5, and if a reflection pulse from the target is included, it will be distributed between 0.5 and 1 according to its SN ratio. Become. Therefore, as shown in FIG. 64, a range block showing a normalized integral value exceeding a threshold value (for example, a range block of #i is set. In FIG. 64, the normalized integral value is made to correspond to the center position of each range block. Although it is plotted, this is shown by plotting it in the central position for convenience in order to illustrate the integrated value in correspondence with each range block, and the integrated value of the intermediate position of each range block is actually shown. In other words, # 1 range block is 0 m, # 2 range block is 10 m, #
The 3 range block indicates the sampling period corresponding to each position of 20 m, ..., And the #i range block corresponds to each position of (i-1) m. The same applies to each timing chart below. ) Is detected, the time delay τ from the transmission timing until the reflected pulse is detected in the range block is determined by τ = Δt × i, and the distance corresponding to one range block, for example, 10 m in steps of 10 m Is multiplied by i to calculate the distance to the target, and the distance data 215 is output.

As described above, in the eleventh embodiment, the signal 21 from the outside including the reflected pulse returned by the receiver 21b reflected by the target is sent to the sent signal 211 repeatedly sent by the transmitter 21a. Receive continuously,
This is repeatedly integrated by the integration circuit 22 for each sampling period of a fixed cycle, the integrated value for each range block corresponding to each sampling period is normalized in the arithmetic circuit 23, and then compared with a threshold value TH for identifying a noise level. Then, when a range block showing an integrated value exceeding the noise level is found, the distance corresponding to the range block is calculated as the distance to the target and output. Therefore, even if noise is mixed in the received signal in a high level block, the SN ratio can be improved for the received signal in the range including the reflected pulse by repeating the integration, and the presence or absence of the reflection target can be determined. The judgment and the calculation of the distance to that point can be accurately performed.

Next, a twelfth embodiment of the present invention will be described with reference to the drawings. FIG. 65 is a block diagram showing the overall configuration of a common embodiment of the inventions of claim 11, claim 12 and claim 14. In the figure, the same parts as the eleventh embodiment, that is, the radar head 21, the integrating circuit 22, and the arithmetic circuit 2 are shown.
3, the control circuit 24 is assigned the same reference numeral as in the eleventh embodiment, and description thereof is omitted. The interference detection circuit 25 is a relative speed calculation circuit 25a and a relative speed calculation circuit 25a that calculate the relative speed with respect to the target from the passage of time for detecting the presence or absence of a reflected pulse.
A first interference wave detection circuit 25A including a relative speed abnormal value detection circuit 25b for detecting an abnormal value of the calculation result of
A second offset detection circuit 25c that detects the offset of the integrated value of the integration circuit 22 and determines the presence or absence of an interference wave.
The interference wave detection circuit 25B of FIG.

The operation of the twelfth embodiment will be described with reference to FIG.
This will be described with reference to FIGS. In these figures, however, in each of the memories M1 to M14 (= Mn), instead of the added value of the third embodiment, each range block obtained by the integrating circuit 22 and normalized in the arithmetic circuit 23 is used. It is assumed that the normalized integral value is stored.

When the sending pulse (2) is radiated to the outside, the receiver 21b continuously receives the sending signal (3) for a predetermined time from the sending timing of the sending pulse (2). Reflected by hitting the target of the receiver 21
After the elapse of (time until reaching b), the reflected pulse Rf with noise is detected. The transmission of the transmission pulse (2) and the detection of the reception signal (3) are performed in synchronization with sampling.

The time interval Δt between the adjacent sampling pulses (4) is again 6 which corresponds to a distance of 10 m, for example.
6.7 ns, 0 to 13 in 14 sampling periods
Distance shall be measured in steps of 10 m from 0 m. The integrated value of each range block corresponding to each sampling period (see FIG.
(5 to 5 are added values in FIGS. 9 to 23) are stored in the memories M1 to M14. When the integrated value (5) stored in each memory exceeds the threshold TH, it is determined that the reflected pulse is detected, and when the integrated value (5) is equal to or less than the threshold TH, it is determined that there is only noise.

Therefore, as shown in FIG. 19, when the reflected pulse Rf is detected when the integrated values of the memories M8 and M9 both exceed the threshold value TH from the total integrated values of the memories M1 to M14, the distance is close. Calculation of the distance from the distance corresponding to range block # 8 on the memory M8 side to the target (70 m in this case) is executed.

Next, a method of calculating the relative speed will be described. The reflected pulse Rf is detected in the memories M8 and M9 with respect to the received signal (3), and the time detected at the short distance M8 is t1.

When a target such as a vehicle ahead approaches the radar device (the distance is narrowed), the reflected pulse Rf moves in the direction of arrow a, and the first distance measurement time t1 The reflected pulse Rf in the memories M8 and M9.
Is detected once or several times after the distance measurement time t
2 is detected by the memories M7 and M8, the time difference between t1 and t2 is such that the reflection pulse Rf shifts the time interval Δt (corresponding to 10 m in terms of distance) of one range block. Since it is a time required to perform, the relative speed is obtained as the approach speed 10 / (t2-t1) (m / s).

On the other hand, when the reflection target is moving away from the radar device, the reflection pulse Rf moves in the direction of the arrow b, and the integrated value of the memory M8 becomes less than the threshold value TH at a certain distance measuring time t3. , The integrated value of the memory M9 is also the threshold value TH at time t4 after the reflection pulse Rf is erased.
If the disappearance of the reflection pulse Rf is observed, the time difference between t4 and t3 is the same as the reflection pulse Rf.
Is the time interval of one range block, which is the time required to shift 10 m in this case, so the exit speed is 10
The relative speed is calculated as / (t4-t3) (m / s).

For example, when approaching or leaving a stationary target at a speed of 100 (km / h), the relative speed is about 28 (m / s), and the moving time of 10 m is 10/28.
= 0.36s (= 360ms), but the reflected pulse R
As described above, the time required to detect f is 32 ms in the case of integrating 8192 times and is 1/10 or less of the moving time. Therefore, the error in the relative speed caused by the detecting time is ± 1 (m
/ S). If the relative speed is smaller than 28 (m / s), the moving time for 10 m is larger than 0.36 s, and the error becomes smaller.

A specific example of the relative velocity calculation will be described with reference to the flowchart of FIG. 20. First, the integrated value of each memory is examined in the order of the shortest distance to see if the reflected pulse Rf is detected (step 171). If the reflected pulse is detected, the detection point is set to Mn, and the detection time t1 is stored (step 172).

Next, at the next detection time, 1 is read from the memory Mn.
It is checked whether or not the reflection pulse is detected in the memory Mn-1 immediately before (step 173), and if detected, the detection time t2 at that time is calculated and the approach speed Vr1 is set to 10 / (t2.
-T1) is obtained (step 174) and output (step 175).

If no reflected pulse is detected in the memory Mn-1 in step 173, it is checked whether or not the reflected pulse in the memory Mn has disappeared. If not, step 1
Returning to step 73, the same operation is repeated at the next detection time (step 176).

At step 176, the memory Mn
If the reflected pulse of is disappeared, the detection time t3 at that time is detected.
Is stored (step 177).

Subsequently, it is checked whether or not the reflected pulse has disappeared in the memory Mn + 1. If not, step 1
Returning to step 73, the same operation is repeated at the next detection time (steps 173-178).

If the reflected pulse disappears also in the memory Mn + 1 at a certain detection time, the time t4 at that time is calculated,
The withdrawal relative speed Vr2 is obtained by 10 / (t4−t3) and is output (steps 178 to 180).

In this relative velocity detection processing, since only the detection and disappearance of the reflected pulse in the range block having the shortest distance are observed, the rising edge is sharpened as a requirement required for the transmission pulse (pulse signal irradiated to the outside). Although it is necessary, the pulse width does not need to be shortened, but rather is preferably longer than the time interval (sampling period) Δt of the range block.

That is, even in the case of only noise, the probability of exceeding the threshold value TH of the reflected pulse detection is not zero, and there is a possibility of erroneous detection at a certain value. Therefore, two or more (including continuous) range blocks are simultaneously detected. By always confirming that it is detected, the probability of false detection due to noise can be reduced.

This is equivalent to further integrating the integrated value, and when two integrated values are used, if the threshold value is the same, 3
Equivalent to getting a dB margin. Further, if the same false detection probability as that of detecting a reflected pulse with only one range block is considered, the detection threshold value can be lowered, and the detection sensitivity can be improved by 3 dB.

Next, the operation of the relative speed abnormal value detection circuit 25b and the offset detection circuit 25c which detects the offset of the integration result and determines the presence or absence of the interference wave will be described.

First, the manner of interference when the same sending pulse sent from an oncoming vehicle is received will be described. Considering the conditions to detect a stationary target by receiving a pulse signal from an oncoming vehicle that is also equipped with the same radar device when the own vehicle equipped with the radar device is stopped, The frequency of the reference clock signal used in the radar device is exactly the same, and the pulse signal from the oncoming vehicle is mixed within the time corresponding to the distance when the radar device of the own vehicle sends the pulse signal and measures the distance. This is the case.

However, since a crystal oscillator or the like having a normal frequency error is used for the reference clock signal, it is observed as a transmission pulse with a synchronization shift corresponding to the frequency error with respect to the pulse signal of the own vehicle. As a result, the measurement result of the radar device and the content of the integrated value are affected as follows by the magnitude of the frequency error.

That is, when the frequency error is 2 × 10 ⁻⁷ or less (see FIG. 21), the relative velocity is 2 × 10 ⁻⁷ × 3 × 10.
^From the relationship of ⁸ (here, 3 × 10 ⁸ is the speed of light), 60 (m /
s) It is observed as a moving target of (216 km / h) or less. In this case, it is determined whether it is a false detection due to interference or whether the target is actually moving at the observed relative speed. If this radar device is applied to a rear-end collision warning device of an automobile, a false alarm may occur.

However, the frequency error is 2 × 10 ⁻⁷ or more,
When 4.16 × 10 ⁻⁶ or less, the relative speed is 60 (m
/ S) (216 km / h) or more is observed as a moving target, and the speed is unthinkable as the actual vehicle speed, so it is possible to distinguish the relative speed as an abnormal value. Therefore, erroneous detection due to the interference wave can be prevented by monitoring the relative speed, and when the relative speed calculated by the relative speed calculation means 9a is 60 (m / s) or more, the relative speed abnormal value detection means 9b. Produces an output indicating an outlier.

The frequency error is 4.16 × 10 ⁻⁶ or more and less than or equal to the sampling processing period / distance measuring time (4 μs in the above example).
/32ms=1.25×10 ⁻⁴ or less) (see FIG. 22), when the frequency error is 4.16 × 10 ⁻⁶ or more, the interference wave is generated during the time 32 ms required for one distance measuring process. 4.1
Since 6 × 10 ^-6 × 0.032 = 133 ns or more is moved, the relative velocity is calculated by observing only the detection and disappearance of the reflection pulse in the range block with the shortest distance detecting the reflection pulse from the target. Using the method described above, the relative speed cannot be calculated, and no false alarm is issued as long as an alarm logic having two parameters of distance and relative speed is used.

Further, since it is observed over three or more range blocks having a width of 66.7 ns, the influence of the interference wave gradually appears in the entire range block as the frequency error increases, and the sampling process is performed. If the interference wave is synchronized at the start of integration at the period / distance-measuring time, that is, at 1.25 × 10 ⁻⁴ , 1.25 × 10 ⁻⁴ × 0.03 32 ms after the integration of 8192 times is completed.
2 = 4 μs, and the pulse width is 1 because it moves for a time equal to the integration repetition period (that is, the sampling period).
It is always observed in all range blocks at a time rate of 133 ns / 4 μs = 3.33% with respect to 33 ns. This is 8 in 8192 times if the SN ratio of the interference wave is sufficiently high.
An offset of the added value of 192 × 0.0333 = 273 is generated. Since the threshold value of signal detection at the time of 8192 times integration is a normalized integration value which is about the average value of noise 0.5 plus about 0.02, this offset corresponds to the threshold value, that is, 8
It is a value larger than 192 × 0.02 = 163.

When a uniform offset occurs in all range blocks, it can be identified as an interference wave by monitoring the integrated value to check whether a uniform offset has occurred. If the frequency error is 1.25 × 10 ^-4 or less, it may not be said that it is partly offset, etc., and it will not necessarily be uniform, and if there are multiple targets, observation will be made in three or more sampling periods. Therefore, the interference wave cannot be accurately detected from the offset of the integrated value.

When the frequency error is equal to or more than the sampling processing period / distance measuring time (= 1.25 × 10 ^-4 ) (see FIG. 23), a uniform offset of the integrated value is always observed, so the offset detecting means 9c It is possible to identify that there is an interference wave by the output of, and detect the integrated value due to the reflection pulse from the target that should be originally detected if it is equal to or greater than the offset. It is possible.

As described above, in order to detect the effect of the interference wave and remove it, it is effective to monitor the relative speed and to monitor that the integrated value has no offset. In the former case, if the frequency error of the reference clock is at least 2 × 10 ⁻⁷ or more, the presence of the interference wave can be detected by the magnitude of the relative speed, and the false alarm can be prevented.

In the latter case, since the detection of the offset depends on the frequency error of the reference clock signal, in order to reliably detect the interference wave, the frequency error must be detected in advance, that is, the frequency error is sampled. If it is determined that the period / distance measuring time (= 1.25 × 10 ⁻⁴ ) or more, the influence of the interference wave can be identified while dispersing the influence of the interference wave over the entire range block, and at the same time, the target can be detected. That is, in this case, a signal larger than the offset is detected, but the magnitude of the offset is 0.
Assuming that the threshold is 0333, the average of noise and the threshold of 0.5
The sum of 2 and 0.5 is added to 0.5533, which is -17d.
Signals up to B can be detected. This is 3 dB when the signal detection level when there is no interference wave is -20 dB, for example.
However, when converted to the detection distance, the sensitivity is 0.91 times as compared with the case where there is no interference wave, or 6 dB as the sensitivity decrease is 0.84 times, and the influence of the interference wave can be made extremely small. .

By thus setting the frequency error of the reference clock signal so as to disperse the influence of the interference wave over the entire range block, extremely large interference wave detection / removal can be obtained.

In this embodiment, it is possible to remove the adverse effect of the interference wave by detecting the presence or absence of the interference wave from the content of the memory in which the calculation result of the relative speed and the integrated value are stored. By appropriately selecting the frequency and its error, it is possible to control so as to minimize the adverse effect of the interference wave, and it is possible to minimize the false detection caused by the interference wave. Therefore, by using this, it is possible to realize an application system such as an inter-vehicle distance warning device for an automobile which is extremely highly reliable.

As in the conventional example, the reference clock signal 1
If the frequency is 5 MHz, the period of 66.7 ns corresponds to a distance of 10 m in the radar device, but the distance measurement error is 1% (100%).
frequency error is 10 ^-2.
Below, that is, the frequency range is from 14.85 MHz to 1
5.15 MHz is allowed. Frequency error is 1.25x
14.85MHz to 15.15 for higher than 10 ^-4
15 × 10 ⁶ × 1.25 × between 300 MHz of MHz
It suffices to allocate the frequencies so that every 10 ⁻⁴ = 1875 Hz has 160 lines. Also, the reference clock signal is not always 1
It does not have to be 5 MHz, and more frequency allocation is possible.

Next, a thirteenth embodiment of the present invention will be described with reference to the drawings. FIG. 66 shows claims 11 and 1.
FIG. 16 is a block diagram showing a configuration of a common embodiment of the invention of claim 2 and claim 15; In the figure, the same parts as those of the eleventh embodiment are designated by the same reference numerals.

The feature of this embodiment lies in the configuration of the integrating circuit, in that the first integrating circuit 22A and the second integrating circuit 22B are arranged in parallel. The first integrator circuit 22A sequentially integrates the binarized reception signal 213 with a plurality of integrators according to the input timing signal 217 'from the control circuit 24', and the eleventh embodiment shown in FIG. Example integrator circuit 2
This is exactly the same as the configuration of 2. And the second integration circuit 22
B transmits the binarized reception signal 213 when the transmitter 21a is not driven, to the input timing signal 21 from the control circuit 24 '.
7 ', which sequentially integrates a plurality of integrators,
Although only noise is iteratively integrated, the internal configuration is exactly the same as that of the first integration circuit 22A, and the difference is the control circuit 24.
It is only the input timing signal 217 'input from'.

The arithmetic circuit 23 'receives the integrated value 21 of each integrator of the first integrating circuit 22A in response to a command from the control circuit 24'.
Control circuit 24 having a function of capturing 4A, normalizing and storing the same
The integrated value 214 of the second integrating circuit 22B according to the command
A function to take in B, normalize and store it as noise level data for each range block, and a first integrating circuit 2
The normalized data of the integrated value 214A from 2A is compared with the noise level data for each range block, and when there is the integrated data exceeding the noise level, it is determined that the reflected pulse exists in the range block, and the distance to the target is determined. It is configured with a function to calculate.

The control circuit 24 'sends a predetermined number of trigger signals to the transmitter 21a for a certain period, and also suspends the operation of the transmitter 21a for a certain period (this period is the period during which the trigger signal is stopped). ) Function, this transmitter 21
The input timing signal 217 'and the output timing signal 218' are output to the first integration circuit 22A in synchronization with the trigger signal during the driving period of a, and the input timing signal 217 'and the output timing are output during the stop period of the transmitter 21a. Signal 218
′ Is output to the second integration circuit 22B, and the arithmetic circuit 23 ′ is provided with a function of calculating the noise level and detecting the reflected pulse. Then, in order to realize this function, the shift register 24 shown in FIG.
For e and 24f, change n bits to 2n bits, and set Q1
To Qn are connected to the first integrating circuit 22A, and Qn + 1 to Q2n
Is connected to the second integrating circuit 22B.

Next, the operation of the radar system of the 13th embodiment will be described with reference to FIGS. 67 to 69. First, in step 502, the counter is reset to N = 0. In steps 502 and 503, the transmitter 2
A pulse signal transmission instruction is given to 1a to transmit a transmission pulse (2), and at the same time, the binarized reception signal 219 received by the receiver 21b and binarized is integrated by the first integrating circuit 22A. At this time, the outputs of Q1 to Qn of the input shift register 24e of the control circuit 24 'are set to the first integration circuit 22A.
Input timing signal 217 'of each of the integrators 22b-1 to 22b-n, so that each of the integrators 22b-1 to 22b-n sequentially performs integration once.

Then, Q of the shift register 24e for input
When n + 1 to Q2n are sequentially output, the input timing signal 217 'is input to the second integrating circuit 22B, and each integrator of the second integrating circuit 22B sequentially receives the noise level 2 Integrate the digitized signal (step 50)
4).

When the integration is completed once in this way, the counter N is incremented by 1 and the predetermined number of repetitions m
It is determined whether or not the number of integrations has been repeated 8192 times set as (steps 505 and 506).
If not repeated 92 times, the above integration operation is repeated until the number reaches 8192 times.

At step 506, the integral is 8192.
If repeated, the control circuit 24 'supplies the output timing signals 218' of Q1 to Qn of the shift register 24f for output to the first integrator circuit 22A to cause the integrators 22b-1 to 22b-n to output. The integrated value is sequentially calculated by the arithmetic circuit 23 '
Are stored in the memories M1 to Mn for each range block (step 507).

Then, the output timing signals 218 'of Qn + 1 to Q2n of the output shift register 24f are given to the second integrating circuit 22B, and the integrated value of the noise level is sequentially calculated from the integrator 22B. Of the transmitted noise level of each range block to the memories M1 to Mn.
It is stored as H (steps 508 and 509).

Thereafter, the received data stored in each of the memories M1 to Mn is compared with the noise level (TH). If there is a range block in which the received data exceeds the noise level, it is judged that there is a reflection pulse, and The distance corresponding to the range block is calculated as the distance to the target, and the distance measurement result is output (steps 510 to 513).

When the received data of any range block does not exceed the noise level in the determination of step 510, it is determined that there is no target (step 514).

In the case of performing the above distance measuring operation, the reception level exceeding the threshold value TH set in advance is detected in the range block M6 in the same manner as described in the fourth embodiment with reference to FIG. , Therefore, it was judged that there was a target in this range block,
In this embodiment, the individual noise level is measured and set for each range block as shown by the curve CTH, and the noise level N6 of the range block M6 tends to be high. It is possible to effectively avoid erroneous detection due to noise without determining a reflected pulse.

Further, in the thirteenth embodiment, the noise level is measured immediately after each distance measuring process of the target object, but first, the sending pulse signal is sent m times to the first integrating circuit 22A. Then, the distance measurement of the target is performed, and thereafter, the sending of the sending pulse signal is stopped and the second integrating circuit 22B is made to perform the integrating operation of m times, and after these processing, the arithmetic circuit 23 '
It is also possible to adopt a configuration in which the respective integration results are transferred to and the comparison processing as shown in FIG. 30 is performed. In this case, unlike the thirteenth embodiment, the second integration circuit 22B is not provided, and the input timing signal 217 and the output timing signal 218 are set to the first timing while the operation of the transmitter 21a is stopped by the control circuit 24 '. It is also possible to adopt a configuration in which the integrating circuit 22A is used alternately for the detection of the reflected pulse and the detection of the noise.

Next, a fourteenth embodiment of the present invention will be described with reference to the drawings. FIG. 69 is a block diagram showing the configuration of another embodiment in which the inventions of claim 11, claim 12 and claim 15 are common. In the figure, the same parts as those of the thirteenth embodiment shown in FIG. 66 are designated by the same reference numerals. The drive control circuit 30 in the control circuit 24 ″ has a function of counting the number of noise level detections (for example, 8192 times) with respect to the second integration circuit 22B, and detects the noise level from the count result of the number of noise level detections. It has a function of ending and a function of instructing the second integration circuit 22B to start detection of the noise level in response to a command from the external control circuit 31.

The external control circuit 31 has a role of outputting a noise sampling start signal to the drive control circuit 30, and is the same as the external control circuit 31 shown in FIG.

In the external control circuit 31 having this configuration, the measured value change signal from the various sensors 31-2, 31-3, 31-5, the time-up signal of the timer 31-6, or the various switches 31-4, 31-. An ON switching signal of 7, 31-8 is output to the notification circuit circuit 31-1, and the notification circuit 31-1
Receives one of these signals, and the drive control circuit 30
A notification signal for notifying the start timing of noise sampling (outputting a noise sampling start signal) is output to the drive control circuit 30, and the drive control circuit 30 receives this notification signal and outputs the second integration circuit 22B in the same manner as in the thirteenth embodiment. The input timing signal 217 'is output to the terminal to perform the noise level integration.

Here, a threshold value for determining the presence / absence of outputs of the various sensors 31-2, 31-3, 31-5 and the timer 31-6 is set for the notification circuit 31-1, and the various switches 31- A function for recognizing ON-OFF of 4, 31-7, 31-8 may be set, but this is set by various sensors 31-
2, 31-3, 31-5, timer 31-6 and various switches 31-4, 31-7, 31-8 may be set.

The operation of the 14th embodiment configured as described above is executed according to the flowcharts of FIGS. 32 and 33 described in the fifth embodiment.

Thus, in the fourteenth embodiment, the illuminance sensor 31-2, the temperature sensor 31-3, and the wiper are used as the external control circuit 31 for controlling the drive control circuit 30 for controlling the presence / absence of noise sampling. Switch 3
1-4, raindrop sensor 31-5, timer 31-6, ignition switch 31-7, and manual switch 31-8
As a result, changes in weather conditions such as sunshine, temperature, and rain, changes in the operating state of mechanical parts such as the vehicle engine and alternator, and changes in power supply voltage may cause changes in the noise state due to these changes. Therefore, when any one of these changes occurs, the noise level at the time of sampling the reflection pulse of the target can be measured and the threshold value TH can be changed each time. Therefore, the normal reflected pulse of the target can be always captured, and error-free distance measurement and relative velocity of the target can be calculated.

Next, a fifteenth embodiment of the present invention will be described with reference to the drawings. FIG. 70 shows claims 13 to 1.
5 shows a common embodiment of the fifth invention. The characteristic part of this fifteenth embodiment is the configuration of the integration circuit 22 'and the control circuit 240, and the other circuits are shown in FIG.
It is the same as the eleventh embodiment shown in FIG. 0 and is shown with the same reference numerals.

As shown in FIG. 71, the integrating circuit 22 'is set to 1
It has one input analog switch 22a ', one RC integrator 22b', and one output analog switch 22c '.

Further, as shown in FIG. 72, the control circuit 240
Is a clock transmitter 24a common to the radar device of FIG.
Start pulse generation circuit 24b, trigger generation circuit 24
c, a sampling pulse generating circuit 24d and an input shift register 24e. The control circuit 240 of this embodiment is characterized by the input shift register 24.
In response to the input timing signal 217 of e, the input timing switching circuit 24g that outputs only the signal of the same sampling period as the input switching signal 27 during the sampling for each predetermined number of m times, and the integration for the predetermined number of times ends. The output timing circuit 24h outputs the output switching signal 28 when the end pulse 220 is received from the sampling generation circuit 24d. Then, this input switching signal 27 is given to the input analog switch 22a 'of the integrating circuit 22', and the output switching signal 2
8 is applied to the output analog switch 22c 'of the integrating circuit 22'.

Next, the operation of the radar apparatus of the 15th embodiment will be described with reference to the timing charts of FIGS. 73 and 74. First, the operation principle will be described. The input timing switching circuit 24g of the control circuit 240
Is the input timing signal 21 from the input shift register 24e every time the trigger signal is counted by a predetermined number m.
7 is sequentially switched from Q1 to Q2 and then to Q3, and only the signal at that timing is input to the switching signal 2
7, the input analog switch 22a of the integrating circuit 22 '
Give to ´.

In the integrating circuit 22 ', the input switching signal 27 causes the input analog switch 22a' to perform a sampling pulse period (that is, a sampling period) only in one selected sampling period in each sampling, for example, the i-th timing. Δt
During this period, it is turned on and the binarized reception signal from the radar head 21 is given to the integrator 22b ', and this operation is repeated every m times (8192 times in each of the above embodiments) sampling.

When the end pulse 220 is applied to the output timing circuit 24h after the sampling for a predetermined number of m times is completed, the output timing circuit 24h outputs the output switching signal 28. In response to this, the output analog switch 22c 'of the integrating circuit 22' is turned on, and the integrated value obtained by the integrator 22b 'is output to the arithmetic circuit 23. In the arithmetic circuit 23, the control circuit 240 Mi to specify
Stored in memory.

2 for this i-th sampling period
When the m-th integration and storage process of the binarized received signal is completed, m-th integration is similarly performed for the next i + 1-th sampling period, the result is stored, and the same operation is performed. It repeats in sequence.

Therefore, as shown in the timing charts of FIGS. 73 and 74, in the first m samplings (m = 8192 in one detection process in each of the above-described embodiments). From the input switching signal 27 from the input timing switching circuit 24g of the control circuit 240, the input switching signal 2 in which the input analog switch 22a 'of the integrating circuit 22' is synchronized with the first sampling point
7 is turned on only during the sampling pulse period Δt by 7, and the binarized reception signal is integrated m times for each sampling,
After that, the output timing circuit 24h causes the end pulse 22
By receiving 0 and giving the output timing signal 28 to the output analog switch 22c ',
The integrated value obtained in b'is output to the arithmetic circuit 23, and is stored in the memory M1 as the integrated value of the first range block.
Remember.

Next, the input timing switching circuit 24g switches the output timing of the switching signal so as to output the input switching signal 27 synchronized with the second sampling pulse of each sampling. Therefore, the input analog switch 22a ′ is turned on for the sampling period Δt by the input switching signal synchronized with the second sampling pulse in each sampling, and the binarized reception signal 213 is integrated by the integrator 22b ′. Repeated m times, and then output from the output timing circuit 24h to the analog switch 22d.
If the output timing signal 28 is input to ‘′, the integrated value obtained by the integrator 22 b ′ by that time is calculated by the arithmetic circuit 23.
Is stored in the memory M2 as the integrated value of the second range block.

Thereafter, in the same manner, every time m trigger signals are counted, the timing of opening the input analog switch 22a 'is shifted by one sampling pulse period (= sampling period) Δt, and the integrated value obtained by sampling m times is calculated. Sequentially, the memories M3, M4, ... Of the arithmetic circuit 23
To remember.

Finally, only the binarized received signal input in the nth sampling period in each sampling is integrated m times, and this is stored in the memory Mn to store each of a series of n range blocks. Sampling of the received signal at will be completed.

When the sampling is completed in this way, the arithmetic circuit 23 executes the detection of the reflection pulse Rf and the calculation of the distance from the range block where the reflection pulse Rf is detected to the target, as in the above-described embodiments. Become.

According to the circuit structure of this embodiment, the structure of the integrating circuit 22 'can be simplified and the cost merit can be realized.

As a modification of the fifteenth embodiment, a memory area corresponding to each of the memories M1 to Mn is prepared in the arithmetic circuit 23, and the series of operations described above is executed during the period during which the transmitter 21a stops the pulse transmission. If each integrated value is stored in each memory by storing each integrated value, the 13th value shown in FIGS.
As in each of the fourteenth and fourteenth embodiments, the noise level is detected for each range block and used as the threshold value for the determination of the reflection pulse Rf, which enables more accurate distance measurement of the target.

In each of the above-mentioned first to fifteenth embodiments, sampling is performed for each of a plurality of sampling periods having different time zones from the transmission timing of the transmission pulse, the binarized signal is integrated, and the integrator is saturated. If there is a range block in which the normalized integral value divided by the voltage value exceeds a predetermined threshold value TH, the distance corresponding to that point is calculated and the distance to the target is explained, but in front of the own vehicle, or If it is just to determine whether there is any obstacle on the side or rear, for example, 1 m from the own vehicle
In order to determine the presence / absence of an obstacle at a distant position, the binarized reception signal is integrated a predetermined number of times in a range block corresponding thereto, and the normalized integration value is compared with a predetermined threshold value TH or a noise level measured separately. If the received signal level is high, it can be determined that there is an obstacle, and output processing such as issuing an alarm or displaying is performed.

As a modification of the fifteenth embodiment, the number of integrations can be set to be different for each range block. That is, a signal received by a long-distance target has a low SN ratio and requires a large number of integrations.
Since the signal-to-noise ratio of the received signal from the short-distance target is high and the number of integrations is small, the number of integrations of the range block corresponding to the short distance is set small, and the number of integrations of the range block corresponding to the long distance is set large. Of. This can be realized by operating the output timing of the end pulse output from the start pulse generation circuit 24b through the sampling pulse generation circuit 24d.

Next, a sixteenth embodiment of the present invention will be described with reference to the drawings. FIG. 75 shows a common embodiment of the inventions of claims 12 to 16. In this embodiment, the same parts as the circuit configuration of the first embodiment shown in FIGS. 60 to 62 are the same. It is shown with reference numerals. That is, the radar head 21 and the radar head 2
The configuration of the integration circuit 23 that samples the binarized received signal from 1 and integrates it for each range block, the arithmetic circuit 23 that calculates the distance to the target, and the control circuit 24 that controls the operation of each circuit are common. Is. The radar head, the integrating circuit, the arithmetic circuit, and the control circuit are shown in FIGS.
The configuration shown in FIG. 70 can also be adopted.
The feature of the sixteenth embodiment is that the peak detection circuit 29 is provided. The peak detection circuit 29 that constitutes this characteristic portion is a processing function additionally incorporated as a software program of a computer that constitutes the arithmetic circuit 23.

The integrating circuit 22 compares the integrated value of each range block obtained by repeating sampling with a threshold value TH to specify a range block exceeding the threshold value TH, and when a plurality of range blocks are found, the range blocks The peak point is estimated from the magnitude relation of the integrated values of the above by an approximation process described later, and the information is passed to the arithmetic circuit 23.

The peak detection processing of the peak detection circuit 29 is almost the same as that of the peak detection means 15 shown in the eighth embodiment, and the peak points are estimated according to the timing chart shown in FIG. 76 and the flowchart shown in FIG. To do. That is, from the transmitter 21a, at least the sampling pulse period Δt (for example, 66.7n in the above embodiments).
s is used), a transmission pulse signal having a width equal to or more than one is used for one sampling processing cycle (4 in the above embodiments).
The receiver 21b continuously receives signals from the outside, amplifies them by the limiter amplifier 21c and the zero-cross comparator 21d, binarizes them, and outputs them to the integration circuit 22.

Therefore, after the sending pulse signal output from the transmitter 21a is reflected by the reflecting target and then enters the receiver 21b as a reflected pulse Rf with a time delay Td according to the distance, the integrating circuit 22 triggers. A binarized received signal is sampled and integrated for each predetermined number of, for example, 14 range blocks in each cycle. The number of times of sampling (= the number of times of outputting a trigger signal (see FIG. 3) = the number of times of transmitting a pulse) for one distance measuring operation is, for example, 8192 times in each of the above-described embodiments, and the integration processing for a predetermined number of times is performed. When is finished, it is output to the peak detection circuit 29 for each integrated value corresponding to each range block. From this integrated value output, the pulse width of the transmission pulse is set to be wider than the sampling pulse period (sampling period) Δt, so that the reflected pulse is detected in a plurality of range blocks.

Therefore, the peak detection circuit 29 is the integration circuit 2
7 receives the integral value 214 for each range block from FIG.
The peak detection processing as shown in 6 is executed, and the time delay τ from the transmission pulse transmission timing corresponding to the peak point
Is passed to the arithmetic circuit 23 as peak data 222.

This peak detection processing procedure will be described with reference to the timing chart of FIG. Note that the calculation processing procedure is the same as the flowchart of the eighth embodiment shown in FIG. 43, so refer to FIG.

First, the integral values of all range blocks (range blocks) # 1 to #n are sequentially read, the largest integral value for data exceeding the threshold value TH is set to the first peak value a1, and the next largest integral value is set to the second integral value. The range blocks p1 and p2 are specified as the peak value a2 of 2 (steps 401 to 404). Here, as shown in FIG. 76, the first peak point p1 (position of # i + 2 as a range block) is the second peak point p2 (# i + 1 as a range block).
Position), the integrated values Si + 2, Si + 1 of them are shown as a1, to show that they are peak values.
It is shown as a2.

Next, the first peak point p1 and the second peak point p
2 Determine the perspective of the distance corresponding to each (step 4
05), when the first peak point p1 is farther than the second peak point p2 at the corresponding distance, the first peak point p1 (=
The integrated value a1 (= Si + 2) of # i + 2) and the integrated value Si + 3 of the range block # i + 3 corresponding to the distance a1
And a straight line A1 (step 406a), and similarly, the integrated value a2 (= Si of the second peak point p2 (= # i + 1))
+1) and the corresponding distance Si are integrated by one step, and the integrated value Si of the range block #i is connected by a straight line A2 (step 4).
07a).

On the contrary, in the judgment of the above step 405, the first
When the peak point p1 is closer than the second peak point p2 in the corresponding distance, the integral value a1 of the first peak point p1 and the integral value of the range block in which the corresponding distance is closer by one step are drawn by a straight line. Similarly, a straight line is used to connect the integral value a2 of the second peak point p2 and the integral value of the range block corresponding to the distance a2 which is further away by one step (step 407b).

Next, the intersection a of the two straight lines A1 and A2 obtained by these processes is obtained as the peak position of the integrated value, and the time τ from the output timing of the transmission pulse to the timing corresponding to this intersection a is transmitted. The time taken from the pulse transmission timing to the reception of the reflected pulse is calculated and output to the arithmetic circuit 23 (step 408).
The arithmetic circuit 23 calculates and outputs the distance data 215 corresponding to the time τ to the peak point.

In this way, the peak detection circuit 29 approximates the received waveform of the reflected pulse Rf by the tangents on both sides near the peak point, and obtains the time τ of the peak point by the approximation method of estimating the peak point by the intersection of the tangents. , And outputs it as peak data 222 to the arithmetic circuit 23.
As a result, the arithmetic circuit 23 calculates the distance data 215 corresponding to the time τ, outputs it as needed, and issues an alarm. The operation of the arithmetic circuit 23 is the same as that of each of the above-described embodiments. Either may be used. It can also be used to detect relative speed.

Also in the sixteenth embodiment, the approximation method of the peak detection circuit is not limited to the above-mentioned example, and the time is X
Various types of quadratic curve approximation using the axis and the integrated value as the y axis and other approximation methods can be widely used.

In this way, the peak detection circuit can measure the distance with higher accuracy than the time interval Δt of the range block, and the distance measurement is possible without making the sampling pulse cycle (which corresponds to the time interval of the range block) fine. The accuracy can be improved. For example, in the embodiment shown in FIG. 75, it is possible to obtain almost 2
The distance can be measured with an accuracy within m, and the measurement accuracy is improved.

Next, a seventeenth embodiment of the present invention will be described with reference to the drawings. FIG. 77 shows a common embodiment of the inventions of claims 11-19. The feature of this embodiment is that when it is determined that the integrated value of the integrator of one of the range blocks of the integrating circuit 23 is close to the preset saturation value, the sensitivity of the device is lowered. On the contrary, when it is determined that the integrated value of the integrator of any range block does not exceed the lower limit value, the output gain adjusting circuit 33 is additionally provided in the arithmetic circuit 23 as a sensitivity adjusting means for increasing the sensitivity of the device. The same parts as those of the radar device of FIGS. 60 to 62 are provided with the same reference numerals.

The transmitter 21a 'of the radar head 21 has a variable control function of the output signal output, and the limiter amplifier 21c' for the received signal 219 received by the receiver 21b.
Has a variable gain control function (so-called AGC function), and these variable output control function and variable gain control function are controlled by the output gain adjusting circuit 33 via the control circuit 24. Controlled by signal 224. The output gain adjusting circuit 33 can be an independent circuit, but can also be configured to be incorporated as a software program in the computer forming the arithmetic circuit 23.

The transmitter 21a 'has a driving circuit 5a-1 as shown in FIG. 2 and a light emitting element 5a such as a laser diode.
-2 and a lens 5a-3 for converging the emitted light toward a target, and an output control circuit for automatically controlling the output of the output pulse thereof includes a light emitting element 5a-such as a laser diode.
A circuit such as a potentiometer is used to automatically increase or decrease the resistance value of the resistor in the output stage of the drive circuit 5a-1 in accordance with a signal from the outside in order to adjust the current to be applied to 2 or the voltage to be applied. To be In order to automatically adjust the gain, a limiter amplifier 21c 'having an AGC circuit is used.

Next, the operation of the 17th embodiment will be described. The output gain adjusting circuit 33 checks the normalized integral value obtained by dividing the integral value for each range block fetched by the arithmetic circuit 23 by the saturation voltage value of the integrator every time the distance measuring operation is completed. When the normalized integral value of the range block exceeds a preset upper limit value A, a command 223 for lowering the output of the transmission signal or / and a command 224 for suppressing the gain of the reception signal is output, and conversely each range is output. The normalized integral value for each block is checked, and any normalized integral value has a lower limit value B (usually, a threshold value TH for identifying a noise level can be used as this lower limit value).
Command 22 to increase the output of the transmission signal when it is below
3 and / or a command 224 for increasing the gain of the received signal is output.

On the other hand, when the transmitter 21a 'receives the command 223 for increasing or decreasing the output, it causes the output variable control function to operate to increase or decrease the output step by step at a preset step, and the output pulse is transmitted. To increase or decrease the intensity of each step and output.

When the limiter amplifier 21c 'receives a gain increase or decrease command 224, the limiter amplifier 21c' activates the gain variable control function to increase or decrease the gain one step at a time by a preset step, thereby increasing the strength of the received signal. Is increased or decreased step by step to output.

Even when the distance measuring operation executed after this one-time output adjustment and / or gain adjustment is completed, if the normalized integral value still exceeds the upper limit value A, further output is performed. Is repeatedly adjusted to lower the gain and / or the gain is decreased. Conversely, if the normalized integral value is still lower than the lower limit value B, the adjustment to further increase the output and / or the adjustment to increase the gain are repeated to adjust the reflected pulse reception timing. The normalized integral value of the corresponding range block is set to fall between the upper and lower limit values A and B.

Output gain adjusting circuit 3 of the seventeenth embodiment
The procedure of the automatic sensitivity adjustment processing by the series of output gain adjustments executed by the third embodiment is almost the same as that of the ninth embodiment shown in the flowchart of FIG. However, the added value in the flowchart of FIG. 48 should be read as an integrated value.

That is, first, the maximum gain and the maximum output are set to prevent an excessive gain increase or output increase (step 420). After that, the processing from step 421 onward is repeated for each normal distance measuring operation.

When one distance measuring operation is completed (step 4
21, 422), the output gain adjusting circuit 33 is the arithmetic circuit 23.
The integrated values of the respective range blocks transferred to are scanned, and it is determined whether or not there is any normalized integrated value that exceeds the upper limit value A obtained from these integrated values (step 423).
Here, as shown in FIG. 78, a range block (for example, range block #) indicating a normalized integral value exceeding the upper limit value A is displayed.
i + 1, # i + 2), since the distance measuring sensitivity is too high, the output reduction or / and gain reduction commands 223 and 224 are output to reduce the output of the transmission pulse by one step, and / or The gain of the received signal is reduced by one step, and the next distance measuring operation is performed (step 424).

If the normalized integrated value exceeding the upper limit value A is not found in the judgment of step 423, then it is judged whether or not there is a range block showing the normalized integrated value larger than the lower limit value B (step 425). Here, as shown in FIG. 79, the lower limit value B (here, it is set to the threshold value TH)
If there is no normalized integration value exceeding, the sensitivity is too low, so the above-described output increase or / and gain increase command is output to increase the output of the output pulse by one step, and / or the gain of the received signal is increased by one step. Then, the next distance measuring operation is performed (step 426).

In the above steps 421 to 426, the normalized integral value of any range block does not exceed the upper limit value A, and the normalized integral value of any range block is the lower limit value B.
The above process is repeated until the distance measuring sensitivity is automatically adjusted.

When the automatic adjustment of the sensitivity is completed by the above procedure, the arithmetic circuit 23 thereafter executes the original distance calculation processing (step 427).

By performing the automatic sensitivity adjustment in this way, it becomes possible to achieve both distance measurement of a reflection target at a long distance and distance measurement of a reflection target at a short distance. For example, if a large output signal output corresponding to the distance measurement of a long-distance reflective target and a large gain are fixed and an attempt is made to measure a short-distance reflective target, the range block # i + 1, The normalized integral value of # i + 2 exceeds the upper limit value and reaches the saturation voltage value S, which makes it impossible to measure the distance at the existing position of the target. On the other hand, if the output of a small transmission signal corresponding to the distance measurement of a short-distance reflection target and a small gain are fixed and the distance of a long-distance reflection target is measured, the range block # i + in FIG.
Like the normalized integral value of 1, # i + 2, the threshold value TH cannot be exceeded even though the target is actually detected, and detection cannot be performed. Therefore, if the sensitivity adjustment function is activated according to the procedure described above, the reflected pulse can always be received and distance-measured at the optimum reception intensity regardless of whether the target object is in the near or far position. The reliability can be improved.

The automatic sensitivity adjusting function is not limited to the above-described embodiment, and the first several steps of the sensitivity adjusting are performed by the gain control, and when it is still insufficient, the procedure is performed by the output control. , Or vice versa. Further, in order to simplify the circuit structure, the sensitivity can be adjusted only by the gain control function or the output control function.

As a modification of the seventeenth embodiment, the structure shown in FIG. 80 may be used. That is,
The radar apparatus having the peak detecting circuit 29 of the sixteenth embodiment shown in FIG. 75 is further provided with the above-mentioned output gain adjusting circuit 33.

In this way, when the output gain adjusting circuit 33 is not provided as shown in FIG. 81 (a), the normalized integral value of either range block #i, # i + 1 becomes the saturation value S. When the peak position is reached, even if the peak position p is detected by the peak detection circuit 29, the peak position r of the actual received signal is reached.
According to this modification, the normalized integral value of any range block can be set to the upper limit value A or less by automatic sensitivity adjustment as shown in FIG. 81 (b). Therefore, the peak position p can be accurately detected, and the distance measurement accuracy can be further improved.

Next, an eighteenth embodiment of the present invention will be described with reference to the drawings. FIG. 82 shows a common embodiment of the inventions of claims 11 to 17 and claim 20. The feature of this embodiment is that when it is determined that the normalized integral value of the integrator of one of the range blocks of the integrating circuit 22 exceeds the upper limit value set in advance for adjusting the number of integration, the number of integration is set. When it is determined that the normalized integration value of the integrator of any range block does not exceed the lower limit value set in advance for adjusting the number of integrations, the number of integrations adjustment circuit 34 increases the number of integrations. Is provided as the sensitivity adjusting means, and the other portions are the same as those of the radar device shown in FIGS. 60 to 62 and are denoted by the same reference numerals. Also in this embodiment, the number-of-integration adjustment circuit 34 may be incorporated in the computer forming the arithmetic circuit 23 as a software program.

Explaining the function of the integration number adjusting circuit 34, the normalized integral value obtained by dividing the integral value of each range block of the integrating circuit 22 by the integral saturation voltage value is calculated every time the distance measuring operation is completed. Is checked, and the normalized integral value of one of the range blocks is the upper limit value A that is set in advance.
When it exceeds ′, a command for reducing the number of integrations m repeated in one distance measuring operation (in the above-described embodiments, the number of integrations is described as 8192) is output, and conversely each range block is output. The sampling pulse generation circuit of the control circuit 24 checks the normalized integration value for each of the sampling pulse generation circuits, and if any of the normalized integration values is below the lower limit value B ′, increases the number of integrations repeated in one distance measuring operation. Output to 24d.

On the other hand, the sampling pulse generation circuit 24d counts the number of trigger signals received from the trigger generation circuit 24c and is set in advance (this is the same as the variably set number of additions).
The output timing of the end pulse that is output when the
Adjustment is made to decrease or increase in steps. As a result, the number of integrations of the integration circuit 22 is adjusted to be increased or decreased.

Then, even when the distance measuring operation executed after the adjustment of the number of integrations is completed, if the normalized integrated value still exceeds the upper limit value A ', the number of integrations is further reduced. On the contrary, if the normalized integral value is still below the lower limit value B ′, the adjustment for further increasing the integral number is repeated.

The automatic sensitivity adjustment processing procedure by the series of integration times adjustment described above will be described with reference to the flowchart of FIG. 55 showing the operation of the tenth embodiment. Note that the added value in the flowchart of FIG. 55 is to be read as an integrated value.

First, the integration number m is set to a standard number, for example, 0 to 13 as illustrated in each of the above embodiments.
There are 14 range blocks for sampling every 10 m between 0 m, and the sending cycle of the sending pulse which is also one sampling processing cycle is 4 μs, and the sampling pulse cycle Δt (this is also the sampling period of each range block. ) Is 66.7 ns, 8192
The number of times of integration is set (step 430).

When a certain distance measuring operation is completed (steps 431 and 432), the integration number adjusting circuit 34 scans the integrated value of each range block of the integrating circuit 22 and normalizes the integrated value obtained from those integrated values. The integrated value is the upper limit A '
It is determined whether or not there is a range block exceeding (step 433). Here, a range block (for example, range block # i +) indicating a normalized integral value exceeding the upper limit value A ′ is displayed.
If 1, # i + 2) is present, a command for advancing the output timing of the end pulse by one step is output to the sampling pulse generating circuit 24d to decrease the number of integrations of the integrating circuit 22 by one step, and the next distance measuring operation. Is performed (step 434).

If the normalized integral value exceeding the upper limit value A'is not found in the judgment of step 433, then the lower limit value B '
It is determined whether or not there is a range block showing a larger normalized integral value (step 435). Here, if there is no normalized integration value exceeding the lower limit value B ', a command for delaying the output timing of the end pulse by one step is output to the sampling pulse generation circuit 24d to increase the integration number of the integration circuit 22 by one step. Then, the next distance measuring operation is performed (step 436).

In the above steps 431 to 436, the normalized integral value of any range block does not exceed the upper limit value A ',
Further, it is repeated until the normalized integral value of any of the range blocks becomes equal to or more than the lower limit value B ', whereby the number of integrals can be determined to be the minimum necessary and have a sufficient SN ratio, and the target can be discriminated and the distance measurement operation can be performed. Is adjusted automatically.

When the automatic adjustment of the number of integrations is completed by the above procedure, the arithmetic circuit 23 thereafter executes the original distance calculation processing (step 437).

By thus adjusting the number of automatic integrations, the presence or absence of the target can be determined and the distance measuring operation can be performed with a sufficient SN ratio with the minimum necessary number of integrations. In distance measurement (at a short distance, it is necessary to shorten the distance measurement time as much as possible so that a quick response can be made), the distance can be measured with a small number of integrations and the processing speed is increased. You will be able to speed up.

As a modification of the eighteenth embodiment, the structure shown in FIG. 83 may be used. That is,
The radar apparatus having the peak detecting circuit 29 of the sixteenth embodiment shown in FIG. 75 is further provided with the above-mentioned integration number adjusting circuit 34.

In this way, the peak position p can be accurately detected by first performing the distance measurement after automatically adjusting the optimum number of integrations and performing the peak detection by the peak detection circuit 29. The distance measuring operation can be speeded up.

As an embodiment in which the seventeenth embodiment and the eighteenth embodiment are combined, as an automatic sensitivity adjustment function, the output signal output is automatically adjusted, the amplification gain of the received signal is automatically adjusted, and A configuration including all automatic adjustments is also possible.

The processing procedure in this case will be described below. First, perform sampling integration processing 1024 times,
If there is a sampling point exceeding the upper limit value A at that time, the gain of the receiving means is reduced, and / or the transmission output of the transmitting means is reduced. In addition, when the integral value of any sampling period does not exceed the lower limit value after the sampling integration is performed 1024 times, the gain of the receiving unit is increased or / and the transmission output of the transmitting unit is increased. Thereby, the optimum SN ratio can be obtained.

When the sampling integrated value falls within the range between the upper limit value and the lower limit value, the integration value is set to 8192 times so that an integrated value with less variation can always be obtained. The normal operation for determining the presence / absence is performed. The number of integrations is set to 7
It may be 168 times (= 8192-1024).

In this way, first, the gain adjustment control and the output adjustment control are performed with a small number of integrations, which is a small fraction of the predetermined number of integrations (8192), so that the gain is adjusted in a short time. It becomes possible to optimize the output and the output, and as a whole, it becomes possible to accurately determine the presence or absence of the reflected signal and to perform the distance measuring operation in a short time and with high accuracy.

Also, in the above, sampling integration is performed 1024 times, and if the integration value of any sampling period exceeds the upper limit value at that time, the gain of the receiver is reduced or / and the transmitter is If the integrated value of any sampling period does not exceed the upper limit value, directly set the number of integration times to 8192 so that an integrated value with less variation can always be obtained. After that, the normal operation of determining the presence / absence of the reflected signal is performed. The number of integrations is set to 7168.
The number of times (= 8192-1024) may be sufficient.

Also in this case, the gain adjustment control and the output adjustment control are first performed with a small number of integrations, which is a fraction of the predetermined number of integrations (8192 times), so that the gain is adjusted in a short time. It becomes possible to optimize the output and the output, and as a whole, it becomes possible to accurately determine the presence or absence of the reflected signal and to perform the distance measuring operation in a short time and with high accuracy.

Next, an example of using the radar device of each of the above-mentioned embodiments will be described. FIG. 84 shows a vehicle collision warning device using a radar device. The radar device 100, various sensors 110 such as a vehicle speed sensor 110a, a steering angle sensor 110b, a relative speed calculation circuit 120, and a calculation control circuit 13 are shown.
0 and the output device 140.

In this collision warning system, the radar system 100
The relative speed to the preceding vehicle is obtained by time-differentiating the distance output obtained from the distance measurement operation repeatedly executed by the relative speed calculation circuit 120, and the calculation control circuit 130
The distance data (which is the inter-vehicle distance) and the relative speed data are output to.

The arithmetic control circuit 130 receives these data and signals such as the vehicle speed and the steering angle from the various sensors 110 and calculates the possibility that the vehicle may collide with the preceding vehicle, so that the inter-vehicle distance is short. If the relative speed exceeds a predetermined value, it is judged that there is a risk of collision and the display 1
An output device 140 such as 40a and a speaker 140b gives a warning to the driver to prevent a collision.

In the case of a collision warning device, when the distance to the preceding vehicle reaches the safe inter-vehicle distance, the output device 140 may be provided with a display for notifying it, a speaker output, and a lamp display.

Next, an on / off control device for a constant speed traveling device using the radar device of each of the above embodiments will be described with reference to FIG. In this device, in addition to the device of FIG. 84, the arithmetic control circuit 130 is connected to the constant speed traveling device 150, and the throttle actuator 151 is controlled by the constant speed traveling device 150. When the driver inputs a desired vehicle speed and turns on the switch, the constant speed traveling device 150 adjusts the opening / closing degree of the throttle actuator 151 to perform constant speed traveling control at the desired vehicle speed.

Therefore, when the constant-speed traveling device 150 attempts to perform constant-speed automatic traveling, the arithmetic control circuit 130
Then, when the distance data from the relative speed calculation circuit 120 and the relative speed data with respect to the preceding vehicle and the signals from the various sensors 110 are received, the degree of approach of the own vehicle to the preceding vehicle is calculated, and it is determined that the vehicle is too close. Outputs to the output device 140 to notify the driver, outputs an OFF signal to the constant speed traveling device 150 to stop the automatic constant speed traveling, and closes the throttle valve by the throttle actuator 151 to decelerate the vehicle. Make sure to keep the distance between cars. When the relative speed is large on the minus side and the inter-vehicle distance is large, an ON signal is output to the constant speed traveling device 150 to operate the automatic constant speed traveling. As a result, even if the constant speed traveling control is performed by the constant speed traveling device, it can be immediately notified when the inter-vehicle distance becomes short.

Next, the collision prevention device shown in FIG. 86 will be described. This collision prevention device is particularly suitable for the arithmetic control circuit 13
When 0 determines the risk of collision from the relationship between the inter-vehicle distance and the relative speed, various actuators 155 are differentially operated to automatically prevent the collision. That is,
Brake actuator, throttle actuator,
The arithmetic control circuit 130 can access various actuators 155 such as a speed change actuator.
If the relative speed is large and the inter-vehicle distance tends to be shortened, the deceleration actuator of the various actuators 155 is differentially operated to apply the engine brake, and the operation to access the brake actuator and apply the brake is automatically performed. To do.

Next, the pre-crash airbag system will be described with reference to FIG. This pre-crash airbag system includes a radar device 100, a relative velocity calculation circuit 120, and a calculation control circuit 130. The calculation control circuit 130 accesses the airbag device 160 to perform the airbag at the earliest possible timing. It is possible to expand.

That is, since the normal airbag device starts the operation of inflating the airbag for the first time by the impact of the collision shown at the timing t0 in FIG. It may come into contact with the face (see curve a).

However, in this pre-crash airbag system, the radar device 100 constantly repeats the distance measuring operation, and the relative speed calculation circuit 120 calculates the relative speed and the inter-vehicle distance with respect to the preceding vehicle each time and the calculation control circuit. 1
You have entered 30.

The arithmetic and control circuit 130 constantly monitors the relative speed and the inter-vehicle distance data, and if it judges that both the own vehicle speed and the relative speed are large and the inter-vehicle distance becomes short just before the collision. , And outputs an operation command to the airbag device 160 at the timing t−. As a result, as shown in FIG. 88, at the time point t0 when the actual collision occurs, the airbag is in a fully inflated state, and it becomes possible to secure a quick activation of the device.

[0405]

As described above, according to the invention of claim 1,
Even if the reflected signal returned from the target and reflected from the target signal is weak, the reflected signal has a high SN ratio that can be distinguished from a predetermined threshold value indicating the noise level by repeatedly adding the binarized received signal. Can be detected, and the presence or absence of the target can be accurately detected.

According to the second aspect of the present invention, the corresponding distance is calculated by finding the sampling point showing the added value larger than the predetermined threshold value, and the distance to the external target is automatically calculated. The distance to the target can be measured accurately.

According to the third aspect of the invention, the addition portion of the binarized signal can be made one, the circuit configuration can be simplified, and the cost can be improved.

According to the fourth aspect of the invention, the interference wave detecting means for detecting the interference wave included in the reflected signal received by the receiving means, and the interference wave removing means for removing the interference wave detected by the interference wave detecting means. By including the means, even when interference is generated by a similar signal transmitted from the radar device mounted on the vehicle of the other party as an external target,
The interference wave can be detected, and the influence of the interference wave can be removed from the calculation result by the adding means, and the presence or absence of the external target and the distance to the target can be calculated without error.

According to the fifth aspect of the present invention, since the added value for the noise at each sampling point is sampled and the added value of the noise sampled for each sampling point is used as the threshold value for each sampling point, each sampling point is used. In addition, the influence of noise can be reliably removed to determine the presence or absence of the target, and the distance to the target can be calculated, which enables accurate determination.

According to the invention of claim 6, when the added value of the plurality of sampling points shows a value larger than a predetermined threshold value, an approximated curve is obtained by connecting the plurality of added values with a predetermined approximate expression, Since the distance is calculated by obtaining the time delay from the signal transmission timing corresponding to the peak position of this approximate curve, even if the target exists at the distance point corresponding to the intermediate position between the adjacent sampling points, The distance can be calculated in detail, and more accurate distance measurement can be performed even with coarse sampling point intervals.

According to the seventh aspect of the invention, when it is determined that the added value of any of the sampling points exceeds the upper limit value, the sensitivity of the apparatus is adjusted to be lowered, and conversely, the addition of any of the sampling points is performed. When it is determined that the value does not exceed the lower limit value, the sensitivity of the device is adjusted so that the level of the added value can always be maintained at an appropriate level, and it is possible to accurately determine the presence or absence of the target. Also, the distance to the target can be calculated stably.

According to the eighth aspect of the invention, since the output adjusting means of the sending pulse of the sending means is used as the sensitivity adjusting means, the level of the added value is always maintained at an appropriate level by adjusting the output of the sending pulse. Therefore, the presence or absence of the target can be accurately determined, and the distance to the target can be stably calculated.

According to the radar apparatus of the ninth aspect of the invention, since the means for adjusting the amplification gain of the received signal is used as the sensitivity adjustment means, the level of the added value is always adjusted to an appropriate level by adjusting the amplification gain of the received signal. Therefore, it is possible to stably determine the presence or absence of the target and to stably calculate the distance to the target.

According to the tenth aspect of the invention, since the addition number adjusting means of the adding means is used as the sensitivity adjusting means,
The number of times of addition by the adding means is set to a minimum necessary minimum number and automatically set so that a reflected signal can be detected with a sufficient SN ratio, and it is possible to determine the presence or absence of a target or speed up the distance measuring operation. it can.

According to the eleventh aspect of the present invention, the noise level is indicated by repeatedly integrating the binarized received signal even if the reflected signal returning from the target with respect to the transmitted signal is weak. The reflected signal can be detected with a high SN ratio that can be discriminated from a predetermined threshold value, and the presence or absence of the target can be accurately detected.

According to the twelfth aspect of the present invention, the corresponding distance is calculated by finding the sampling period showing the integral value larger than the predetermined threshold value, and the distance to the external target is automatically calculated. The distance to the target can be measured accurately.

According to the thirteenth aspect of the present invention, the number of integration circuits of the binarized signal can be reduced to one, the circuit configuration can be simplified, and the cost can be improved.

According to the fourteenth aspect of the invention, the interference wave detecting means for detecting the interference wave contained in the reflected signal received by the receiving means, and the interference wave removing means for removing the interference wave detected by the interference wave detecting means. By including the means, even if interference occurs due to a similar signal transmitted from the radar device mounted on the vehicle of the other party, which is an external target, the interference wave is detected and the integration means is used. The influence of the interference wave can be removed from the calculation result, and the presence or absence of the external target and the distance to the target can be calculated without error.

According to the fifteenth aspect of the present invention, since the integrated value for noise in each sampling period is sampled and the integrated value of noise for each sampling period is used as the threshold for each sampling period, the noise for each sampling period is used. It is possible to reliably remove the influence of the above and determine the presence or absence of the target, and also to calculate the distance to the target, which enables an accurate determination.

According to the sixteenth aspect of the invention, when the integrated values of the plurality of sampling periods show a value larger than a predetermined threshold value, an approximate curve is obtained by connecting the plurality of integrated values with a predetermined approximate expression, Since the distance is calculated by obtaining the time delay from the signal transmission timing corresponding to the peak position of this approximate curve, even when the target is present at the distance point corresponding to the intermediate position between the adjacent sampling periods, The distance can be calculated finely, and highly accurate distance measurement can be performed even if the sampling pulse period is roughly set.

According to the seventeenth aspect of the invention, when it is determined that the integrated value of any sampling period exceeds the upper limit value, the sensitivity of the apparatus is adjusted to be lowered, and conversely, the integration of any sampling period is performed. When it is determined that the value does not exceed the lower limit value, the sensitivity of the device is adjusted so that the level of the integrated value can be maintained at an appropriate level at all times, and it is possible to accurately determine the presence or absence of the target. Also, the distance to the target can be calculated stably.

According to the eighteenth aspect of the invention, since the output adjusting means of the sending pulse of the sending means is used as the sensitivity adjusting means, the output level of the sending pulse is always adjusted so that the level of the integrated value is maintained at an appropriate level. Therefore, the presence or absence of the target can be accurately determined, and the distance to the target can be stably calculated.

According to the radar device of the invention of claim 19,
Since the means for adjusting the amplification gain of the received signal is used as the sensitivity adjustment means, the level of the integrated value can always be maintained at an appropriate level by adjusting the amplification gain of the received signal, and it is possible to accurately determine the presence or absence of the target. Moreover, the distance to the target can be calculated stably.

According to the twentieth aspect of the invention, since the integration number adjusting means of the integrating means is used as the sensitivity adjusting means,
By automatically adjusting the increase / decrease of the number of integrations of the integrator so that the reflected signal can be detected with a sufficient SN ratio with the minimum number of integrations required, the presence / absence of a target is determined or the distance measurement operation is speeded up. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the first embodiment.

FIG. 3 is a timing chart of various signals used in the first embodiment.

FIG. 4 is a graph showing a result of calculating a probability distribution of an integral value k represented by equation (3).

FIG. 5 is a block diagram showing a configuration of a start pulse generating circuit (addition number setting circuit).

FIG. 6 is a block diagram showing a configuration of a trigger generation circuit.

FIG. 7 is a block diagram showing a configuration of a sampling pulse generation circuit.

FIG. 8 is a block diagram showing a configuration of an addition clock generation circuit that is a component of a timing circuit.

FIG. 9 is a block diagram showing a configuration of a control pulse generation circuit which is another component of the timing circuit.

FIG. 10 is a timing chart of various signals of the control pulse generation circuit.

FIG. 11 is a block diagram showing a configuration of a sampling / adding circuit.

FIG. 12 is a timing chart showing an addition processing operation.

FIG. 13 is a flowchart showing the operation of the determination means.

FIG. 14 is a distribution chart when the data distribution of Na = 128 times is repeated 2000 times to obtain the frequency distribution (probability distribution) of the integrated value.

FIG. 15 is a distribution chart showing a calculation result of a normalized expected value k ′ / Na of k and a range of 3σ when Na = 8192.

FIG. 16 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 17 is a timing chart of the second embodiment.

FIG. 18 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 19 is an explanatory diagram illustrating a specific example of detection of a reflected pulse and calculation of a relative speed.

FIG. 20 is a flowchart showing a specific example of relative velocity calculation.

FIG. 21 is an explanatory diagram illustrating a specific example of processing of an interference wave.

FIG. 22 is an explanatory diagram illustrating a specific example of processing of an interference wave.

FIG. 23 is an explanatory diagram illustrating a specific example of processing of an interference wave.

FIG. 24 is a block diagram showing a configuration of a modified example of the third exemplary embodiment.

FIG. 25 is a flowchart showing an operation of a former stage of the modified example of the third exemplary embodiment.

FIG. 26 is a flowchart showing an operation of a latter stage of the modified example of the third exemplary embodiment.

FIG. 27 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 28 is a flowchart showing the operation of the first stage of the fourth embodiment.

FIG. 29 is a flowchart showing a second-stage operation of the fourth exemplary embodiment.

FIG. 30 is an explanatory diagram showing a specific example of threshold setting based on a noise level.

FIG. 31 is a block diagram showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 32 is a flow chart showing the operation of the first stage of the fifth embodiment.

FIG. 33 is a flow chart showing the operation of the latter stage of the fifth embodiment.

FIG. 34 is a block diagram showing a configuration of a sixth exemplary embodiment of the present invention.

FIG. 35 is a flowchart showing the operation of the first stage of the sixth embodiment.

FIG. 36 is a flow chart showing the operation of the middle part of the sixth embodiment.

FIG. 37 is a flowchart showing an operation of a latter stage of the sixth embodiment.

FIG. 38 is a block diagram showing the configuration of the seventh exemplary embodiment of the present invention.

FIG. 39 is a timing chart showing the sampling operation of the seventh embodiment.

FIG. 40 is a timing chart showing the sampling operation of the seventh embodiment.

FIG. 41 is a block diagram showing the configuration of the eighth exemplary embodiment of the present invention.

FIG. 42 is a timing chart of the eighth embodiment.

FIG. 43 is a flowchart showing the operation of the eighth embodiment.

FIG. 44 is an explanatory diagram of an approximation method of the eighth example.

FIG. 45 is a graph showing the ranging accuracy of the eighth embodiment.

FIG. 46 is a block diagram showing a configuration of a ninth exemplary embodiment of the present invention.

FIG. 47 is a block diagram showing a specific circuit configuration of the ninth embodiment.

FIG. 48 is a flowchart showing the operation of the ninth embodiment.

FIG. 49 is an explanatory diagram showing an output gain reducing operation of the ninth embodiment.

FIG. 50 is an explanatory diagram showing an output gain increasing operation of the ninth embodiment.

FIG. 51 is a block diagram showing a configuration of a modified example of the ninth exemplary embodiment.

FIG. 52 is an explanatory diagram showing an output gain adjustment and a peak detection operation of a modified example of the ninth embodiment.

FIG. 53 is a block diagram showing the structure of the tenth embodiment of the present invention.

FIG. 54 is a block diagram showing a specific circuit configuration of the tenth embodiment.

FIG. 55 is a flowchart showing the operation of the tenth embodiment.

FIG. 56 is an explanatory diagram showing reduction adjustment of the number of additions according to the tenth embodiment.

FIG. 57 is an explanatory diagram showing increase adjustment of the number of additions according to the tenth embodiment.

FIG. 58 is a block diagram showing the configuration of a modified example of the tenth exemplary embodiment of the present invention.

FIG. 59 is an explanatory diagram showing an operation of adjusting the number of times of addition in a modification of the tenth embodiment.

FIG. 60 is a block diagram showing the structure of an eleventh embodiment of the present invention.

FIG. 61 is a block diagram showing the structure of the integrating circuit of the eleventh embodiment.

FIG. 62 is a block diagram showing the structure of the control circuit of the eleventh embodiment.

FIG. 63 is a timing chart showing the operation of the integrating circuit of the eleventh embodiment.

FIG. 64 is a timing chart showing the distance measuring operation of the eleventh embodiment.

FIG. 65 is a block diagram showing the structure of a twelfth embodiment of the present invention.

FIG. 66 is a block diagram showing the structure of the thirteenth embodiment of the present invention.

FIG. 67 is a flow chart showing the first stage of the operation of the thirteenth embodiment.

FIG. 68 is a flowchart showing a latter stage of the operation of the thirteenth embodiment.

FIG. 69 is a block diagram showing the structure of the fourteenth embodiment of the present invention.

FIG. 70 is a block diagram showing the structure of a fifteenth embodiment of the present invention.

71 is a block diagram showing the structure of an integrating circuit of the fifteenth embodiment. FIG.

FIG. 72 is a block diagram showing the structure of the control circuit of the fifteenth embodiment.

FIG. 73 is a timing chart showing the sampling operation of the fifteenth embodiment.

FIG. 74 is a timing chart showing the sampling operation of the fifteenth embodiment.

FIG. 75 is a block diagram showing the structure of a sixteenth embodiment of the present invention.

FIG. 76 is an explanatory diagram showing a peak point approximation method according to the sixteenth embodiment;

77 is a block diagram showing a configuration of a seventeenth exemplary embodiment of the present invention. FIG.

FIG. 78 is an explanatory diagram showing an output gain reducing operation of the seventeenth embodiment.

FIG. 79 is an explanatory diagram showing an output gain increasing operation of the seventeenth embodiment.

FIG. 80 is a block diagram showing the configuration of a modified example of the seventeenth embodiment of the present invention.

FIG. 81 is an explanatory diagram showing a sensitivity adjustment and a peak point detection operation of a modified example of the seventeenth embodiment.

FIG. 82 is a block diagram showing the structure of an eighteenth embodiment of the present invention.

FIG. 83 is a block diagram showing the configuration of a modified example of the eighteenth embodiment of the present invention.

FIG. 84 is a block diagram showing the configuration of a collision prevention device to which the radar device of the present invention is applied.

FIG. 85 is a block diagram showing the configuration of another example of the collision prevention device to which the radar device of the present invention is applied.

FIG. 86 is a block diagram showing the configuration of still another example of the collision prevention device to which the radar device of the present invention is applied.

FIG. 87 is a block diagram showing a configuration of a pre-crash airbag system to which the radar device of the present invention is applied.

FIG. 88 is an explanatory diagram showing an operation of the pre-crash airbag system.

FIG. 89 is a block diagram showing a configuration of a conventional radar device.

FIG. 90 is a timing chart of various conventional signals.

FIG. 91 is a graph showing a conventional noise probability distribution.

[Explanation of symbols]

 5 radar head 5a pulse signal sending means 5b reflected pulse signal receiving means 5a-1 first drive circuit 5a-2 light emitting element 5a-3 lens 5a-4 output control circuit 5a'-1 second drive circuit 5a'-2 Light emitting element 5a'-3 lens 5b-1 lens 5b-2 light receiving element 5b-3 limiter amplifier 5b-4 zero cross comparator 5b-5 gain control circuit 6,6 'addition storage means 6a sampling means 6b first addition storage means 6c Second addition storage means 6a Timing circuit 6b Sampling / addition circuit 6b-2 to 6b-3 8-bit shift register 6b-8 to 6b-9 Memory 6b-11 to 6b-14 Bidirectional buffer 6b-17 to 6b-20 Preset counter for addition 6'-1 Gate timing switching circuit 6'-2 Counter 6'-3 Input gate Path 6'-4 Addition storage circuit 6'-5 Output gate circuit 6'-6 Memory 6'-7 Memory switching circuit 7, 7 ', 7 "Judgment means 8, 8', 8" Control means 8a Clock transmitter 8b Start pulse generation circuit (addition number setting circuit) 8c Trigger generation circuit 8d Sampling pulse generation circuit 9 Interference detection means 9a Relative speed calculation means 9b Relative speed abnormal value detection means 9c Offset detection means 12 Relative speed detection counter 13 False detection prevention means 14 Relative velocity calculating means 15 Peak detecting means 16 Sensitivity adjusting means 17 Output gain adjusting circuit 18 Addition number adjusting means 19 Addition number adjusting circuit 20, 20 ', 20 "Drive control means 21, 210 Radar head 21a, 21a' Transmitter 21b Receiver 21c, 21c 'Limiter amplifier 21d Zero cross comparator 22 Integration times 22a-1 to 22a-n input analog switch 22b-1 to 22b-n integrator 22c-1 to 22c-n output analog switch 22a 'input analog switch 22b' integrator 22A first integration circuit 22B second integration circuit 22c 'Output analog switch 23, 23', 23 "Arithmetic circuit 24, 24 ', 240 Control circuit 24a Clock oscillator 24b Start pulse generation circuit 24c Trigger generation circuit 24d Sampling pulse generation circuit 24e Shift register 24f Shift register 24g Input timing switching Circuit 24h Output timing circuit 29 Peak detection circuit 31 External control circuit 31-1 Notification circuit 31-2 Illuminance sensor 31-3 Temperature sensor 31-4 Wiper switch 31-5 Raindrop sensor 31-6 Timer 31-7 Ignition Switch 31-8 manual switch 33 outputs a gain adjustment circuit 34 integration count adjustment circuit 41 shutter 51 switching circuit

Claims (20)

[Claims] 1. A sending means for periodically outputting a pulsed signal to the outside, and a receiving means for continuously receiving a signal from a direction in which the signal output by the sending means is reflected by a target. The binarizing means for binarizing the signal received by the receiving means, and the binarizing means for each sampling point at which one or more fixed times after the sending timing of the sending means are different Sampling means for sampling the binarized signal; one or a plurality of adding means for adding the sampling value for each sampling point by the sampling means by a predetermined number of times the signal is sent by the sending means; and each of the adding means. The normalized addition value obtained by normalizing the addition value is compared with a predetermined threshold value, and determination means for determining whether or not there is a reflection signal from an external target based on the magnitude of the comparison value is provided. Over da apparatus. 2. The radar device according to claim 1, further comprising a value greater than the predetermined threshold value after the transmission timing of the transmission means when the determination means determines that a reflection signal from an external target exists. A radar apparatus comprising: distance calculating means for calculating a distance to an external target based on a time delay to a sampling point corresponding to an adding means for giving a normalized added value. 3. Sending means for periodically outputting a pulsed signal to the outside, and receiving means for continuously receiving signals from the direction in which the signal output by the sending means is reflected by a target, Binarizing means for binarizing the signal received by the receiving means, and sampling means for sampling the binarized signal output by the binarizing means at a predetermined sampling point after the sending timing of the sending means. A sampling value at a predetermined sampling point by the sampling means is added by a predetermined number of times the signal is sent by the sending means; and a plurality of kinds of sampling points of the sampling means are set at different times, When the adding means finishes the adding operation for the predetermined number of times of transmission at one sampling point,
Sampling timing switching means for sequentially switching to another sampling point to cause the adding means to perform addition operation, storage means for storing the added value of the adding means in association with each of a plurality of types of sampling points, and the storage means Judgment is made by comparing each normalized addition value obtained by normalizing the addition value corresponding to each sampling point to be stored with a predetermined threshold value, and based on the magnitude, whether or not there is a reflection signal from an external target. Means and the determination means determines that a reflection signal from an external target is present, after the sending timing of the sending means, a time delay to a sampling point at which an added value larger than the predetermined threshold value is obtained. A radar device comprising a distance calculating means for calculating a distance to an external target based on the distance calculating means. 4. An interference wave detecting means for detecting an interference wave included in a reflected signal received by the receiving means, and an interference wave removing means for removing an interference wave detected by the interference wave detecting means. The radar device according to any one of claims 1 to 3, which is formed. 5. The determination means is provided with another one or a plurality of addition means for adding a sampling value for noise received by the reception means a predetermined number of times at the same sampling point during a period in which the transmission means does not transmit a signal. 5. The radar device according to any one of claims 1 to 4, wherein each normalized addition value obtained by normalizing the addition value of the one or more addition means is used as the threshold value for each sampling point used by. 6. The radar device according to claim 2, further comprising: when the normalized addition value corresponding to the plurality of sampling points has a value larger than a predetermined threshold value, the plurality of normalized values. Approximating means for obtaining an approximate curve by connecting the added values with a predetermined approximate expression, and a time delay from the sending timing corresponding to the peak position of the approximate curve obtained by the approximating means is given to the distance calculating means. A radar device comprising a peak detecting means. 7. The radar device according to any one of claims 1 to 6, further determining whether or not the normalized addition value of any one of the sampling points of the addition means exceeds a predetermined upper limit value. An upper limit discriminating means, a lower limit discriminating means for discriminating whether or not the normalized addition value of any sampling point of the adding means exceeds a predetermined lower limit value, and the upper limit discriminating means normalizes any sampling point. When it is determined that the normalized addition value exceeds the upper limit value, the sensitivity of the device is lowered, and when the lower limit determination means determines that the normalized addition value at any sampling point does not exceed the lower limit value. A radar apparatus comprising: a sensitivity adjusting means for adjusting the sensitivity of the apparatus. 8. The radar apparatus according to claim 7, wherein the sensitivity adjusting unit is an output adjusting unit that adjusts the output signal output of the sending unit so that the normalized addition value falls within the upper and lower limit values. . 9. The gain adjusting means for adjusting the reception gain of the receiving means so that the normalized addition value is within the upper and lower limit values is used as the sensitivity adjusting means.
The described radar device. 10. The radar device according to claim 7, wherein the sensitivity adjusting unit is an addition number adjusting unit for increasing or decreasing the number of additions of the adding unit. 11. Sending means for periodically outputting a pulsed signal to the outside, and receiving means for continuously receiving signals from a direction in which the signal output by the sending means is reflected by a target, The binarizing means for binarizing the signal received by the receiving means, and the binarizing means for each sampling period in which a fixed one or a plurality of time zones after the sending timing of the sending means are different Sampling means for sampling the binarized signal, and one or a plurality of integrating means for integrating the binarized signal for each sampling period by the sampling means by a predetermined number of times of sending of the signal by the sending means, The integrated value of each means is normalized and each normalized integrated value is compared with a predetermined threshold value, and a judging means for judging whether or not there is a reflection signal from an external target based on the magnitude is provided. That the radar device. 12. The radar device according to claim 11, further comprising a value greater than the predetermined threshold value after the transmission timing of the transmission means when the determination means determines that a reflection signal from an external target exists. A radar device comprising distance calculating means for calculating a distance to an external target based on a time delay until a sampling period corresponding to an integrating means indicating a normalized integrated value. 13. Sending means for periodically outputting a pulsed signal to the outside, and receiving means for continuously receiving signals from the direction in which the signal output by the sending means is reflected by a target. Binarizing means for binarizing the signal received by the receiving means, and sampling means for sampling the binarized signal output by the binarizing means in a predetermined sampling period after the sending timing of the sending means. An integrating means for integrating a binarized signal of a predetermined sampling period by the sampling means for each predetermined number of times of transmission of the signal by the transmitting means; and a plurality of types of sampling periods of the sampling means with different time zones. , When the integrator completes the integration operation for a predetermined number of times in one sampling period, it sequentially switches to another sampling period. Sampling timing switching means for causing the integrating means to perform an integrating operation, storage means for storing the integrated value of the integrating means in association with each of a plurality of types of sampling periods, and integration corresponding to each sampling period stored by the storing means. Comparing each normalized integral value that normalizes the value with a predetermined threshold value, a determination unit that determines whether or not there is a reflection signal from an external target based on the magnitude, and the determination unit is an external When it is determined that there is a reflection signal from the target, after the sending timing of the sending means, an external target can be obtained based on the time delay until the sampling period when the normalized integral value larger than the predetermined threshold value is obtained. A radar device comprising a distance calculating means for calculating the distance of the. 14. An interference wave detecting means for detecting an interference wave included in a reflected signal received by the receiving means, and an interference wave removing means for removing an interference wave detected by the interference wave detecting means. The radar device according to any one of claims 11 to 13, wherein the radar device comprises: 15. A further one or a plurality of integrating means for integrating a binarized signal for noise received by the receiving means a predetermined number of times in the same sampling period during a period in which the transmitting means does not transmit a signal, 15. The radar according to claim 11, wherein each of the normalized integrated values obtained by normalizing each of the integrated values of the one or more other integrating means is used as the threshold for each sampling period used by the determining means. apparatus. 16. The radar device according to claim 12, further comprising: when the normalized integrated value corresponding to the plurality of sampling periods has a value larger than a predetermined threshold value, the plurality of normalized signals. Approximating means for obtaining an approximated curve by connecting the integrated values with a predetermined approximate expression, and a time delay from the sending timing corresponding to the peak position of the approximated curve obtained by the approximating means is given to the distance calculating means. A radar device comprising a peak detecting means. 17. The radar device according to claim 11, further comprising determining whether or not the normalized integral value of any one of the sampling periods of the integrating means exceeds a predetermined upper limit value. An upper limit discriminating means, a lower limit discriminating means for discriminating whether or not the normalized integrated value of any of the sampling periods of the integrating means exceeds a predetermined lower limit value, and the upper limit discriminating means for normalizing any sampling period. When it is determined that the integrated integral value exceeds the upper limit value, the sensitivity of the device is lowered, and when the lower limit determining means determines that the normalized integral value of any sampling period does not exceed the lower limit value. A radar apparatus comprising: a sensitivity adjusting means for adjusting the sensitivity of the apparatus. 18. The radar apparatus according to claim 17, wherein the sensitivity adjusting means is an output adjusting means for adjusting the output signal output of the sending means so that the normalized integral value falls within the upper and lower limit values. . 19. The radar apparatus according to claim 17, wherein the sensitivity adjusting unit is a gain adjusting unit that adjusts the reception gain of the receiving unit so that the normalized integral value falls within the upper and lower limit values. 20. The radar device according to claim 17, wherein the sensitivity adjusting unit is an integration number adjusting unit that increases or decreases the integration number of the integrating unit.