JPH0770954B2 - Signal analysis and synthesis filter bank - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal analysis filter bank for dividing a signal into subband signals of equal bandwidth and a signal synthesis filter bank for synthesizing the subband signals to reproduce an original signal.

[0002]

2. Description of the Related Art In recent years, a signal analysis / synthesis filter bank has been attracting attention as a signal analysis / synthesis means for realizing high-efficiency coding by subband coding of audio signals and image signals.

As a conventional signal analysis and synthesis filter bank, for example, J. H. Rothweiler (JHR) is used.
OTHWEILER) Proceedings of IAC SSP held in Boston in 1983 (PROC. ICA)
SSP 83, BOSTON) pp. 1280 to 1283 "Polyphase Quadrature Filter, New Subband Coding Technology" (POLYPHASE QUADRATURE FILTERS-A
NEW SUBBAND CODING TECHNIQUE)
(Referred to as reference 1) and H. Jay Nussbaumer (H.
1 by J.NUSSBAUMER) and M.VETTERLI
Proceedings of I.C.A.S.S.P. held in San Diego in 984 (PROC. ICASSP 84, SAN DI
EGO) "Computation-efficient QMF filter bank" announced on pages 11.3.1 to 11.3.4.
ALLY EFFICIENT QMF FILTER BANKS) (hereinafter referred to as Reference 2).

A conventional signal analysis and synthesis filter bank will be described below. FIG. 5 is a block diagram of a conventional signal analysis filter bank and signal synthesis filter bank. In FIG. 5, 51 is a signal analysis filter bank, 52 is a signal synthesis filter bank, M is the number of band divisions, 53 (0) to 53 (M-1) are band pass filters for analysis, and 54 (0) to 54 ( M-1) is a decimator, 55
(0) to 55 (M-1) are interpolators, and 56 (0) to 56 (56)
(M-1) is a band pass filter for synthesis, and 57 is an adder. The signal analysis filter bank 51 is composed of M band pass filters 53 (0) to 53 (M-1) and M decimators 54 (0) to 54 (M-1), and the signal synthesis filter bank 52 is M interpolators 55 (0) to 55 (M-
1) and M band pass filters 56 (0) to 56 (M-
1) and an adder 57. The band pass filters 53 (0) to 53 (M-1) for analysis and the band pass filters 56 (0) to 56 (M-1) for synthesis are paired with each other. The signal analysis filter bank 51 converts the input signal of the sampling frequency f _s into a band-pass signal by M equal-bandwidth analysis band-pass filters 53 (0) to 53 (M−1), and a decimator 54 (0). ) To 54 (M-1), the sampling frequency is set to 1 by thinning out M-1 data for every M data and outputting 1 data.
/ M, convert to a subband signal of sampling frequency f _s / M, and output. The signal synthesis filter bank 52 receives the sub-band signal of the sampling frequency f _s / M output from the signal analysis filter bank 51 as an input, and interpolators 55 (0) to 55 (M−1) use M−1 zeros. The sampling frequency is set to M by inserting data.
Bandpass filters 56 (0) to 5 for synthesizing
6 (M-1) to form a bandpass signal, and then adder 57
And outputs a full band signal having a sampling frequency f _s .

In the subband coding of audio signals and image signals, the bias of the distribution of the subband signals in the frequency direction between the signal analysis filter bank and the signal synthesis filter bank and human auditory or visual characteristics are used. Performs information compression and realizes high-efficiency coding.

From Documents 1 and 2, such a signal analysis and synthesis filter bank has a bandwidth of f _s / 4M,
The amplitude response H (f) at the frequency f is expressed by the following relational expression (Equation 1)
A prototype filter satisfying 5) can be constructed by frequency transition.

[0007]

[Equation 15]

FIG. 6 is a diagram for explaining the frequency amplitude response of the signal analysis or synthesis filter bank. Figure 6
Where (a) shows the frequency magnitude response of a prototype filter with a bandwidth fs / 4M. In the same figure, (b) shows the frequency amplitude response of a signal analysis or synthesis filter bank consisting of M filters of bandwidth f _s / 2M constructed by frequency-transitioning the prototype filter of (a). As shown in the figure, the i-th sub-band (where 0 ≦
The center frequency of i ≦ M−1) is f _s (2i + 1) / 4M.

According to Reference 2, when the 2MP + 1 filter coefficients (P is a positive integer) of the linear phase acyclic prototype filter are set to h (l) (where 0 ≦ l ≦ 2MP), the signal analysis filter bank The filter coefficient h _a (i, l) of the i-th subband is given by (Equation 16).

[0010]

[Equation 16]

Therefore, if the input signal at the sample time n of the signal analysis filter bank is x (n), then the i-th
Output signal y at subband sample time Mm
(I, Mm) is given by (Equation 17).

[0012]

[Equation 17]

When 2M first intermediate signals w1 (k) (where 0≤k≤2M-1) obtained by (Equation 18) and (Equation 19) are introduced, the subband signal becomes ( It can be obtained by the equation (20), and the calculation amount can be reduced as compared with the case of directly calculating the equation (17).

(A) When k = 0,

[0015]

[Equation 18]

(B) For 1≤k≤2M-1,

[0017]

[Formula 19]

[0018]

[Equation 20]

Digital signal processor (hereinafter referred to as DS
In order to estimate the calculation amount and the memory amount when the above process is realized by using (P), the calculation of (Equation 18) and (Equation 19) is the first operation, and the calculation of (Equation 20) is the second operation. Will be called the operation of. In many high-speed DSPs, a series of product-sum calculations are efficiently executed by pipeline processing, so the number of calculations will be evaluated by the number of product-sum calculations.
In order to calculate M subband signals, the first operation requires 2MP + 1 product-sum calculations, and the second operation requires 2M ² product-sum calculations. Random access memory (hereinafter referred to as RAM) includes a memory that stores 2MP + 1 input signals, a memory that stores 2M first intermediate signals, and a memory that stores M subband output signals. is necessary. As a read-only memory (hereinafter referred to as a ROM), 2MP + 1 filter coefficient tables (0 ≦ l ≦ 2M for executing the first operation)
H (l) table for P) and 2M ² cosine coefficient tables (0 ≦ i ≦ for executing the second operation).
Cos [π (2i +) for M−1 and 0 ≦ k ≦ 2M−1
1) (2k-M) / 4M] table).

Similarly, the filter coefficient h _s (i, l) of the i-th sub-band of the signal synthesis filter bank is obtained by (Equation 21).

[0021]

[Equation 21]

Therefore, the input signal y at the sample time Mm of the i-th subband of the signal synthesis filter bank
If (i, Mm), the output signal x ′ (Mm + at the sampling time Mm + n (where 0 ≦ n ≦ M−1) is obtained.
n) is given by (Equation 22).

[0023]

[Equation 22]

Here, 4MP + 1 second intermediate signals w
2 (k) (where 0 ≦ k ≦ 4MP) is introduced, and 0 ≦ k
The second intermediate signal w2 (k) for w ≦ 4MP-2M
2 (k + 2M), and w2 (k) is obtained by (Equation 23) for 0 ≦ k ≦ 2M−1,
The output signal can be obtained by (Equation 24) and (Equation 25), and the amount of computation can be reduced compared to the case where (Equation 22) is directly calculated.

[0025]

[Equation 23]

(A) When n = 0,

[0027]

[Equation 24]

(B) When 1≤n≤M-1,

[0029]

[Equation 25]

As with the signal analysis filter bank,
Hereinafter, in order to estimate the calculation amount and the memory amount when realizing using the DSP, the calculation of (Equation 23) is performed by the third operation (Equation 2)
The calculation of 4) and (Equation 25) will be referred to as a fourth operation. In order to calculate M output signals, 2M ² product-sum calculations are required in the third operation, and 2M ² in the fourth operation.
P + 1 product-sum calculations are required. As RAM, M
Memory for storing 4 subband input signals and 4MP +
A memory for storing one second intermediate signal and a memory for storing M output signals are required. As the ROM, 2M ² cosine coefficient tables (c for 0 ≦ i ≦ M−1 and 0 ≦ k ≦ 2M−1) for executing the third operation are used.
os [π (2i + 1) (2k + M) / 4M]) and 2MP + 1 filter coefficients (h (l) table for 0 ≦ l ≦ 2MP) for executing the fourth operation. .

[0031]

However, the above-mentioned conventional signal analysis and synthesis filter banks are, for example, DS.
When implementing using hardware such as P,
There is a problem that the amount of filter calculation is large and the amount of memory is large. That is, it had the following problems.

(1) A large amount of calculation is required to realize the filter bank. (2) The memory capacity for storing the first and second intermediate signals is large. Particularly, the amount of memory for storing the second intermediate signal is large.

(3) A cosine coefficient table is required for each of the signal analysis filter bank and the synthesis filter bank, and the amount of memory is large.

(4) The amount of memory for storing the filter coefficient is large. The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a small signal analysis and synthesis filter bank with low power consumption by reducing the calculation amount and memory amount required to realize the filter bank. And

That is, a first object of the present invention is to provide a small signal analysis filter bank with low power consumption, which reduces the calculation amount and the memory amount for storing the first intermediate signal.

A second object of the present invention is to provide a small signal synthesis filter bank with low power consumption by reducing the calculation amount and the memory amount for storing the second intermediate signal.

A third object of the present invention is to reduce the memory amount of the cosine coefficient table and to make the signal analysis and synthesis filter bank a common table, thereby reducing the hardware scale. It is to provide a bank.

Further, a fourth object of the present invention is to provide a signal analysis and synthesis filter bank in which the memory amount of the filter coefficient table is reduced.

[0039]

In order to achieve this object, the signal analysis filter bank of the present invention has a linear phase acyclic type having 2MP (P is a positive integer) filter coefficients having a first value of zero. Of the prototype filter by frequency transition, and the filter coefficient of the prototype filter is h (l) (where 0 ≦ l ≦ 2MP−1),
The input signal at sampling time n is x (n), and the M first intermediate signals are w1 (k) (where 0 ≦ k ≦ M−
1), the output signal at the sampling time Mm of the i-th subband (where 0 ≦ i ≦ M−1) is y (i, Mm)
When (1) M is an even number, (a) k = 0,

[0040]

[Equation 26]

(B) When 1≤k≤M / 2,

[0042]

[Equation 27]

(C) In M / 2 + 1≤k≤M-1,

[0044]

[Equation 28]

A first arithmetic unit for calculating a first intermediate signal by

[0046]

[Equation 29]

A second arithmetic unit for calculating the sub-band output signal by (2) when M is an odd number, (a)
For 0 ≦ k ≦ (M−1) / 2,

[0048]

[Equation 30]

(B) In (M + 1) / 2≤k≤M-1,

[0050]

[Equation 31]

A first arithmetic unit for calculating a first intermediate signal by

[0052]

[Equation 32]

And a second arithmetic unit for calculating the sub-band output signal. Further, the signal synthesis filter bank of the present invention is configured by frequency-transitioning a linear-phase acyclic prototype filter having 2MP (P is a positive integer) filter coefficients whose initial value is zero. The filter coefficient of h (l)
(Where 0 ≦ l ≦ 2MP−1), the input signal at the sampling time Mm of the i-th subband (where 0 ≦ i ≦ M−1) is y (i, Mm), 2MP second intermediate signals Where w2 (k) (where 0 ≦ k ≦ 2MP−1) and the output signal at the sampling time Mm + n (where 0 ≦ n ≦ M−1) is x ′ (Mm + n), 0 ≦ k ≦
The second intermediate signal w2 (k) is w for 2MP-M-1.
Shift to 2 (k + M) and (1) M is even,

[0054]

[Expression 33] 33

A third arithmetic unit for calculating a second intermediate signal for 0 ≦ k ≦ M−1, and (a) 0 ≦ n ≦ M /
In 2-1

[0056]

[Equation 34]

(B) When n = M / 2,

[0058]

[Equation 35]

(C) In M / 2 + 1≤n≤M-1,

[0060]

[Equation 36]

And a fourth arithmetic unit for calculating an output signal according to (2) where M is an odd number,

[0062]

[Equation 37]

A third arithmetic unit for calculating a second intermediate signal for 0 ≦ k ≦ M−1, and (a) 0 ≦ n ≦ (M
-1) / 2,

[0064]

[Equation 38]

(B) In (M + 1) / 2≤n≤M-1,

[0066]

[Formula 39]

And a fourth arithmetic unit for calculating the output signal. Further, the second operation unit of the signal analysis filter bank and the third operation unit of the signal synthesis filter bank of the present invention are provided with M or 2M or 4M common cosine coefficient tables.

Further, the first calculation section of the signal analysis filter bank and the fourth calculation section of the signal synthesis filter bank of the present invention have MP common filter coefficient tables.

[0069]

The signal analysis filter bank according to the present invention performs efficient calculation using the first intermediate signal with the above-described configuration, and thus the number of product-sum calculations performed by the second arithmetic unit can be increased as compared with the conventional example. The memory amount of the first intermediate signal can be halved.

The signal synthesizing filter bank of the present invention performs efficient calculation using the second intermediate signal in the above-mentioned configuration, and thus the number of product-sum calculations of the third arithmetic unit is increased as compared with the conventional example. The memory amount of the second intermediate signal can be halved.

Further, the signal analysis and synthesis filter bank of the present invention makes the table storing the cosine coefficient common in the analysis and the synthesis, and utilizes its periodicity and symmetry to perform either analysis or synthesis. In order to realize, the memory amount of the cosine coefficient can be reduced to 1 / 2M, 1 / M or 2 / M of the conventional example. By using a common table for analysis and synthesis, the number can be further reduced by half when analysis and synthesis are performed simultaneously.

In the signal analysis and synthesis filter bank of the present invention, the table storing the filter coefficients is made common for analysis and synthesis, and the symmetry is utilized to realize either analysis or synthesis. The memory amount of the filter coefficient can be halved. By using a common table for analysis and synthesis, the number can be further reduced by half when analysis and synthesis are performed simultaneously.

[0073]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

The signal analysis filter bank of the present invention divides the signal of sampling frequency f _s into M equal-bandwidth sub-band signals of sampling frequency f _s / M, and also the signal synthesis filter bank of the present invention. Is a filter bank that synthesizes M equal-bandwidth subband signals of sampling frequency f _s / M to regenerate a full-band signal of sampling frequency f _s , the first value of these filter banks being It is configured by frequency-transitioning a linear-phase acyclic prototype filter having 2MP (P is a positive integer) filter coefficients which are zero. 2MP
In the conventional prototype filter having +1 filter coefficient, the first and last filter coefficient values are set to zero (h (0)
= H (2MP) = 0). With such a configuration, the first calculation in the signal analysis filter bank of the conventional example is (a) k = 0 and (b) 1 ≦ k ≦ 2M−
What was divided into two cases of 1 is 0 ≦ k ≦ 2M−1
Then, the equation (5) should be calculated. Similarly, the fourth operation of the conventional signal synthesis filter bank is
What was divided into two cases, (a) n = 0 and (b) 1 ≦ n ≦ M−1, is different from 0 ≦ n ≦ M−1 (Equation 2
It suffices to calculate 5).

Further, the prototype filter of the present invention is
According to the linear phase condition, the relationship of (Equation 40) is established regarding the filter coefficient.

[0076]

[Formula 40]

FIG. 1 is a block diagram of a signal analysis filter bank according to the first embodiment of the present invention. In FIG. 1, 11 is a first arithmetic unit, 12 is a second arithmetic unit, 13 is 2MP input signal memories, 14 is M first intermediate signal memories, and 15 is M subband output signals. It is a memory.

The first calculation unit 11 includes a first multiplier 16,
First filter coefficient memory 17, first adder / subtractor 1
8 and a first register 19. The second arithmetic unit 12 is composed of a second multiplier 110, a first cosine coefficient memory 111, a second adder / subtractor 112, and a second register 113.

The operation of the signal analysis filter bank of the first embodiment constructed as above will be described below.

First, the main variables used in the following description will be defined. That is, the filter coefficient of the prototype filter is h (l) (where 0 ≦ l ≦ 2MP−
1), input signal at sampling time n is x
(N), w 1 (k) (where
0 ≦ k ≦ M−1), i-th subband (where 0 ≦ i ≦
The output signal at the sampling time Mm of M-1) is y
(I, Mm).

The input signal memory 13 is a memory for storing the latest 2MP input signals x (n). When M input signals of the sampling frequency f _s are input to the input signal memory 13, the first arithmetic unit 11 calculates M first intermediate signals w1 (k) according to the following equation, and the result is obtained. Are stored in the first intermediate signal memory 14. The calculation of w1 (k) is divided into the following two cases depending on whether the value of M is an even number or an odd number. (1) When M is an even number, (a) k = 0,

[0082]

[Formula 41]

(B) When 1≤k≤M / 2,

[0084]

[Equation 42]

(C) For M / 2 + 1≤k≤M-1,

[0086]

[Equation 43]

(2) When M is an odd number, (a) 0≤k≤
In (M-1) / 2,

[0088]

[Equation 44]

(B) For (M + 1) / 2≤k≤M-1,

[0090]

[Equation 45]

The first filter coefficient memory 17 is
6) 2MP first filter coefficients h1 defined in 6)
It remembers (l). Where INT () is ()
It is a function that rounds down the value after the decimal point.

[0092]

[Equation 46]

In the first calculation section 11, the first calculation is performed at the beginning of the calculation.
Input signal memory 1 after clearing register 19 of
The input signal from the first filter coefficient memory 17 and the first filter coefficient from the first filter coefficient memory 17 are read according to the address shown in the above calculation formula, the first multiplier 16 is used to multiply both, and the multiplication result is the first Cumulative calculation is performed using the adder / subtractor 18 and the first register 19 that holds the result of addition / subtraction. Whether the first adder / subtractor 18 performs addition or subtraction depends on the above calculation formula. First multiplier 1
6 and the first adder / subtractor 18 and the first register 19 perform sum-of-products calculation.

As shown in the above equation, the first arithmetic unit 11 calculates M first intermediate signals by performing 2MP product-sum calculations both when M is even and when M is odd.

Next, the second arithmetic section 12 calculates M subband output signals using the first intermediate signal memory 14 and the first cosine coefficient memory 111 according to the following equation. . The calculation of the second calculation unit 12 is also divided into the following two cases depending on whether M is an even number or an odd number. (1) M
Is an even number,

[0096]

[Equation 47]

(2) If M is an odd number,

[0098]

[Equation 48]

The first cosine coefficient memory 111 is defined by (Equation 49) when M is an even number, and M ² cosine coefficients c defined by (Equation 50) when M is an odd number.
It stores (i, k). (1) If M is an even number,

[0100]

[Equation 49]

(2) When M is an odd number,

[0102]

[Equation 50]

The second arithmetic unit 1 as well as the first arithmetic unit 11
In step 2, after the second register 113 is cleared to zero at the beginning of the calculation, the first intermediate signal from the first intermediate signal memory 14 and the cosine coefficient from the first cosine coefficient memory 111 are calculated by the above formula. Reading is performed according to the indicated address, and the sum of products calculation is performed using the second multiplier 110, the second adder / subtractor 112, and the second register 113. Second
Whether the addition / subtraction is performed by the adder / subtractor 112 is according to the above calculation formula. The second arithmetic unit 12 calculates M subband signals by M ² times of product-sum calculations both when M is even and when M is odd, as shown in the above formula.
The subband output signal memory 15 is a memory for storing and outputting M subband signals y (i, Mm) (where 0 ≦ i ≦ M−1), which are the calculation results of the second arithmetic unit 12. Is.

The operation of the first embodiment will be further described using equations. Here, a case where M is an even number will be described, but a case where M is an odd number can be similarly described, and a description thereof will be omitted. (Equation 41) and (Equation 42)
And (Equation 43) are substituted into (Equation 47). In consideration of the fact that (Equation 51) is generally established, the following variable q (where 0 ≦ q ≦ 2M−1) is introduced, (Equation 5)
The relational expressions 2) to (Equation 56) hold.

[0105]

[Equation 51]

(1) q = M / 2−k (where 0 ≦ k ≦
M / 2, 0 ≦ q ≦ M / 2)

[0107]

[Equation 52]

(2) q = M / 2 + k (where 1 ≦ k ≦
M / 2, M / 2 + 1 ≦ q ≦ M)

[0109]

[Equation 53]

(3) q = M / 2 + k (where M / 2 +
1≤k≤M-1, M + 1≤q≤3 / 2M-1)

[0111]

[Equation 54]

(4) q = 3M / 2

[0113]

[Equation 55]

(5) q = 5M / 2-k (where M / 2
+ 1 ≦ k ≦ M-1, 3M / 2 + 1 ≦ q ≦ 2M-1)

[0115]

[Equation 56]

The variable k is replaced with q using the relational expressions of (Equation 52) to (Equation 58). Furthermore, if the variable q is replaced with the variable l by l = 2Mj + q (where 0 ≦ l ≦ 2MP−1), and h (2MP) = 0 is taken into consideration, (Equation 17) is obtained. That is, although the calculation method is different between the first embodiment and the document 2, it has been proved that the final results match.

As described above, according to the first embodiment, M
It is possible to reduce the number of product sums of the second arithmetic unit necessary to output the individual subband signals from 2M ² times of the conventional example to M ² times.

Further, the memory amount of the first intermediate signal can be halved from 2M in the conventional example to M.

FIG. 2 is a block diagram of a signal synthesis filter bank according to the second embodiment of the present invention. In FIG. 2, 21 is a third arithmetic unit, 22 is a fourth arithmetic unit, 23 is a subband input signal memory, 24 is a second intermediate signal memory, and 25 is an output signal memory.

The third calculation section 21 includes a third multiplier 26,
Second cosine coefficient memory 27, third adder / subtractor 2
8 and a third register 29. The fourth calculation unit 22 is composed of a fourth multiplier 210, a second filter coefficient memory 211, a fourth adder / subtractor 212, and a fourth register 213.

The operation of the signal synthesizing filter bank of the second embodiment constructed as above will be described below.

First, the main variables used in the following description will be defined. The filter coefficient of the prototype filter is h (l) (where 0 ≦ l ≦ 2MP−1), and the input signal at the sampling time Mm of the i-th subband (where 0 ≦ i ≦ M−1) is y (i, Mm). ), The second intermediate signal is w2 (k) (where 0≤k≤2MP-1), and the output signal at the sampling time Mm + n (where 0≤n≤M-1) is x '(Mm + n).

The subband input signal memory 23 stores M subband input signals y (i, Mm) (where 0≤i≤M).
It is a memory for storing -1). Sampling frequency f
_When M subband input signals of _s / M are input to the subband input signal memory 23, the second intermediate signal w2 (k) is changed to w2 (k + M) for 0 ≦ k ≦ 2MP-M−1. shift. This shift is performed by actually moving the data in the second intermediate signal memory 24. In addition, 2M is obtained by adding M to the address without moving the data in the memory.
It can be equivalently performed by cyclic addressing that takes the remainder of P. Next, the third arithmetic unit 21 calculates the second intermediate signal w2 (k) for 0 ≦ k ≦ M−1 according to the following equation, and stores the result in the second intermediate signal memory 24. The calculation of w2 (k) is divided into the following two cases depending on whether the value of M is an even number or an odd number. (1) If M is an even number,

[0124]

[Equation 57]

(2) If M is an odd number,

[0126]

[Equation 58]

The second cosine coefficient memory 27 defines M ² cosine coefficients c defined by (Equation 59) when M is an even number and defined by (Equation 60) when M is an odd number.
It stores (i, k). (1) If M is an even number,

[0128]

[Equation 59]

(2) When M is an odd number,

[0130]

[Equation 60]

This value is the same as the cosine coefficient used in the first cosine coefficient memory 111 of the signal analysis filter bank of the first embodiment.

In the third operation unit 21, the third calculation unit 21
Of the sub-band input signal memory 23 and the cosine coefficient from the second cosine coefficient memory 27 are read out according to the address indicated by the above calculation formula, and the third multiplier 26 Are used to multiply the two, and the multiplication results are accumulated using the third adder / subtractor 28 and the third register 29 to calculate the sum of products.
Whether the third adder / subtractor performs addition or subtraction depends on the above calculation formula. The number of sums of products of the third calculation unit 21 is M
Is M ² for both even and odd cases. The second intermediate signal memory 24 is a 2MP number of memories that store the second intermediate signal w2 (k), which is the calculation result of the third calculation unit 21.

Next, the fourth arithmetic unit 22 uses the second intermediate signal memory 24 and the second filter coefficient memory 211 to calculate M output signals according to the following equation. The calculation of the fourth calculation unit 22 is also divided into the following two cases depending on whether M is an even number or an odd number. (1) When M is an even number, (a) In 0 ≦ n ≦ M / 2-1,

[0134]

[Equation 61]

(B) With n = M / 2,

[0136]

[Equation 62]

(C) For M / 2 + 1≤n≤M-1,

[0138]

[Equation 63]

(2) When M is an odd number, (a) 0≤k≤
In (M-1) / 2,

[0140]

[Equation 64]

(B) In (M + 1) / 2≤k≤M-1,

[0142]

[Equation 65]

The second filter coefficient memory 27 is
2) 2MP number of second filter coefficients h2 defined in 6)
It remembers (l).

[0144]

[Equation 66]

Similar to the third arithmetic unit 21, the fourth arithmetic unit 22 clears the fourth register 213 to zero at the beginning of the calculation and then outputs the second intermediate signal from the second intermediate signal memory 24. The signal and the second filter coefficient from the second filter coefficient memory 211 are read according to the address shown in the above calculation formula, and the fourth multiplier 210 and the fourth adder / subtractor 2 are read.
12 and the fourth register 213 are used to calculate the sum of products.
Whether the fourth adder / subtractor 212 performs addition or subtraction depends on the above calculation formula.

As described above, the fourth arithmetic unit 22 can calculate M full-band signals by calculating the sum of products 2MP times both when M is even and when M is odd. The output signal memory 25 stores M, which is the calculation result of the fourth arithmetic unit 22.
This is a memory for storing and outputting individual full band signals.

In the same way as described in the first embodiment, also in the second embodiment, when M is an even number, (Equation 57) is changed to (Equation 61), (Equation 62) and (Equation 63). Substitute, y
(Equation 22) can be derived by using the fact that (i, n) takes a value of zero except when n is an integer multiple of M. That is, although the calculation method is different between the second embodiment and the document 2, it can be proved that the final results match.

As described above, according to the second embodiment, the third arithmetic unit 2 necessary for outputting M full-band signals.
The number of product sums of 1 can be halved from 2M ² of the conventional example to M ² .

Further, the memory amount of the second intermediate signal can be halved from 4MP in the conventional example to 2MP.

Regarding the cosine coefficient memory, the same table can be used for the signal analysis filter bank of the first embodiment and the signal synthesis filter bank of the second embodiment, and the signal analysis filter bank and the signal synthesis filter bank can be used. It is possible to reduce the amount of memory in the case of simultaneous realization to half as compared with the conventional example.

FIG. 3 is a block diagram of the third embodiment of the present invention. In FIG. 3, 31 is a RAM, 32 is a ROM, 33 is a multiplier, 34 is an adder / subtractor, and 35 is a register.
This is a typical DSP configuration. In the signal analysis filter bank shown in FIG. 1, the configurations of the first calculation unit and the second calculation unit are the same, and in the signal synthesis filter bank shown in FIG. 2, the third calculation unit and the fourth calculation unit. The arithmetic units have the same configuration. In the third embodiment, these two arithmetic units have a common 1
It is used as one operation unit and is used for time division to realize a signal analysis or synthesis filter bank. By switching the operation mode between analysis and synthesis using the hardware of FIG. 3, both the signal analysis filter bank and the synthesis filter bank can be realized by the same hardware. In the case of the signal analysis filter bank, the RAM 31 comprises an input signal memory, a first intermediate signal memory and a subband output signal memory, and the ROM 32 comprises a first filter coefficient memory and a cosine coefficient memory. In the case of the signal synthesis filter bank, the RAM 31 is composed of a subband input signal memory, a second intermediate signal memory and an output signal memory,
The ROM 32 is composed of a cosine coefficient memory and a second filter coefficient memory (in the case of the third embodiment, the cosine coefficient memory can be used in common, so there is no need to distinguish it from the first and second ones). .).

As described above, in the third embodiment, the hardware scale of the arithmetic unit can be reduced by half by sharing the arithmetic unit.

FIG. 4 is a detailed block diagram of an embodiment in which the memory amount of the cosine coefficient memory is reduced. In FIG. 4, 41 is a switch, 42 is a remainder calculator, 43 is an address register, 44 is an adder, and 45 is a ROM storing a cosine coefficient table. The switcher 41 selects the direct address in the direct address mode according to the setting of the address operation mode, selects the output of the adder 44 in the incremental address mode, and outputs the result as the remainder calculator 4.
Output to 2. The remainder calculator 42 outputs one cycle of the input, that is, the remainder of 4M.
It is unnecessary when is a power of 2. The remainder calculator 42 is
It plays a role of converting cosine coefficient data for time longer than one cycle into cosine coefficient data for time less than one cycle. The address register 43 holds the output of the remainder calculator 42 and outputs the ROM address for the ROM 45. The adder 44 outputs the result of adding the increment address to the ROM address which is the output of the address register 43, thereby outputting the address increased by the increment address specified by the previous address. The ROM 45 is a look-up table and outputs ROM data corresponding to the ROM address designated by the address register 43.

The ROM 45 stores one cycle of the cosine function represented by (Equation 67) or (Equation 68) as the cosine coefficient data d (r) when r is an address, that is, 4
It stores M values. (1) If M is an even number,

[0155]

[Equation 67]

(2) When M is an odd number,

[0157]

[Equation 68]

By adopting the configuration shown in FIG. 4, the first
(Equation 49), (Equation 5) of the embodiment of
0) or the same value as the cosine coefficient represented by (Equation 59) or (Equation 60) can be output. Below, M
Will be described in the case of an even number, but a similar case can be described in the case of an odd number, and therefore the description thereof will be omitted here. Further, although the usage in the signal analysis filter bank will be described, the description will be omitted because the signal synthesis filter bank can be similarly described.

In the signal analysis filter bank of the first embodiment, as shown in (Equation 47), the value of i is kept constant and the value of k is changed from 0 to M-1. First, the value of the direct address is set to 2i + 1 and the switch 41 is set to the direct address mode to set the ROM address to r = 2i + 1 and output the ROM data.
The value of the ROM data at this time is the value of the cosine function of the term of k = 0 in (Equation 47). Next, increment the address by 2i
The ROM address is set to r = 4i + 2 by setting +1 and the switch 41 to the incremental address mode to output the ROM data. This is the value of the cosine function of the term of k = 1 in (Equation 47). Hereinafter, by operating in the incremental address mode, r = 6i + 3,8
i + 4, ..., (2i + 1) (M-1), k
The value of the cosine function of the terms of = 2, 3, ..., M-1 can be output.

As described above, in the embodiment of FIG. 4, the cosine coefficient table is stored for one cycle by utilizing the periodicity of the cosine function, so that the memory amount of the cosine coefficient is changed from 2M ² of the conventional example to 4M. Can be reduced to 2 / M,
For example, when M is 16, the memory amount can be reduced to 1/8.

Further, by utilizing the symmetry of the cosine function, the half cycle or the quarter cycle, that is, the memory amount of the cosine coefficient table can be set to 2M or M.

Next, an embodiment of the filter coefficient memory in which the memory size of the filter coefficient is reduced to MP using the relational expression (Equation 40) will be described.

The filter coefficient memory of the present embodiment is (equation 6)
The MP filter coefficients g (s) defined in 9) are stored.

[0164]

[Equation 69]

The following relational expression is provided between the first filter coefficient h1 (l) of the first embodiment defined by (Equation 46) and the filter coefficient g (s) defined by (Equation 69). To establish. (1) When l = 0,

[0166]

[Equation 70]

(2) When 1 ≦ l ≦ MP,

[0168]

[Equation 71]

That is, the filter coefficient table g (s)
Is referred to by the address s = l−1, and the table data is output as it is or with the sign inverted depending on whether the value of INT (l / 2M) is an even number or an odd number. (3) MP + 1 ≦ l ≦ 2MP-1

[0170]

[Equation 72]

That is, the filter coefficient table g (s)
With an address s = 2MP-1 and INT (l / 2
Depending on whether the value of M) is an even number or an odd number, the table data is output as it is or with its sign inverted.

When this filter coefficient table is used instead of the second filter coefficient h2 (l) of the second embodiment defined by (Equation 66), M is stored just before storing the full band output signal in the memory. It is necessary to double and match the gain.

As described above, in this embodiment, by utilizing the symmetry of the filter coefficient of the linear phase acyclic filter, the memory amount of the filter coefficient can be halved from 2MP of the conventional example to MP. Furthermore, the filter coefficient table can be shared between the signal analysis filter bank and the synthesis filter bank, and the memory amount of the filter coefficient table when the signal analysis filter bank and the signal synthesis filter bank are realized using the same hardware. Can be halved.

[0174]

As described above, the signal analysis filter bank of the present invention is provided with the first arithmetic unit and the second arithmetic unit, so that the sum of products of the second arithmetic unit is compared with the conventional example. The number of calculations and the memory amount of the first intermediate signal can be reduced by half.

Further, the signal synthesis filter bank of the present invention is provided with the third arithmetic unit and the fourth arithmetic unit, so that the product-sum calculation frequency of the third arithmetic unit and the third arithmetic unit are compared with those of the conventional example. The memory amount of the intermediate signal of 2 can be halved.

Further, the signal analysis and synthesis filter bank of the present invention is provided with M or 2M or 4M cosine coefficient tables which can be commonly used for analysis and synthesis, so that the memory amount thereof is 1/2 M or respectively. It can be reduced to 1 / M or 2 / M.

Further, the signal analysis and synthesis filter bank of the present invention can reduce its memory amount by half by providing MP filter coefficient tables which can be commonly used for analysis and synthesis. The signal analysis and synthesis filter bank of the present invention can reduce the calculation amount and the memory amount, and can realize a small filter bank with low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal analysis filter bank according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a signal synthesis filter bank according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a signal analysis or synthesis filter bank according to a third embodiment of the present invention.

FIG. 4 is a detailed block diagram showing the configuration of a cosine coefficient memory in an embodiment in which the memory amount of the present invention is reduced.

FIG. 5 is a block diagram showing configurations of a conventional signal analysis filter bank and signal synthesis filter bank.

FIG. 6A is a spectrum diagram showing a frequency amplitude response of a prototype filter, and FIG. 6B is a spectrum diagram showing a frequency amplitude response of a signal analysis or synthesis filter bank configured by performing frequency transition of the prototype filter.

[Explanation of symbols]

 11 First Operation Unit 12 Second Operation Unit 13 Input Signal Memory 14 First Intermediate Signal Memory 15 Subband Output Signal Memory 16 First Multiplier 17 First Filter Coefficient Memory 18 First Adder / Subtractor 19 First register 110 Second multiplier 111 First cosine coefficient memory 112 Second adder / subtractor 113 Second register 21 Third arithmetic unit 22 Fourth arithmetic unit 23 Subband input signal memory 24 Second intermediate signal memory 25 Output signal memory 26 Third multiplier 27 Second cosine coefficient memory 28 Third adder / subtractor 29 Third register 210 Fourth multiplier 211 Second filter coefficient memory 212 Fourth adder / subtractor 213 Fourth register 31 RAM 32,45 ROM 33 Multiplier 34 Adder / subtractor 35 Register 41 Rikae 42 remainder calculator 43 address register 44 adder

Continuation of the front page (56) References JP 63-6930 (JP, A) JP 63-303507 (JP, A) JP 2-13111 (JP, A) JP 61-177015 (JP , A)

Claims (9)

[Claims] 1. A signal analysis filter bank for dividing a signal having a sampling frequency f _s into M equal-bandwidth sub-band signals having a sampling frequency f _s / M, said signal analysis filter bank having a first value. 2MP (P
Is a positive integer) and is configured by frequency transition of a linear phase acyclic prototype filter having filter coefficients.
(L) (where 0 ≦ l ≦ 2MP−1), x (n) is the input signal at sampling time n, and w1 (k) is the first M intermediate signals (where 0 ≦ k ≦ M−1). ), When the output signal at the sampling time Mm of the i-th subband (where 0 ≦ i ≦ M−1) is y (i, Mm), (1) If M is an even number, (a) k = For 0, (B) When 1 ≦ k ≦ M / 2, (C) For M / 2 + 1 ≦ k ≦ M−1, A first arithmetic unit for calculating a first intermediate signal by And (2) if M is an odd number, (a) if 0 ≦ k ≦ (M−1) / 2, then: (B) For (M + 1) / 2 ≦ k ≦ M−1, A first arithmetic unit for calculating a first intermediate signal by And a second arithmetic unit for calculating a subband output signal according to the following. 2. M equal bandwidth sampling frequencies f _s
Sampling frequency f by synthesizing / M subband signals
A signal synthesis filter bank for reproducing the signal of _s ,
The signal synthesis filter bank is 2M with a first value of zero.
The prototype filter of the linear phase acyclic type having P (P is a positive integer) number of filter coefficients is configured by frequency transition, and the filter coefficient of the prototype filter is h (l) (where 0 ≦ l ≦ 2MP-1 ), Y (i, Mm) for the input signal at the sampling time Mm of the i-th sub-band (where 0 ≦ i ≦ M−1), and w2 (k) for 2MP second intermediate signals (where 0 ≦ k≤2MP-
1), sampling time Mm + n (where 0 ≦ n ≦ M
When the output signal in −1) is x ′ (Mm + n), the second intermediate signal w for 0 ≦ k ≦ 2MP-M−1
If 2 (k) is shifted to w2 (k + M), and (1) M is an even number, then And a third arithmetic unit for calculating a second intermediate signal for 0 ≦ k ≦ M−1, and (a) 0 ≦ n ≦ M / 2−1: (B) When n = M / 2, (C) For M / 2 + 1 ≦ n ≦ M−1, And (4) M is an odd number, And a third arithmetic unit for calculating a second intermediate signal for 0 ≦ k ≦ M−1, and (a) 0 ≦ n ≦ (M−1) / 2: (B) For (M + 1) / 2 ≦ n ≦ M−1, And a fourth arithmetic unit for calculating an output signal by the signal synthesis filter bank. 3. A signal analysis and synthesis filter bank, comprising the signal analysis filter bank according to claim 1 and the signal synthesis filter bank according to claim 2. 4. The signal analysis filter bank according to claim 1, wherein the second arithmetic unit includes M, 2M or 4M cosine coefficient tables. 5. The signal synthesizing filter bank according to claim 2, wherein the third arithmetic unit comprises M, 2M or 4M cosine coefficient tables. 6. The signal analysis filter bank according to claim 1, 3 or 4, wherein the first arithmetic unit includes MP filter coefficient tables. 7. The signal synthesizing filter bank according to claim 2, 3 or 5, wherein the fourth arithmetic unit comprises MP filter coefficient tables. 8. The signal analyzing and synthesizing filter according to claim 3, wherein the second arithmetic unit and the third arithmetic unit have M or 2M or 4M common cosine coefficient tables. bank. 9. The signal analyzing and synthesizing filter bank according to claim 3, wherein the first arithmetic unit and the fourth arithmetic unit are provided with MP common filter coefficient tables.