JPH0770696B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0770696B2
JPH0770696B2 JP63195487A JP19548788A JPH0770696B2 JP H0770696 B2 JPH0770696 B2 JP H0770696B2 JP 63195487 A JP63195487 A JP 63195487A JP 19548788 A JP19548788 A JP 19548788A JP H0770696 B2 JPH0770696 B2 JP H0770696B2
Authority
JP
Japan
Prior art keywords
area
metal wiring
circuit
light incident
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63195487A
Other languages
Japanese (ja)
Other versions
JPH0244770A (en
Inventor
芳雄 鶴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP63195487A priority Critical patent/JPH0770696B2/en
Publication of JPH0244770A publication Critical patent/JPH0244770A/en
Publication of JPH0770696B2 publication Critical patent/JPH0770696B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、同一半導体基板に集積した複数の半導体素子
の一部に光検知素子のような光感応素子を含む半導体集
積回路装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device including a photosensitive element such as a photodetector in a part of a plurality of semiconductor elements integrated on the same semiconductor substrate.

〔従来の技術〕[Conventional technology]

従来、光検知素子を応用した装置は、多く実用化されて
おり、それらはいずれも光検知部と信号処理回路とが別
々の容器に納められていたが、最近はシステムのコンパ
クト化,信号処理速度の向上等装置の性能を改善するた
めに光検知部と信号処理回路とを同一の基板上に作り込
んだ半導体集積回路装置として用いられるようになって
いる。
Conventionally, many devices applying photodetection elements have been put to practical use, and all of them had a photodetection section and a signal processing circuit housed in separate containers. Recently, however, the system has been made compact and signal processing has been performed. In order to improve the performance of the device such as an improvement in speed, it has been used as a semiconductor integrated circuit device in which a photodetector and a signal processing circuit are formed on the same substrate.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上記のような半導体集積回路装置において問題となるの
は、光が光検知素子以外の集積回路構成素子に入射した
とき、半導体内で本来は不必要な電子・正孔対を励起
し、そのため素子のリーク電流が増加する等の好ましく
ない現象が生ずることである。この現象は、アナログ回
路やダイナミック動作を行うデジタル回路においては大
きな問題となる。一例として、走査回路等に用いられ
る、ダイナミック型のMOSシフトレジスタについて考え
た場合、MOSトランジスタのゲート容量が一時的な情報
記憶として用いられるが、この部分に光が入射すると、
接合領域に発生する不必要な電子・正孔対によりリーク
電流が流れ、記憶時間を著しく短くすることになる。そ
の結果、リーク電流によって決まる時定数よりも低周波
動作のクロックパルスでは誤動作が発生する。
The problem with the semiconductor integrated circuit device as described above is that when light is incident on an integrated circuit constituent element other than the photo-sensing element, an originally unnecessary electron-hole pair is excited in the semiconductor, so that the element That is, an unfavorable phenomenon such as an increase in the leak current is generated. This phenomenon poses a serious problem in analog circuits and digital circuits that perform dynamic operations. As an example, when considering a dynamic type MOS shift register used for a scanning circuit or the like, the gate capacitance of a MOS transistor is used as temporary information storage, but when light enters this portion,
Leakage current flows due to unnecessary electron-hole pairs generated in the junction region, which significantly shortens the storage time. As a result, a malfunction occurs with a clock pulse operating at a lower frequency than the time constant determined by the leak current.

上述の問題の対策として、例えば特公昭52-26876号公報
に開示されているように、光検知素子以外の半導体素子
を含む領域上に導電性物質を絶縁膜を介して設ける方法
がある。この方法によって、不必要な電子・正孔対によ
るリーク電流等の問題を解決することができ、また、こ
の方法は通常のICプロセス工程と同じプロセスで形成で
きる等の長所もあるが、新たに次のような重大な欠点が
生じる。すなわち、導電性物質を半導体素子を含む領域
上に形成した場合、下層の金属配線との間に寄生容量を
形成してしまい、動作遅延を起こし誤動作を発生させる
可能性があるということである。特に、アルミニウム等
の金属配線は、抵抗率が低く、配線下の絶縁膜厚が厚い
故、半導体基板との寄生容量も小さいため、配線に長く
引き回され使用される場合が多いが、上層の光入射防止
膜とは配線面積に比例した分、寄生容量を形成してしま
う。また、配線アルミニウム上の絶縁膜は素子の保護膜
であることから、耐湿性の高い窒化けい素膜が用いられ
ることが多いが、これは7.5という高い比誘電率を有す
るため、このことも寄生容量を大きくする一因となって
いる。このように、金属配線が大きな寄生容量を持った
場合、高速動作を必要とする論理回路等においては動作
遅延を引き起こすため、誤動作が発生し素子が正常に働
かないという問題が起こる。
As a measure against the above-mentioned problem, for example, as disclosed in Japanese Patent Publication No. 52-26876, there is a method of providing a conductive material on a region including a semiconductor element other than a photodetection element via an insulating film. This method can solve problems such as leakage current due to unnecessary electron-hole pairs, and this method has the advantage that it can be formed in the same process as a normal IC process step. The following serious drawbacks occur. That is, when the conductive material is formed on the region including the semiconductor element, a parasitic capacitance is formed between the conductive material and the metal wiring in the lower layer, which may cause operation delay and malfunction. In particular, metal wiring such as aluminum has a low resistivity and a large insulating film thickness under the wiring, and thus has a small parasitic capacitance with the semiconductor substrate. The light incident prevention film forms parasitic capacitance in proportion to the wiring area. In addition, since the insulating film on the wiring aluminum is a protective film for the element, a silicon nitride film with high moisture resistance is often used, but this also has a high relative dielectric constant of 7.5, and this is also a parasitic factor. This is one of the reasons for increasing the capacity. As described above, when the metal wiring has a large parasitic capacitance, an operation delay occurs in a logic circuit or the like that requires high-speed operation, which causes a problem that a malfunction occurs and the element does not work normally.

さらに、他の問題点として、導電性物質を半導体素子を
含む広い領域上に形成すると、導電性物質を通して半導
体素子間に短絡事故が起こる可能性が発生する。このこ
とは半導体集積回路装置の製造歩留りを著しく低下させ
る。
Further, as another problem, when a conductive material is formed on a large area including a semiconductor element, a short circuit may occur between the semiconductor elements through the conductive material. This significantly reduces the manufacturing yield of semiconductor integrated circuit devices.

これら、寄生容量,短絡を補う方法として、本出願人の
特許出願に係る特願昭62-211952号明細書に第2図に示
す半導体集積回路装置が記載されている。図において、
同一半導体基板内に複数の光検知素子1が形成され、そ
れを囲んでアナログ回路およびダイナミック型のデジタ
ル回路2が、さらにその外側にデジタル回路3が集積さ
れている。そして、光検知素子1の存在する光検知領域
の回りのリーク電流の影響を受け易いアナログ回路およ
びダイナミック型のデジタル回路2の領域のみ絶縁膜を
介して導電性光入射防止膜4で覆われている。これによ
れば不必要な電子・正孔対によるリーク電流の問題もな
く、前記特公昭52-26876号公報に開示の方法に比較し
て、寄生容量の影響もなく、明らかに短絡の確率も小さ
くなって製造歩留まりが向上する。
As a method of compensating for these parasitic capacitance and short circuit, the semiconductor integrated circuit device shown in FIG. 2 is described in the specification of Japanese Patent Application No. 62-211952 filed by the present applicant. In the figure,
A plurality of photodetecting elements 1 are formed in the same semiconductor substrate, an analog circuit and a dynamic type digital circuit 2 are surrounded by the photodetecting element 1, and a digital circuit 3 is integrated outside thereof. Then, only the regions of the analog circuit and the dynamic type digital circuit 2 which are easily affected by the leak current around the photodetection region where the photodetection element 1 exists are covered with the conductive light incident prevention film 4 via the insulating film. There is. According to this, there is no problem of leakage current due to unnecessary electron-hole pairs, there is no influence of parasitic capacitance, and the probability of a short circuit is apparent, as compared with the method disclosed in Japanese Patent Publication No. 52-26876. The size is reduced and the manufacturing yield is improved.

しかしながら、この場合も新たに以下の問題が発生す
る。すなわち、第2図のように光検知素子1の回りにの
み光入射防止膜4を設けた場合、光入射防止膜4の外側
に入射した光により発生した電子・正孔対が光検知部ま
で拡散していき、光検知部で検知した正規の光量にバッ
クグラウンドとして乗ってしまうということである。電
子・正孔対の拡散長はIC基板内のライフタイムに依存す
るが大体10〜500μm程度あり、この影響を全く無くす
には、検知部以外の全ての領域を光入射防止膜で覆う必
要があるが、これが不可なことは前述したとうりであ
る。このバックグラウンドは雑音として各検知部での感
度のばらつきを引き起こす。その結果、第3図のように
光検知素子1を一列に配置したラインセンサの場合、均
一な光量を与えたにもかかわらず、第4図に示すように
バックグラウンドの影響で各センサの感度にばらつきが
発生する。
However, also in this case, the following problems newly occur. That is, when the light incident prevention film 4 is provided only around the light detection element 1 as shown in FIG. 2, electron-hole pairs generated by the light incident on the outside of the light incidence prevention film 4 reach the light detection portion. It means that the light diffuses and gets on the regular amount of light detected by the light detector as a background. The diffusion length of electron-hole pairs depends on the lifetime in the IC substrate, but it is about 10 to 500 μm, and in order to eliminate this effect at all, it is necessary to cover all regions except the detection part with a light incident prevention film. However, this is impossible, as mentioned above. This background causes variations in sensitivity among the detectors as noise. As a result, in the case of the line sensor in which the photo-sensing elements 1 are arranged in a row as shown in FIG. 3, the sensitivity of each sensor is affected by the background as shown in FIG. Variation occurs.

本発明の課題は、上記の各問題を解決し、光検知素子を
含む半導体集積回路装置の光による誤動作を防ぐための
光入射防止膜と配線部とが短絡する確率を抑え、かつ光
入射防止膜の外側に入射した光により発生した電子・正
孔対による光検知素子へのバックグラウンドの影響を無
くした半導体集積回路装置を提供することにある。
An object of the present invention is to solve the above problems and suppress the probability of short circuit between a light incident prevention film and a wiring portion for preventing malfunction of a semiconductor integrated circuit device including a photodetector due to light, and prevent light incident. It is an object of the present invention to provide a semiconductor integrated circuit device in which the influence of the background on the photo-detecting element due to electron-hole pairs generated by the light incident on the outside of the film is eliminated.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記の課題の解決のために、本発明は、同一基板内に集
積した複数の半導体素子の一部が光感応素子である半導
体集積回路装置において、光感応素子の形成される領域
をアナログ回路部およびダイナミック動作を行うデジタ
ル回路部を含む領域が二次元的に囲み、さらにその外側
を金属配線密度の均一でないデジタル回路部領域が二次
元的に囲み、アナログ回路部およびダイナミック動作を
行うデジタル回路部を含む領域の全部とその周辺部のデ
ジタル回路部領域の一部の上に絶縁膜を介して導電性光
入射防止膜が覆い、その際光入射防止膜の面積が金属配
線密度が大きいデジタル回路部領域上におけるより金属
配線密度の小さいデジタル回路部領域上で広いものとす
る。
In order to solve the above problems, the present invention provides a semiconductor integrated circuit device in which a part of a plurality of semiconductor elements integrated in the same substrate is a photosensitive element, and an area in which the photosensitive element is formed has an analog circuit portion. And an area including a digital circuit section that performs a dynamic operation is two-dimensionally surrounded, and a digital circuit section that does not have a uniform metal wiring density is two-dimensionally surrounded outside the analog circuit section and a digital circuit section that performs a dynamic operation. A digital circuit in which the conductive light incident prevention film covers the entire area including the area and a part of the peripheral digital circuit area through an insulating film and the area of the light incident prevention film is large in metal wiring density. It should be wide in the digital circuit area where the metal wiring density is smaller than in the partial area.

〔作用〕[Action]

本発明は光感応素子の設けられる領域の周りのリーク電
流の影響を受け易いアナログ回路およびダイナミック型
のデジタル回路の領域およびその周辺部のデジタル回路
部上を光入射防止膜で覆うが、その際金属配線が密集し
ている区域上に比して金属配線が疎の区域上の光入射防
止膜の領域を広く取ることにより、光入射防止膜で覆わ
れない領域では金属配線が疏の区域で金属配線が密集し
ている区域に比して発生する量の多い電子・正孔対の差
を補償し、バックグラウンドとして乗る電子・正孔対の
量を均一化し、各光検知部の感度ばらつきを抑えるよう
にしたものである。
The present invention covers the area of the analog circuit and the dynamic type digital circuit, which is easily affected by the leak current around the area where the photosensitive element is provided, and the digital circuit section in the peripheral area thereof with the light incident prevention film. By making the area of the light incident prevention film on the area where the metal wiring is sparse as compared to the area where the metal wiring is dense, the area where the metal wiring is Compensate for the large difference in electron / hole pairs generated compared to the area where metal wiring is dense, equalize the amount of electron / hole pairs to be carried as the background, and vary the sensitivity of each photo detector. It is intended to suppress.

なお、バックグラウンドとして乗る電子・正孔対の光量
依存性は光検知部で発生する正規の電子・正孔対の光量
依存性と同じなので、バックグラウンドとして微小量が
均一に乗る場合は何ら問題はない。
Note that the light quantity dependency of the electron / hole pair that is used as the background is the same as the light quantity dependency of the regular electron / hole pair that is generated in the photodetector, so there is no problem if a small amount of light is uniformly distributed as the background. There is no.

〔実施例〕〔Example〕

第1図に本発明の一実施例を示し、第2図,第3図と共
通の部分には同一の符号が付されている。素子の配置は
第3図と同一でラインセンサを形成する光検知素子1を
とりまく半導体基板領域にアナログ回路およびダイナミ
ック型デジタル回路2が設けられ、さらにその外側にデ
ジタル回路が設けられているが、デジタル回路の金属配
線密度が同一でなく、金属配線密度の大きいデジタル回
路31と小さいデジタル回路32がある。光検知素子1の領
域以外の領域でアナログ回路部およびダイナミック型の
デジタル回路部2の領域を絶縁膜を介して導電性光入射
防止膜4で覆い、さらにその光入射防止膜4をその周辺
部のデジタル回路部31,32の一部上まで延長している。
この場合、周辺のデジタル回路部領域においては、金属
配線密度が低い領域32上では、密度の高い領域31上より
斜線でハッチングした光入射防止膜4の面積を大きくす
る。
An embodiment of the present invention is shown in FIG. 1, and the same parts as those in FIGS. 2 and 3 are designated by the same reference numerals. The arrangement of the elements is the same as that shown in FIG. 3, and the analog circuit and the dynamic digital circuit 2 are provided in the semiconductor substrate region surrounding the photo-sensing element 1 forming the line sensor, and further the digital circuit is provided outside thereof. There is a digital circuit 31 having a high metal wiring density and a digital circuit 32 having a low metal wiring density. In a region other than the region of the light detecting element 1, the regions of the analog circuit portion and the dynamic type digital circuit portion 2 are covered with a conductive light incident prevention film 4 via an insulating film, and the light incident prevention film 4 is further surrounded by the conductive light incident prevention film 4. It extends to a part of the digital circuit parts 31, 32 of.
In this case, in the peripheral digital circuit area, the area of the light incident prevention film 4 hatched with diagonal lines is made larger on the area 32 having a lower metal wiring density than on the area 31 having a high density.

このようにすることにより、光入射防止膜で覆われてい
ない領域に入射した光は電子・正孔対を作るが、金属配
線密度が高い領域では、金属配線により光が遮られる基
板内に発生する単位面積当たりの電子・正孔対の発生頻
度が金属配線密度の低い領域より小さい。また、金属配
線密度の低い領域では単位面積当たりの電子・正孔対の
発生頻度は大きいが、防止膜で覆われていない面積が密
度の高い領域より小さいので、この効果により結果とし
て電子・正孔対は同程度となり、均一なバックグラウン
ドになる。その結果、第5図に示すように各センサの感
度は均一性が向上する。
By doing this, light incident on the area not covered by the light incident prevention film forms electron-hole pairs, but in areas where the metal wiring density is high, light is generated inside the substrate where the light is blocked by the metal wiring. The frequency of generation of electron-hole pairs per unit area is smaller than that in the region where the metal wiring density is low. In addition, in regions where the metal wiring density is low, the frequency of generation of electron-hole pairs per unit area is high, but since the area not covered by the protective film is smaller than in the regions where density is high, this effect results in electron-positive pairs. The hole pairs are comparable and have a uniform background. As a result, the sensitivity of each sensor is improved in uniformity as shown in FIG.

この光入射防止膜の覆う面積比は、おおむね配線密度比
の逆数で求められるが実際は種々のパターンを用意し、
実際に感度ばらつきを測定し最良のパターンを求めるの
が望ましい。
The area ratio covered by this light incident prevention film is generally calculated by the reciprocal of the wiring density ratio, but in reality various patterns are prepared,
It is desirable to actually measure the sensitivity variation and find the best pattern.

なお、光入射防止膜4は回路配線等に使用されるアルミ
ニウム,モリブデン,ダングステン等で窒化けい素膜な
どの上に形成でき、通常のICプロセス工程と同じプロセ
スを利用することができる。
The light incident prevention film 4 can be formed on a silicon nitride film or the like using aluminum, molybdenum, dangsten or the like used for circuit wiring or the like, and the same process as a normal IC process step can be used.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明によれば、通常プロセスで
容易に形成できる光入射防止膜を電子・正孔対によるリ
ーク電流の影響を受け易いアナログ部およびダイナミッ
ク型のデジタル部の領域上、さらにその周辺のデジタル
回路部の一部の領域上に設け、その際デジタル回路部の
金属配線密度の高い領域上の光入射防止膜の面積を、金
属配線密度の低い領域上の光入射防止膜の面積より小さ
くすることにより、光によるリーク電流の影響,高速動
作を行うデジタル回路部への寄生容量の影響および短絡
事故の確率等を抑え、かつ光感応素子部へのバックグラ
ウンドを均一化し感度ばらつきを抑えることができるの
で、安定して動作する高性能の半導体集積回路装置を実
用に供することが可能となる。
As described above, according to the present invention, the light incident prevention film that can be easily formed by the normal process is provided on the area of the analog section and the dynamic type digital section which are easily affected by the leak current due to the electron-hole pair. It is provided on a part of the area of the digital circuit part around it, and at that time, the area of the light incident prevention film on the region of the digital circuit part where the metal wiring density is high is By making it smaller than the area, the influence of leakage current due to light, the influence of parasitic capacitance on the high-speed operation digital circuit, the probability of short-circuit accident, etc. are suppressed, and the background to the photo-sensitive element is made uniform and the sensitivity varies. Therefore, it is possible to put into practical use a high-performance semiconductor integrated circuit device that operates stably.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例の半導体集積回路装置の平面
図、第2図は既出願の半導体集積回路装置の平面図、第
3図は第2図の装置の構成をラインセンサに適用した場
合の平面図、第4図は第3図の装置の各光センサの感度
の分布図、第5図は第1図の実施例の各光センサの感度
の分布図である。 1:光検知素子、2:アナログ回路およびダイナミック型デ
ジタル回路、31:金属配線密のデジタル回路、32:金属配
線疎のデジタル回路、4:光入射防止膜。
FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor integrated circuit device of an already-filed application, and FIG. 3 is an apparatus configuration of FIG. 2 applied to a line sensor. FIG. 4 is a plan view in the case of doing so, FIG. 4 is a sensitivity distribution diagram of each optical sensor of the apparatus of FIG. 3, and FIG. 5 is a sensitivity distribution diagram of each optical sensor of the embodiment of FIG. 1: Photodetector, 2: Analog circuit and dynamic digital circuit, 31: Digital circuit with dense metal wiring, 32: Digital circuit with sparse metal wiring, 4: Light incident prevention film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】同一基板内に集積した複数の半導体素子の
一部が光感応素子であるものにおいて、光感応素子の形
成される領域をアナログ回路部およびダイナミック動作
を行うデジタル回路部を含む領域が二次元的に囲み、さ
らにその外側を金属配線密度の均一でないデジタル回路
部領域が二次元的に囲み、アナログ回路部およびダイナ
ミック動作を行うデジタル回路部を含む領域の全部とそ
の周辺部のデジタル回路部領域の一部の上に絶縁膜を介
して導電性光入射防止膜が覆い、その際光入射防止膜の
面積が金属配線密度が大きいデジタル回路部領域上にお
けるより金属配線密度の小さいデジタル回路部領域上で
広いことを特徴とする半導体集積回路装置。
1. A device in which a part of a plurality of semiconductor elements integrated on the same substrate is a photosensitive element, an area in which the photosensitive element is formed includes an analog circuit section and a digital circuit section which performs a dynamic operation. Is surrounded in a two-dimensional manner, and the outside is surrounded by a digital circuit area in which the metal wiring density is not uniform, and the entire area including the analog circuit section and the digital circuit section that performs dynamic operation and its peripheral area are digital. A part of the circuit area is covered with a conductive light incident prevention film through an insulating film, and the area of the light incident prevention film has a large metal wiring density. Digital with a smaller metal wiring density on the digital circuit area. A semiconductor integrated circuit device having a large area on a circuit area.
JP63195487A 1988-08-05 1988-08-05 Semiconductor integrated circuit device Expired - Lifetime JPH0770696B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63195487A JPH0770696B2 (en) 1988-08-05 1988-08-05 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63195487A JPH0770696B2 (en) 1988-08-05 1988-08-05 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0244770A JPH0244770A (en) 1990-02-14
JPH0770696B2 true JPH0770696B2 (en) 1995-07-31

Family

ID=16341905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63195487A Expired - Lifetime JPH0770696B2 (en) 1988-08-05 1988-08-05 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0770696B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252338A (en) * 2000-12-18 2002-09-06 Canon Inc Imaging device and imaging system
JP4907034B2 (en) * 2001-05-31 2012-03-28 マグナチップセミコンダクター有限会社 CMOS image sensor

Also Published As

Publication number Publication date
JPH0244770A (en) 1990-02-14

Similar Documents

Publication Publication Date Title
US5440130A (en) X-ray imaging system and solid state detector therefor
US4905265A (en) X-ray imaging system and solid state detector therefor
EP0096725B1 (en) Semiconductor image pick-up device
US7755679B2 (en) Apparatus and method for reducing edge effect in an image sensor
JP3319419B2 (en) Solid-state imaging device
AU7322091A (en) X-ray imaging system and solid state detector therefor
US4791468A (en) Radiation-sensitive semiconductor device
US5355013A (en) Integrated radiation pixel detector with PIN diode array
US5254868A (en) Solidstate image sensor device
US4078243A (en) Phototransistor array having uniform current response and method of manufacture
US6278169B1 (en) Image sensor shielding
US5336919A (en) Solid-state image pickup device with high melting point metal shield
EP0023656B1 (en) Charge storage type semiconductor device
JPH09511361A (en) Electromagnetic radiation imager using dual gate thin film transistor
JPH0661471A (en) Ccd imager provided with tset structure and test method of ccd imager
Marczewski et al. SOI active pixel detectors of ionizing radiation-technology and design development
JPH0770696B2 (en) Semiconductor integrated circuit device
JPH07114270B2 (en) Semiconductor integrated circuit device
JPS60241277A (en) Semiconductor device
JP3426872B2 (en) Optical semiconductor integrated circuit device and method of manufacturing the same
JPS63316471A (en) Semiconductor integrated circuit device
US7271390B2 (en) Imaging systems and methods including an alternating pixel arrangement
JP2676814B2 (en) Multi-type light receiving element
JP3375389B2 (en) Charge detection element
JP3487069B2 (en) Semiconductor light receiving element