JPH0770672B2 - Semiconductor package - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and particularly to packaging of a semiconductor device, which is suitable for application to an interposer module disposed between a semiconductor and an interconnection substrate.

[0002]

2. Description of the Related Art It has come to be used to mount a number of integrated circuit chips on a common substrate and interconnect the substrates to the chips via input / output contact lands. This shared substrate includes printed wiring and a multilayer ceramic sheet with multiple biases, with the biases selectively interconnecting the printed wiring in the various layers. When it is necessary to modify the internal circuitry in this type of board, it is often necessary to correct imperfect lines and / or biases and adapt the modification in the circuit to the design changes to the semiconductor chip. It is being appreciated.

In the past, a number of techniques have been proposed to change the layout of the chip or module package according to the processing technique. U.S. Pat. No. 4,489,364 describes a chip-holding module in which the chip-holding module includes a process modification line embedded within the module. The modified line of such processing is interrupted at predetermined intervals and connected to a set of biases extending to the surface portion of the module between the mounting chips.
The biases are interconnected by dumbbell pads containing thin links. By sequentially removing links with a laser, circuit lines are disconnected and other dumbbell pads are interconnected by new wiring.

Another technique for processing modification uses an interposer module between the semiconductor chip and the underlying ceramic substrate. U.S. Pat. No. 4202007
No. 5,837,049 shows an interposer module supporting a semiconductor chip having bump-shaped contacts. The interposer module interconnects these contacts to contact lands on the main board via internal wiring. The modification by processing is done by modifying the internal wiring in the interposer module.

A similar interposer module is shown in US Pat. No. 4,803,595. In this case, X
By using an interposer module having a wiring surface and a Y wiring surface, modification pads due to processing and individual wiring are avoided. Modifications by processing are made by selectively removing interconnects within the interposer module. In addition, short-circuit jumper formation techniques have been adapted to form new internal interconnects by being applied between proper internal wiring planes and vias. U.S. Pat. No. 4,803,595 also shows the use of a decoupling capacitor mounted on the surface of an interposer structure adjacent to a semiconductor chip supported on that surface. The decoupling capacitor is connected to internal wiring in the interposer.

A number of documents describing various interposer structures can be found in the "IBM Technical Publication Report". Issue 5, October 1975, Vol. 18, page 1440,
Page 1441 shows an interposer structure with a correction pad on the top surface that can be modified by machining. 19
The interposer structure is shown in Vol. 9, No. 24, February 1982, pages 4637 and 4638. Here, it is shown that the modification can be performed by combining with the modification pad on the surface of the shared substrate that supports the interposer. In addition, Issue 4, September 29, Vol. 29, 169
On pages 4 and 1695, an interposer type modification method using a replacement interposer is shown. The interposer described in this document uses unused bump lands on a chip to connect them to a process modification channel embedded in a shared substrate. The X and Y processing change means in which the processing change wiring in the interposer is embedded is used. Issue 9, February 1984, Vol. 26, pages 4590, 4591, shows a pair of interposers supporting around a main chip with auxiliary chips mounted below and between the interposers. Issue 8 January 27, Vol. 27 46
At pages 72 and 4673, another interposer is shown including a signal redistribution network that reduces the number of required ceramic layers in a shared support module. 1987
Issue 4, September 30, 1868, 1787,
It is shown to include a decoupling capacitor interconnected to the end of the interposer chip retention module. These capacitors provide decoupling action within the module.

Moreover, it is known that decoupling capacitors are often required in electronic packaging. It is desirable to place the decoupling capacitor as close as possible to the semiconductor chip. In U.S. Pat. No. 4,328,530, such a decoupling capacitance is placed in a notch in the board so that the capacitance is placed as close as possible for soldering between the chip and the board. To do. The stack of the laminated ceramic capacitor is inserted into the slot and treated as a power plane. Other Patent No. 4
No. 3,498,62 describes that a chip retention module is located internally with respect to the module between the biases interconnecting the decoupling capacitors. Also, U.S. Pat. No. 4,349,862 (FIG. 2) shows the use of an interposer module for supporting a semiconductor wafer and placing a decoupling capacitor thereon. In addition, U.S. Pat. No. 4,744,007 shows another electronic packaging technique involving decoupling capacitance. In this example, the decoupling capacitance is electrically connected to the input / output contacts of the semiconductor chip, and is connected to the capacitance that is mounted under the chip like individual devices.

[0008]

More powerful and faster computers allow interconnections between chips with more chips and shorter interconnection lengths. Therefore, it is important to reduce the distance between chips while maintaining the wiring ability of the substrate. Modification techniques that use the surface area of the substrate or by processing that reduces the wiring capability of the substrate destroys the optimal package target. Thus, the interposer process modification technique having the capacitor interposer by the modification technique using the surface-mounted decoupling capacitor or the wiring in the substrate is still insufficient.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a module in which integrated circuit chips are mounted on a common ceramic substrate by being entirely arranged in a plane. Another object of the present invention is to improve an interposer module that supports semiconductor chips on a shared ceramic substrate. Yet another object of the present invention is to provide an interposer module having capacitance that decouples to a given overall shape within the module. Yet another object of the present invention is an interposer module having the ability to be modified by processing provided by X and Y interconnect lines that are selectively connected to a bias within the module or isolated from the bias within the module. Is to provide.

[0010]

SUMMARY OF THE INVENTION To solve this problem, the present invention provides a semiconductor package for supporting and interconnecting semiconductor chips, each chip having a contact land on a contact surface, the package at least A substrate 54 having a contact surface and an interposer module 50 disposed between one chip contact surface and a substrate contact surface, the interposer module 50 having first and second opposing surfaces, the chip contact land. A first plurality of contacts on a first surface positioned to match with a second surface on a second surface positioned to match a contact land on the substrate.
The plurality of contacts and the first plurality of contacts to the second
A set of conductive biases in interposer module 50 for connecting to a first subset of a plurality of contacts of the interposer and distributed capacitive means positioned in interposer 50 and an adjacent first surface. To

[0011]

The semiconductor package is shown as supporting and interconnecting semiconductor chips, each chip having a contact land on a contact surface, the package also including a substrate having a contact surface. The interposer module is disposed between the contact surface of at least one chip and the contact surface of the substrate. The interposer module has first and second opposing surfaces and a first plurality of contact locations positioned on the first surface thereof that match the contact lands of the chip. A second plurality of contact locations on the second surface of the interposer module are positioned to match contact lands on the substrate. 1
A set of conductive biases is positioned within the interposer module to connect the first plurality of contact locations with the first subset of the second plurality of contact locations. The distributed capacitance layer is positioned within the interposer and is adjacent to its first surface.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 generally shows an interposer module 50, which supports an LSI circuit chip 52 and is mounted on a ceramic interconnect substrate 54. Silicon chip 52 and interposer module 50 are each bonded to a support surface by solder balls 56. The interposer module 50 forms on its upper surface a voltage distribution plane 58 separated by a decoupling capacitance layer. On the lowermost surface of the interposer 50, a processing change wiring layer connected to various solder balls 56 is provided.

The connections between interposer modules 50 are made by peripheral solder balls 62 and interconnect lines below the surface in substrate 54. Of particular note is
By forming an interposer module between the chip 52 and the ceramic substrate 54, the exposed surface area of the substrate can be utilized to the maximum extent to provide a dense packaging configuration. Substrate 54 is a multi-layer glass ceramic structure including circuit patterns disposed therebetween. Structures and suitable processes for producing such substrates are described in US Pat. Nos. 4,301,324 and 42343.
No. 67.

Similarly, the interposer module 50 is constructed with a multilayer glass ceramic structure and includes a thin film intermediate layer of a conductive metal circuit that provides both process modification capability and voltage distribution. A plurality of biases 64 carry signals between particular ones of the upper and lower solder balls 56, 56. FIG. 2 shows a cross-sectional view of interposer module 50. A plurality of solder ball cavities 70, 72 are formed in the upper polyimide surface 74 on the interposer module 50. The solder ball cavities (eg, 70) are electrically connected to the upper voltage distribution layer 76 and the other solder balls are directly interconnected to the bias 78. Bias 78 passes through but does not interconnect with openings 80 in voltage distribution layer 76. Such biases are used during signal interconnection between the top and bottom of interposer module 50.

The lower voltage distribution layer 84 is the upper voltage distribution layer 7.
6 and is separated from the lower voltage distribution layer 84 by a dielectric layer 86. The dielectric layer 86 can provide a decoupling capacitance underneath the solder ball cavity 70 by forming a distributed capacitance between the voltage distribution layers 76 and 84. Each cavity 70 is connected to the upper voltage distribution layer 76. By connecting the bias 90 to the lowermost surface of the upper voltage distribution layer 76, the upper voltage distribution layer 76 can be connected to both the uppermost surface and the lowermost surface of the interposer module 82. The bias connected to the lower voltage distribution layer 84 is not shown as having a cross section different from that shown in FIG.

The body 92 of the interposer module is shown in FIG.
It is composed of the same glass ceramic as the interconnection module 54 of FIG. On the bottom surface of the interposer module 50 is a conductive ground plane 94, which has a hole 96 through the biases 78 and 90. Each bias 78 and 90 contacts an underlying solder ball cavity 98, 100, respectively. The cavities 98, 100 are interconnected by extending at right angles into the modified wiring layer 60. The processing modified wiring layer 102 is connected to the peripheral solder ball cavities 106 in the range from the leftmost part to the rightmost part of the interposer module 50, but the processing modified wiring layer 104 is from the innermost part to the outermost part of the interposer module 50. Contact with similar solder ball cavities (not shown) in the range. The surrounding solder ball cavities 106 connect to the work modification layer but not to the bias (thus providing work modification capability when connected to the proper bias via metal or wire deposited in the work modification layer).

As shown in FIG. 1, the interposer module 50 is provided.
Of the solder balls 56 on the upper surface of the substrate 54 by mounting the solder balls on the substrate 54.
It is designed to match 00. Solder balls 56 and solder ball cavities 98 due to the following reflow operation,
The 100 can be electrically interconnected. When processing changes are required, one or more solder balls 56 on the substrate 54 are removed to break the interconnection with the solder cavities (eg, 98 in FIG. 2) and the deposited metal is removed from FIG. By connecting to the appropriate machining change line 102 or 104, the interconnection for machining change can be performed. The chip 52 is an upper solder ball cavity 70,
72 and so on. Thus, multiple chips, interposer modules and interconnect substrate interconnections can be completed by reflowing the entire system simultaneously.

3 and 4 show a pair of X and Y process modification interconnect layers. FIG. 4 is a cross-sectional view taken along the line 4-4 of FIG. The X layer 102 is composed of a plurality of X-direction conductor lines 110 and interconnects to either end of an interposer module having a modified solder cavity 112. The bias subset is adapted to match the simultaneous interconnect tabs on the X process modified conductors by providing interconnect tabs 114. further,
This bias also provides an interconnect tab 116 that provides interconnect capability to the Y-direction modification line 120. Each Y
The redirection line 120 is connected to the solder cavity 122 at either tip thereof. Some bias (eg 12
4, 126) are not provided with tabs 114 and / or 116 and thus do not have the ability to modify. The X and Y modification layers 102 and 104 are manufactured by conventional sequence processing techniques of a thin film multi-layer metallization technique using a chromium-copper-chromium metallization separated by a polyimide dielectric. The X and Y process change layers 102 and 104 are manufactured by the transfer and adhesion technique described below.

To reroute the wire from one solder cavity to another, the tabs 114 or 116 are interconnected so that only one of the two solder cavities connected to the X or Y line can be connected to X. Either the line or the Y line is cut. For example, when rewiring a wire from solder cavity 130 to modified solder cavity 122, a metal tab 132 may be used by using a laser.
The polymeric material overlying the can be removed. The laser enhances copper deposition by chemical vapor deposition and then uses wire straps to bond the tabs 132 together. A notch 134 is made in line 136 because only the pad 112 is connected,
As a result, the solder cavity (not shown) on the side separated from the solder cavity 112 is blocked. The interconnection is completed by removing the solder cavities 130 beneath the solder balls. The cavities 112 are interconnected to adjacent interposer modules 50 by interconnecting surface connections on the substrate 54 or wiring below the surface of the substrate. Similar connections in other suitable interposer modules complete the other end of the line. The crossing angle of the X and Y wirings is a right angle. A laser is used to remove the layer of polymeric material covering the line and the metal placed to connect the line. The Y-level interconnect is similar to the X interconnect described above. Thus, the tabs 114, 116 and the surrounding solder cavities 112 allow a significant number of processing changes, and to a large extent avoid the need for changes to the internal wiring within the substrate 54.

5 to 12 show steps necessary for manufacturing the voltage distribution layer 58. The lower voltage distribution layer 84 is shown in FIGS. The voltage distribution layer 84 is made of a conductive metal and can distribute the voltage V1. The metal layer 84 is deposited on the top surface of the interposer module 50, which is the glass ceramic portion. The signal bias S and the voltage biases V2 and V3 (see FIG. 6) are provided by the etched toroidal conductor free region 152 to the metal layer 84.
To a conductive region that is separated from. As shown in FIG. 5, the voltage bias 154 (V1) is connected to the lower side of the conductive metal layer 84 to provide the voltage V1. As shown in FIGS. 7 and 8, a dielectric layer 160 is then deposited over the conductive metal layer 84 and masked so that the toroidal region 152 is a conductive region on V2, V3 and the signal bias S. Stay with.

Thereafter, as shown in FIGS. 9 and 10, the second
A metal layer 162 is deposited over the insulating layer 160.
In this embodiment, the metal layer 162 is masked so that it is added so that it does not short circuit the signal bias S and fills the V2 and V3 regions with conductive regions. Thus, the conductive layer 162 covering the bias V2 becomes a capacitor plate having a voltage V2. Also, a conductive layer 162 covering a bias having a voltage V3 as well.
Form a capacitor plate, which in this example is powered up to the V3 level. When the conductive layers 162 are deposited, the added conductive layers are placed on the signal bias S to grow their upper surfaces 164 to the same level as the upper layers of the insulating layer 160.

The second metal treatment layer 16 is shown in FIGS. 11 and 12.
Following deposition of 2, polyimide layer 170 is shown to be deposited over the surface of the interposer module. As shown in FIG. 12, the polyimide layer 170 is masked and the opening is etched to expose the underlying conductive surface. The metallization layer added at that point is deposited within the etched openings to form solder ball cavities 172, 174, and 176. Cavity 174 connects to the top surface of the bias of signal S, so that cavities 172 and 176 are in contact with conductive layer 162 in contact with voltage biases V2 and V3, respectively.
Contact with. In this approach, individual voltages are drawn to the top surface of the interposer module 50 while at the same time preserving decoupling capacitance between the voltage distribution layers.

13 and 14 show a transfer layer manufacturing process for a process change line. FIG. 13 shows the Y process changing conductive transfer layer 200. Transfer layer 200 is composed of a suitable conductive metal, such as copper, and includes a metal ring 202 at each bias site, which ring ultimately contacts the conductive bias. As shown in FIG. 14, the transfer layer 200
Are mounted on a polyimide layer 204, each supported by a light emitting layer 206. The quartz plate 208 is treated as a temporary carrier for the above structure. As can be seen, the laser is scanned through the quartz plate 208 and the light emitting layer 2 is scanned.
The transfer layer can be transferred to the glass ceramic body of the interposer module 50 by using 06 to operate.

The second polyimide layer 2 is shown in FIGS.
10 is attached to cover the Y conductive transfer layer 200, and the X process changing conductive transfer layer 212 is attached to the second polyimide layer 210.
To be attached to. The metal ring 214 is registered with the underlying metal ring 202. 17 and 18, the added polyimide layer 216 is the X wiring transfer layer 212.
Shows that a ground plane 218 is deposited over and is placed on the additional polyimide 216. Etching the ground plane 218 leaves a donut-shaped region to expose the underlying polyimide layer 216 (see FIG. 17).
The central portion of the donut-shaped opening is retained to form an interconnection point for biasing (its structure will be described later).

The transfer of the transfer layer structure shown in FIG. 18 is carried out by installing a ground plane 218 covering the matching metal surface on the surface of the glass ceramic interposer substrate 92 and releasing the light emitting layer 206 by exposure of the film. Will be realized.
A cross section of this structure is shown in FIG. After transfer of the transfer layer film, holes 220 are created to expose the conductive areas and become a toroidal portion of conductive layer 218. Each hole is then metallized to provide a solder ball cavity.

The ability to make processing modifications to the structure described above can be increased. Also, the X and Y wires are used to pass through the long lines of each interposer module, thus depleting the ability to connect solder balls. This problem can be mitigated by adding a line added to each wiring channel as shown in FIG. Instead of providing a single X and / or Y modification line through the channels, a pair of conductor lines runs through each channel. In addition, the peripheral solder ball cavities 254 and 256 have conductors 2 at their opposite ends.
Providing 50 and 252, respectively, essentially doubles the process modification capability when all channels include a pair of conductor lines. Although the present invention has been particularly shown and described based on the preferred embodiments thereof as described above, various changes may be made in both form and detailed structure without departing from the spirit and scope of the present invention.

[0028]

As described above, by providing an interposer module that combines the function of the voltage distribution type decapping capacitor and the function of the ability to change by important processing, an entirely high density chip is provided. Can be placed. Such a structure makes it possible to reach extremely low inductances suitable for the fastest bipolar circuits. The given modification capability has little effect on the substrate wiring capacitance, and it is possible to avoid modification on a substrate that needs to be modified by machining.

[Brief description of drawings]

FIG. 1 is a schematic side view showing an outline of a semiconductor package to which the present invention is applied.

FIG. 2 is a cross-sectional view showing an outline of an interposer module to which the present invention is applied.

FIG. 3 is a plan view showing a wiring layer for making changes by X and Y processing in the interposer module.

4 is a cross-sectional view taken along line 4-4 of FIG.

FIG. 5 is a plan view showing a first capacitive metal layer in the interposer module.

6 is a sectional view taken along the line 6-6 in FIG.

FIG. 7 is a plan view showing a capacitive dielectric layer in an interposer module.

8 is a cross-sectional view taken along the line 8-8 of FIG.

FIG. 9 is a plan view showing a second capacitive dielectric layer in the interposer module.

10 is a cross-sectional view taken along the line 10-10 of FIG.

FIG. 11 is a plan view showing a capacitive layer after disposing a passivation layer and a contact metal treatment on the capacitive layer.

12 is a sectional view taken along the line 12-12 in FIG.

FIG. 13 is a plan view showing a transfer layer used for manufacturing a Y-direction line for processing modification.

14 is a sectional view taken along the line 14-14 of FIG.

FIG. 15 is a plan view in which the transfer layer line for X processing change in the interposer module is arranged on the transfer layer line for Y processing change.

16 is a cross-sectional view taken along the line 16-16 of FIG.

FIG. 17 is a plan view showing the reference voltage plane after the X and Y transfer layer lines have been installed.

FIG. 18 is a cross-sectional view taken along line 18-18 of FIG. 17 showing the modification layer manufactured prior to transfer.

FIG. 19 is a plan view showing a contact hole that has been metallized by making a hole after transfer of the transfer layer.

20 is a cross-sectional view taken along the line 20-20 of FIG.

FIG. 21 is a plan view in which the arrangement of the wiring transfer layer which gives the interposer module the added processing change ability is changed.

[Explanation of symbols]

50 ... Interposer module, 52 ... LSI circuit chip, 54 ... Ceramic interconnection substrate, 56 ... Solder ball, 58 ... Voltage distribution surface, 60 ... Processing change wiring layer, 62, 106 ... Surrounding solder Ball, 64, 9
0, 124, 126 ... Bias, 70, 72 ... Solder ball cavity, 74 ... Upper polyimide surface, 76 ... Upper voltage distribution layer, 78 ... Bias, 80 ... Opening, 82
...... Bottom surface, 84 ...... Lower voltage distribution layer, 86 …… Dielectric layer, 92 …… Interposer module body, 94 ……
Conductive ground plane, 96, 220 ... hole, 98, 10
0, 172, 174, 176 ... Solder ball cavity, 1
02,104 ... Processing change wiring layer, 110 ... X direction conductor line, 112 ... Processing change solder cavity, 114,1
16 ... Interconnection tab, 120 ... Y direction processing change line, 122, 130 ... Solder cavity, 132 ... Metal tab, 134 ... Notch, 136 ... Line, 150 ...
Conductive region, 152 ... Conductor free region, 154 ... Voltage bias, 160 ... Insulating layer, 162 ... Metal layer, 16
4 ... Top surface, 170 ... Polyimide layer, 200 ... Y
Processing change Conductive transfer layer, 202, 214 ... Metal ring, 204 ... Polyimide layer, 206 ... Light emitting layer, 2
08 ... Crystal plate, 210 ... Second polyimide layer, 212
...... X processing change conductive transfer layer, 216 ... added polyimide layer, 218 ... ground plane, 250,252 ... conductor, 254,256 ... peripheral solder ball cavity.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Evan Ezra Debittson, New York, USA 12533, Hopewell Jianxillon, Mountain Path Road 18 (72) Inventor Timothy Rare Dainger, New York, USA 10520 , Croton-on-Hudson, North Highland Place 110 (72) Inventor Debited Bryan Goland United States, New York, 10507, Bethdoff Ord Hills, Bethdoff Road, 425 (72) Invented Debited Paul Lapotin 2 Meadow Road, Carmel, 10512 New York, USA

Claims (10)

[Claims] 1. A semiconductor package for supporting and interconnecting semiconductor chips, each chip having a contact land on a contact surface, said package also being disposed between at least one chip contact surface and a substrate contact surface. A substrate having an exposed contact surface and an interposer module, the interposer module having first and second opposing surfaces, the first surface on the first surface positioned to match the contact land of the chip. One contact, a second plurality of contacts on the second surface positioned to match a contact land on the substrate, the first plurality of contacts to the second plurality of contacts. A set of conductive biases in the interposer module for connecting to a first subset of Semiconductor bobbin, characterized in that it comprises the above-described interposer and positioned adjacent to said first inner surface distributions capacitive means. 2. A second subset of the second plurality of contacts is disposed about the first subset, and further the contacts of the second subset of contacts are selected with the conductive bias. 2. The semiconductor package according to claim 1, further comprising electrically connecting conductor means. 3. In the conductor means, the lines of the first layer and the second layer, which are spaced apart from each other, are conductive lines which are substantially parallel and orthogonal to each other, and the lines of the second plurality of contact positions are formed. 3. The semiconductor package according to claim 2, comprising the line connected to the second subset. 4. Each of the parallel conductive lines passes through a plurality of adjacent conductive biases and can be selectively interconnected with some of the biases so that the biases are in the second.
4. The semiconductor package of claim 3, wherein the semiconductor package is capable of interconnecting with some of the second subset of contacts. 5. Each of the parallel conductive lines connects to the pair of second subsets of the second plurality of contacts and can be selectively cut off therefrom to provide a bias of the second plurality of contacts. A semiconductor package according to claim 4, characterized in that it can be interconnected with only one of the two subsets. 6. A first voltage distribution surface connected to some bias selected from the bias, and a second voltage distribution surface connected to the other bias of the bias.
The semiconductor package according to claim 5, further comprising a conductive voltage distribution surface and a dielectric layer between the voltage distribution surfaces. 7. The semiconductor package according to claim 6, wherein the first voltage distribution surface cuts individual segments connected to separate the voltage bias. 8. The semiconductor package according to claim 7, wherein the first and second voltage distribution planes provide a gap through which a signal transmission bias extends. 9. A plurality of solder ball receiving cavities within said first facing surface of said interposer module and a selected ball cavity of said solder ball cavities in contact with said first voltage distribution surface. 9. The semiconductor package of claim 8 including selected cavities, said other cavity in contact with said second voltage distribution plane segment, and said other cavity in contact with a signal bias. 10. A plurality of parallel conductive lines are positioned between rows of conductive vias, each conductive line being connected to a contact of the pair of second subsets. Item 6. The semiconductor package according to item 5.