JPH0766851B2 - I / O pin repair method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A method of repairing an I / O pin that is applied when repairing an I / O pin arranged on a ceramic substrate. A repair substrate provided with at least three I / O pin insertion holes provided corresponding to the arrangement pitch of I / O pins for the purpose of providing a viable repair method, and the I / O.
A member for repairing an I / O pin is configured by a repair pin that is fitted into the pin insertion hole in a substantially fitted state, and a repair substrate having the repair pin mounted in one of the I / O pin insertion holes is provided. , The repair pin is located at the removal mark of the I / O pin to be repaired, and the I / O pin that does not require repair is inserted into another I / O pin insertion hole of the repair substrate. The feature is that the I / O pins are repaired by mounting them on a ceramic substrate in the form of

[Industrial application field]

The present invention relates to a method of repairing I / O pins applied when repairing I / O pins arranged on a ceramic substrate.

[Conventional technology]

FIGS. 3 (a) and 3 (b) are a perspective view and a side sectional view of the main part showing the structure of the ceramic substrate.

As shown in FIGS. 3A and 3B, the ceramic substrate 20
Are provided with reference pads 18 at a reference pitch P from each other, and I / O pins 1 for signal input / output or power supply are arranged on each of the reference pads 18 in an upright state. There is. These I / O pins 1 are brazed (soldered) to the respective reference pads 18 using a high temperature brazing material (solder having a higher melting temperature than the solder used for mounting electronic components). In the figure, 21 is a via for electrically connecting the reference pad 18 and the inner layer wiring 22.

These I / O pins 1 are not particularly problematic when they are used in a normal state, but if a large external force acts on them, they may be damaged by the impact. This I /
Of course, if the O-pin 1 is damaged, it will be repaired, but at that time, the following problems occur.

[Problems to be Solved by the Invention]

That is, if the damage to the I / O pin 1 is mere breakage or peeling from the reference pad 18, another I / O pin 1 may be prepared and re-soldered to the reference pad 18. (Even in this case, it goes without saying that the ceramic substrate 20 is locally heated, which is not preferable in terms of quality).

However, when the damage to the I / O pin 1 is caused by the I / O pin 1 and the reference pad 18 being simultaneously peeled off from the ceramic substrate 20 as shown in FIG. It is adhered to the ceramic substrate 20 by using it and a repairing wire (hereinafter referred to as a repairing wire) 6 is connected to the reference pad 18 thereof (this repairing wire 6 is the I / O pin 1 to be repaired).
(Corresponding vias 21 and inner layer wirings 22 provided correspondingly are connected at locations other than those shown) for repairing. However, it is technically impossible to correctly position the I / O pin 1 that has been separated from the ceramic substrate 20 in the reference pads 18 from each other. Was there.

The present invention provides a method for effectively repairing a failure such as that shown in FIG.

[Means for Solving the Problems]

As shown in FIGS. 1 and 2, an I / O pin restoration method according to the present invention (hereinafter referred to as “pin restoration method”) has at least three I / O pins 1 corresponding to the arrangement pitch P of the I / O pins 1. The repair substrate 10 having the I / O pin insertion hole 8 and the repair pin 5 inserted into the I / O pin insertion hole 8 in a substantially fitted state form an I / O pin repair member. A repair substrate 10 having the repair pin 5 in place of the I / O pin 1 to be repaired is mounted in one of the I / O pin insertion holes 8, and the repair pin 5 is used to repair the I / O pin to be repaired. The I / O pin 1 which is located at the removal trace of No. 1 and does not require repair is the other I of the repair substrate 10.
The repairing substrate 10 is mounted on the ceramic substrate 20 so as to be inserted into the / O pin insertion hole 8 to repair the pins.

[Work]

The pin repairing method according to the present invention comprises mounting the repairing substrate 10 equipped with the repairing pin 5 in place of the I / O pin 1 to be repaired on the ceramic substrate 20, that is, the I / O pin to be repaired substantially.
The I / O pin is repaired by replacing the O pin 1 with the repair pin 5, and the normal I / O pin 1 is used as a guide for positioning the repair pin 5. Therefore, the positioning accuracy of the repair pin 5 can be significantly improved.

〔Example〕

 The present invention will be described in detail below with reference to the accompanying drawings.

FIGS. 1 (a) and 1 (b) are a schematic perspective view showing a structural example of a repair substrate used in the present invention and a cross-sectional view taken along line AA, and FIG.
FIGS. (A), (b) and (c) are side sectional views of the essential part showing one embodiment of the present invention, in which the same parts as those in FIGS. 3 and 4 are designated by the same reference numerals. .

As shown in FIGS. 1A and 1B, the repair substrate 10 is
For example, three I / O pin insertion holes 8 made of ceramic or the like and provided at a reference pitch P from each other, and a metallized pad 15 and a bonding pad formed in the peripheral portion of the I / O pin insertion hole 8. Equipped with 11. The size or shape of the metallized pad 15 and the bonding pad 11 will not be specified because they can be determined at the design stage.

An embodiment of the present invention will be described below in the order of steps with reference to FIGS. 2 (a), 2 (b) and 2 (c). This embodiment is intended for the case where the I / O pin is in the state shown in FIG.

(1). First Step [Refer to FIG. 2 (a)] This step is a step of embedding an insulator 7 in which, for example, a ceramic material and an adhesive material are mixed in the mark of the dropped I / O pin 1, and the surface of the insulator 7 is It is finished so as to be flush with the surface of the ceramic substrate 20.

(2). Second Step [See FIG. 2 (b)] This step is a step of mounting the repair pin 5 on the repair substrate 10 shown in FIG. In this step, as shown in FIG. 2B, the repair pin 5 is inserted into the pin insertion hole 8 at the center of the pin insertion hole 8 in a fitted state, and then the solder 40 is used to solder the metallized pad 15 to the metallized pad 15. Attached. At this time, the distance between the restoration pin 5 and the I / O pin insertion holes 8 provided on both sides of the restoration pin 5 is the reference pitch P.

(3). Third step [see FIG. 2 (c)] In this step, the repair substrate 10 on which the repair pins 5 are mounted is finished.
Is attached to the ceramic substrate 20 so that the repair pin 5 is located at the mark of the I / O pin 1 to be repaired,
At this time, the two I / O pins 1 on the ceramic substrate 20 side are fitted into the I / O pin insertion holes 8 on the restoration substrate 10 side in a fitted state. After this operation, the ceramic substrate 20 side
The I / O pins 1 are soldered to the metallized pads 15 provided on the repair substrate 10 side using solder 40, respectively.

When the repair work of the I / O pin 1 is completed in this way, the repair wire 6 is connected to the bonding pad 11 on which the repair pin 5 is mounted.

The pin repair method according to the present invention has a configuration in which the normal I / O pins 1 arranged on both sides of the I / O pin to be repaired are used as positioning guides and the repair pin 5 is mounted. The positioning accuracy is extremely higher than that of the conventional method.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, the positional accuracy of the repair pin 5 newly mounted as an alternative to the I / O pin to be repaired can be remarkably improved, and its work is remarkably facilitated. Therefore, there is an excellent industrial effect that the reliability of I / O pin repair work and the work efficiency can be greatly improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) and 1 (b) are schematic perspective views showing a structural example of a repair substrate used in the present invention and a cross-sectional view taken along the line AA, and FIG. 2 (a). 1, (b) and (c) are cross-sectional views of an essential part showing an embodiment of the present invention, and FIGS. 3 (a) and (b) are a perspective view and a cross-sectional view of a main part showing a structure of a ceramic substrate. FIG. 4 is a partially broken perspective view showing an example of damage to the I / O pin. In the figure, 1 is an I / O pin, 5 is a repair pin, 6 is a repair wire, 7 is an insulator, 8 is an I / O pin communication hole, 10 is a repair substrate, 11 is a bonding pad, 15 is a metallized pad, Reference numeral 18 is a reference pad, 20 is a ceramic substrate, 21 is a via, 22 is an inner layer wiring, and 40 is solder.

Claims (1)

[Claims] 1. An I / O arranged on a ceramic substrate (20).
This is a method applied when repairing the pin (1), and is equipped with at least three I / O pin insertion holes (8) provided corresponding to the arrangement pitch (P) of the I / O pins (1). And a repair substrate (10) and a repair pin (5) which is fitted into the I / O pin insertion hole (8) in a substantially fitted state to form an I / O pin repair member. A repair substrate (10) having the repair pin (5) mounted in one of the I / O pin insertion holes (8) is removed by the repair pin (5) to remove the repair target I / O pin (1). The ceramic substrate in such a manner that it is located in the trace and the I / O pin (1) that does not require repair is inserted into the other I / O pin insertion hole (8) of the repair substrate (10). A method of repairing an I / O pin, characterized by being mounted on (20) to repair the I / O pin (1).