JPH0766704A - Pulse circuit - Google Patents

Abstract

PURPOSE:To enable this pulse circuit to have sufficiently large discharged current supplying capacity by electrically connecting an output of a circuit capable of generating a low impedance output only for a period of saturated voltage to a reference waveform generating circuit. CONSTITUTION:This pulse circuit is provided with the reference waveform generating circuit 1A for generating a rising/falling waveform and the circuit 1B capable of generating a low impedance output only for the period of saturated voltage and respective outputs are electrically connected. If a load current is suddenly allowed to flow when an output pulse is in a saturate voltage period, i.e., when a transistor(TR) Q5 e.g. is OFF, output voltage continuously falls until the gate voltage of a TR Q3 exceeds ON voltage even in a delay time up to transition from OFF to ON and then the output voltage reaches low output impedance to maximize current supply capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse circuit which is capacitive and drives a load in which impedance fluctuations repeat every pulse cycle, and more particularly to a gas discharge element which becomes low impedance after the applied pulse voltage is saturated. The present invention relates to a pulse circuit suitable for a drive circuit such as (plasma display).

[0002]

2. Description of the Related Art A plasma display is a display device that utilizes the discharge phenomenon of a rare gas enclosed inside.
The display cell of the plasma display panel acts as a simple capacitive load when the voltage applied to it is below the discharge start voltage, but once it exceeds the discharge start voltage,
Since the rare gas in the display cell is discharged, it changes to a low impedance resistive load at that moment.

The plasma display panel is roughly classified into a DC type and an AC type.

Since the electrodes of the DC type are exposed to the display cell, a means for adding a current limiting resistance at the time of discharging is generally used.

On the other hand, in the AC type, the electrodes are covered with a dielectric, so that the capacitors are equivalently connected in series at both ends of the display cell. Therefore, after the discharge is generated, the electric charge that cancels the externally applied voltage is attracted to the surface of the dielectric, the effective voltage inside the display cell becomes low, and the discharge ends. After that, when an external voltage having the same polarity as the internal voltage is applied, the discharge process similar to that described above is performed and then converges. The charges on the surface of the dielectric material that generate this internal voltage are called wall charges. When this wall charge exists, discharge can be repeatedly generated even if the externally applied voltage is below the discharge start voltage. This action is called a memory action and is a feature of the AC type plasma display panel.

In the AC type plasma display panel, a drive circuit having a low impedance output capable of suppressing the voltage drop of the externally applied voltage as much as possible is necessary in order to generate sufficient wall charges to bring out the memory effect. is there.

Conventionally, in order to realize this drive circuit, a CMOS type circuit as shown in FIG. 5 has been used. In this circuit, FETs Q19 and Q20 are alternately turned on and off.
A pulse waveform is output by repeating FF. FET
Q19 and Q20 have low on-resistance and large maximum drain current, but if one element is not enough, multiple FETs should be connected in parallel to obtain lower impedance output. It was being done.

FIG. 6 shows a totem pole type circuit as another circuit example in the prior art. This circuit outputs a pulse waveform by alternately turning on and off Q22 and Q23. Q21 is a PNP transistor for current amplification, and Q22 and Q23 are NPN transistors for output. A bipolar transistor having a small collector-emitter saturation voltage and a large maximum collector current has been selected for Q22 and Q23.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As individual elements used for switching in these drive circuits,
With each technological advancement, the one satisfying the above-mentioned requirements has been obtained, and a driving circuit having a low impedance output and a high switching speed has been achieved.

By obtaining the drive circuit having such characteristics, the characteristics at the time of discharging became very good. However, the steep rise and fall of the output pulse causes excessive overshoot and ringing at both ends of the display cell due to the inductance of the output line, and it becomes impossible to obtain a stable applied voltage. Due to its existence, a lot of line noise and radiated noise were generated, and it became easy to cause a malfunction.

[0011]

Means for Solving the Problems A pulse circuit of the present invention includes a first circuit that switches at the rising and falling edges of a pulse, and a high level output after the rising and falling periods of the pulse are completed. Alternatively, it is characterized by comprising a second circuit which is turned on only during a period of being saturated to a low level, and electrically connecting the output end of the first circuit and the output end of the second circuit.

[0012]

In the gas discharge, there is a discharge delay phenomenon that the discharge does not occur until a certain period of time elapses even if a voltage is applied. This time varies depending on the applied voltage, the wall charge amount and the space charge amount immediately before the application, and also changes depending on the type of the enclosed gas. However, under any of the conditions, there is a minimum discharge delay time, and for example, in the case of He-Xe mixed gas, an experimental value of about 0.5 μs was obtained when the voltage was driven in the memory region.

Therefore, if the rise time and the fall time of the pulse voltage are set to be relatively large within the range of the discharge delay time or less, the high frequency of ringing and overshoot at the pulse rise has almost no effect on the discharge characteristic. The components can be reduced.

Therefore, a basic waveform generating circuit for producing rising and falling edges and a falling edge of a pulse, or
A circuit that provides a low impedance output only during the saturation voltage after the rise is completed and each output is electrically connected to provide a suitable rise / fall time and sufficient discharge current supply capability. Became possible.

[0015]

EXAMPLES Next, examples of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. It consists of two types of circuit parts, 1A and 1B.
A is a source follower type output, and 1B is a CMOS type output circuit.

The input terminals IN1 to IN4 and the output terminal O of FIG.
The voltage waveform of UT1 is shown in FIG. In FIG. 4, voltage waveforms 4A to 4D correspond to voltage waveforms applied to the input terminals IN1 to IN4, respectively, and 4E is an output waveform of the output terminal OUT1.

One cycle of this driving is classified into a period from a to d. During period a, Q1 and Q3 are ON, and other FE
Since T is OFF, the output rises from 0V potential to Vs potential. The rising time at this time is the resistance R
2, R3, R4 and parasitic capacitances (Q1, Q2
Output capacitance and wiring stray capacitance, etc.). Therefore, when the load is a plasma display panel, the above-mentioned time constants, especially R2 and R
Set R3 and R4 appropriately. Q3 is a current buffer at the time of rising in the source follower type, which keeps the output impedance of the circuit relatively low and suppresses the fluctuation of the rising time due to the load capacitance.

In period b, Q1, Q3 and Q5 are ON, and Q
2, Q4 and Q6 are OFF. Q1 continues to be in the ON state during the period a, but the output impedance depends on Q5 if the element having the smallest ON resistance is selected for Q5.

In the period b in which the output pulse is at the saturation voltage Vs, when the load current suddenly flows, only the source follower circuit operates, that is, if Q5 is OFF here.
Then, the output voltage drops until the gate voltage of Q3 becomes equal to or higher than the ON voltage, and further, the output voltage continues to drop even in the delay time from the transition from OFF to ON, and then the low voltage The output impedance becomes the maximum current supply capacity.

Therefore, in the case of a load in which a discharge current suddenly flows out after application of a voltage and converges in a very short time as in the AC type plasma display panel, the source follower type always maintains a low output impedance during the discharge period. Is difficult. However, in this embodiment,
Since the Q5 of the CMOS type circuit 1B continues to be kept in the ON state, it is possible to always cope with a sharp change in the load current with its maximum driving ability.

The period c is a period in which Q2 and Q4 are ON and the other FETs are OFF and the voltage of the output terminal OUT1 falls from Vs to 0 potential. The fall time is the same as the rise time, and the resistors R2, R3, R
4 and the total parasitic capacitance (total of the parasitic capacitances of Q1 and Q2, the stray capacitance of the wiring, etc.) 4 and the parasitic capacitance. Q4 is a current buffer at the time of falling in the source follower type, and functions to keep the output impedance of the circuit relatively low.

During the period d, Q2, Q4 and Q6 are ON and Q
1, Q3 and Q5 are OFF. Q4 continues to be in the ON state for the period c, but the output impedance depends on Q6 if the element having the smallest ON resistance is selected for Q6. The operation mechanism is similar to that of the period b.

Further, in the period b and the period c, it is effective to connect Q5 and Q6 in parallel with a plurality of FETs in order to achieve a lower output impedance.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. It consists of two types of circuit parts, 2A and 2B.
A is an emitter follower type output, and 2B is a totem pole type output circuit. Input terminals IN5-8 and output terminal O
The voltage waveform of UT2 is shown in FIG. 4 as in the first embodiment. In FIG. 4, 4A to 4D are input terminals IN, respectively.
Corresponding to the voltage waveform applied to 5 to IN8, 4E is the output waveform of the output terminal OUT2.

Since Q7 and Q9 are ON and the other transistors are OFF during the period a, the output rises from 0V potential to Vs potential. The rise time at this time is the resistance R7, R8, R9 and the parasitic capacitance (total of the output capacitance of Q7 and Q8 and the stray capacitance of the wiring) related thereto.
Depends on the time constant determined by Q9 is a current buffer at the time of rising in the emitter follower type, which keeps the output impedance of the circuit relatively low and suppresses the fluctuation of the rising time due to the load capacitance.

In period b, Q7, Q9, Q11, Q12,
Q13 is ON and Q8, Q10, Q14 are OFF. Q9 remains ON for the period a,
If an element with a small collector-emitter saturation voltage and a large maximum collector current is selected for Q12, the output impedance will depend on Q12.

In the period b in which the output pulse is at the saturation voltage Vs, if the load current suddenly flows, only the emitter follower type circuit operates, that is, if Q12 is used.
Is OFF, the output voltage thereof continues to drop in the delay time until the transition of Q9 from OFF to ON, and then the output voltage becomes low and the current supply capability becomes maximum.

However, in this embodiment, since the Q12 of the totem pole type circuit 2B continues to be in the ON state, it is possible to cope with a sharp change in the load current with its maximum drive capacity.

During the period c, Q8 and Q10 are ON, the other transistors are OFF, and the output terminal OUT2
Is a period in which the voltage of V falls from Vs to 0 potential. The fall time is the same as the rise time.
8, R9 and the total parasitic capacitance (total of parasitic capacitances of Q7 and Q8, stray capacitance of wiring, etc.) depending on them and R9. Q10 is a current buffer at the time of falling in the emitter follower type, and functions to keep the output impedance of the circuit relatively low.

During period d, Q8, Q10 and Q14 are ON
Therefore, the other transistors are off. Q10 continues to be in the ON state during the period c, but if an element is selected for Q14, the collector-emitter saturation voltage is small, and if the element with a large maximum collector current is selected, the output impedance will be Q14. Depends on.

The operating mechanism is similar to that of the period b.

Further, as shown in FIG. 3, in a circuit for generating a basic waveform, a resistor R is provided in its output line so as to have appropriate rise and fall times according to the load capacitance.
A combination of the CMOS type circuit 3A in which 19 and R20 are inserted and the low impedance output type CMOS type circuit 3B may be used.

Input terminals IN9 to IN12 and output terminal OUT
The voltage waveform of No. 3 is shown in FIG. 4 as in the first embodiment.
In FIG. 4, 4A-4D are input terminals IN9-
Corresponding to the voltage waveform applied to IN12, 4E is the output waveform of the output terminal OUT3.

[0034]

As described above, as in the source follower unit 1A of FIG. 1 or the emitter follower unit 2A of FIG. 2, a circuit that determines the rise time and fall time of a pulse and creates a basic waveform, and FIG. CMOS part 1
B or a circuit having a low impedance in the voltage saturation period of the pulse like the totem pole section 2B in FIG. 2 to obtain an appropriate rise time and fall time and to obtain a steep slope in the voltage saturation period. It has become possible to cope with various changes in load current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a timing chart showing waveforms of various parts in the circuits of FIGS. 1 and 2.

FIG. 5 is a diagram showing a conventional CMOS type pulse circuit.

FIG. 6 is a diagram showing a prior art totem pole type pulse circuit.

[Explanation of symbols]

Q1 to Q6, Q15 to Q20 FETs Q7 to Q14, Q21 to Q23 Bipolar transistors R1 to R26 Resistors C1 to C12 Capacitors ZD1 to ZD5 Zener diodes 1A Source follower type circuit section 1B in the first embodiment of the present invention First of the present invention CMOS type circuit part OUT1 in the embodiment of the present invention 2A Output terminal in the first embodiment of the present invention 2A Emitter-follower type circuit part 2B in the second embodiment of the present invention Totem pole type circuit part OUT2 in the second embodiment of the present invention Output terminal 3A in the second embodiment of the present invention 3A First CMOS type circuit portion 3B in the third embodiment of the present invention 3B Second CMOS type circuit portion OUT3 in the third embodiment of the present invention Output Terminals in Third Embodiment 4A, 4B, 4C, 4D First to Third Embodiments of the Present Invention Output terminals of the definitive input waveform 4E first to third output waveforms in the embodiment of OUT4 conventional output of the CMOS-type pulse circuit technology terminal OUT5 prior art totem pole type pulse circuit of the present invention

Claims (4)

[Claims] 1. A first circuit that switches at the rising and falling edges of a pulse, and only after the rising and falling periods of the pulse are completed and only when the output is saturated at a high level or a low level. A second circuit that is turned on, and an output end of the first circuit and an output end of the second circuit are electrically connected. 2. The first circuit is a switching circuit that generates a pulse having a specified time constant, or one of a source follower circuit and an emitter follower circuit connected to the output of the switching circuit. The pulse circuit according to claim 1, wherein: 3. The pulse circuit according to claim 2, wherein the second circuit is one of a CMOS type circuit and a totem pole type circuit. 4. A pulse circuit for driving a plasma display panel, comprising: a first circuit for switching at the rising and falling edges of the driving pulse; and after the rising and falling periods of the driving pulse have ended,
A second circuit which is turned on within a gas discharge delay period of the plasma display panel in a period in which the output is saturated to a high level or a low level, and an output terminal of the first circuit. And an output terminal of the second circuit are electrically connected to each other.