JPH0766372A - Formation of diffusion resistance layer - Google Patents

Abstract

PURPOSE:To provide a method for reducing the wiring resistance of a device wherein the source-drain of an NMOS transistor is used as wiring. CONSTITUTION:After an N-type impurity diffusion region 2 is formed in a P-type silicon substrate 1 by ion implantation, a P-type impuritiy diffusion region 3 is formed by ion-implanting P-type impurities concentration of 5X10<20>/cm<3> or higher. Since the P-type impurity diffusion region 3 is low resistive, high speed access of a device is possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a diffusion resistance layer for a device using an N type diffusion layer as a wiring.

[0002]

2. Description of the Related Art In recent years,
As the junction depth of the source / drain regions becomes shallower due to device miniaturization, in devices (ASIC, memory, etc.) that use the source / drain regions as wiring, it is necessary to reduce the wiring resistance of this portion. Therefore, the concentration of the diffusion layer has been conventionally increased, but the concentration and the resistivity of the N ⁺⁺ diffusion layer have almost reached saturation.
Further, although a salicide technique for forming a silicide that selectively forms a silicide in the source / drain regions has been studied, it has a drawback that the process becomes complicated. As described above, in order to use the N ⁺⁺ diffusion layer as a wiring, a simple process for reducing the resistance of the diffusion layer is required.

The problem to be solved by the present invention is what kind of means should be taken in order to obtain a method for forming a diffusion resistance layer, which greatly reduces the wiring resistance of the diffusion layer by a simple process. It is in.

[0004]

The invention according to claim 1 of the present application is a method for forming a diffusion resistance layer in which diffusion regions of a source and a drain of an N-channel MOS transistor are used as wirings, and the N type of the source and the drain is formed. Forming a P-type impurity diffusion region of 5 × 10 ²⁰ / cm ³ or more in the impurity diffusion region is a means for solving the problem.

The invention according to claim 2 is characterized in that the wiring according to claim 1 is a bit line of a memory integrated circuit.

[0006]

In the present invention, the fact that P ⁺⁺ has a lower resistivity than N ⁺⁺ in the high-concentration diffusion region of 5 × 10 ²⁰ / cm ³ or more is utilized, and P ^{++ is} contained in the N ⁺⁺ diffusion layer. By making the ⁺⁺ region, the wiring resistance of the diffusion layer can be reduced to about 2/5 or less.

For example, as shown in FIG. 6, high-concentration (1 × 10 ²¹ cm ⁻³ ) ion implantation is performed on the surface of a P-type silicon substrate 11, and an N-type impurity diffusion region 12 is formed.
When the P-type impurity diffusion regions are formed with the same concentration, as can be seen from the graph of FIG.
The ratio of the resistance value to the mold is about 5: 2. Along with this, in addition to speeding up access, the number of bit contacts in the memory can be reduced because the bit line can be extended, and the chip area can be reduced.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is a method for reducing the resistance of a diffusion resistance layer required in a device using an N ⁺⁺ diffusion layer as a wiring. The present inventors, in high concentration of 5 × 10 ²⁰ / cm ³ or more, focusing on that towards the P ⁺⁺ diffusion layer than N ⁺⁺ diffusion layer has a lower resistivity, in the N ⁺⁺ diffusion layer It was achieved to reduce the resistance of the diffusion layer to about 2/5 or less by making the P ⁺⁺ region.

The details of the present invention will be described below with reference to the embodiments shown in the drawings. First, the basic structure of this embodiment is shown in FIG.
A description will be given based on (A), (B), (C) and FIG.

In the figure, 1 is a P-type silicon substrate,
N-type impurity diffusion regions 2 serving as a source and a drain are formed on the silicon substrate 1. Further, a P-type impurity diffusion region 3 is formed in the N-type impurity diffusion region 2. Then, an interlayer insulating film 4 is deposited on the silicon substrate 1, and an Al contact 5 that comes into contact with the surface of the P-type impurity diffusion region 3 is formed through a contact hole opened in the interlayer insulating film 4. .

In FIG. 2 and FIG. 6 showing the conventional one, a P-type impurity diffusion region 3 and an N-type impurity diffusion region 32 are shown.
When the concentrations are equal to each other and are sufficiently high (5 × 10 ²⁰ / cm ³ or more), when the resistances between C and D and between E and F (both are the same distance) are compared, the resistance between C and D becomes lower. This is because the impurity concentration of the N-type impurity diffusion region 2 and the P-type impurity diffusion region 3 is high, so that both regions form an ohmic junction.
In addition, as shown in the graph of FIG. 3, 5 × 10 ²⁰ / cm ³
This is because the resistivity of the P-type region is lower than that of the P-type region in the above region.

Thus, the high concentration N-type impurity diffusion layer 2 is formed.
By forming the P-type impurity diffusion region 3 therein by low-energy, high-dose ion implantation, the resistance of the diffusion layer region can be reduced.

Next, the method for forming the diffusion resistance layer of the present invention will be described.
An embodiment applied to the memory array portion of the flat type E ² PROM will be described. FIG. 4 applies the present embodiment,
It is a plane explanatory view of the memory array part of a usual flat type E ² PROM. In the figure, 6 is a bit line consisting of a source or drain, 7 is a word line as a control gate,
8 is a floating gate, 9 is a bit contact, 1
0 is a column selection line, 11 is a bit selection line, and 12 is a word line.

FIG. 5A shows this flat type E ² PRO.
The state where the floating gate of the memory array part of M is formed is shown. In this forming method, the gate insulating film 13 is deposited on the P-type silicon substrate 1, then the polysilicon film 14 is deposited on the gate insulating film 13, and the lithography technique and the dry etching technique are used to form the polysilicon film 14.
Pattern the gate 14a as shown in FIG.

Next, as shown in FIG. 5B, the gate 1
LDD (Light Doped) using 4a as a mask
LDD with low concentration
Region 15 is formed. Next, an LDD spacer 16 made of, for example, SiO ₂ is formed on the side wall of the gate 14a by an ordinary method, and as shown in FIG. 5C, ion implantation is performed so that the N-type impurity has a high concentration, and the source 17S is formed. And the drain 17D are formed.

Further, as shown in FIG.
The side spacers 17 are formed outside the spacers 16 by the same method as that of the spacers 16. Next, ion implantation is performed so that the dose amount of the P-type impurity is 5 × 10 ²⁰ cm ⁻³ or more, and the P-type impurity diffusion region 18 is formed in the source 17S and the drain 17D. Can be formed in the source 17S and the drain 17D.
Therefore, the flat type E ² PROM as in this embodiment is
The wiring resistance of can be significantly reduced. Along with this, in addition to achieving high-speed access, since the bit lines can be extended in the memory, the number of bit contacts can be reduced and the chip area can be reduced.

According to the present invention, 5 × 10 ²⁰ / cm
^In the high-concentration range of ³ to, P ⁺⁺ is about 2/5 that of N ^++.
The resistance value can be lowered below.

Although the embodiment has been described above, the present invention is not limited to this, and various modifications can be made.

For example, in the above embodiment, the present invention is applied to the flat type E ² PROM, but N channel M
Of course, it can be applied to other devices using the source / drain of the OS transistor as wiring.

In the above embodiment, the N-channel transistor is formed on the P-type silicon substrate, but it may be formed on the P-well.

[0021]

As is apparent from the above description, according to the present invention, the resistance as the source / drain wiring of the N-channel transistor can be significantly reduced, and thus the access speed of various devices can be increased. Has the effect of Further, in the memory, since the bit lines can be extended, the number of bit contacts can be reduced, and the chip area can be reduced.

[Brief description of drawings]

FIG. 1A is a plan view of the basic structure of the present invention, and FIG.
Is a sectional view taken along the line AA of (A), and (C) is a sectional view taken along the line BB of (A).

FIG. 2 is a perspective view showing a diffusion layer structure of the present invention.

FIG. 3 is a graph showing the relationship between concentration and resistance of P-type impurities and N-type impurities.

FIG. 4 is a flat type E ² P used as an example of the present invention.
The plane explanatory view of ROM.

5A to 5D are process cross-sectional views showing a method for forming a diffusion resistance layer of this embodiment.

FIG. 6 is a perspective view showing a conventional diffusion layer structure.

[Explanation of symbols]

 1 ... Silicon substrate (P type) 2 ... N type impurity diffusion region 3 ... P type impurity diffusion region

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/06 H01L 21/265 J 8934-4M 27/06 102 E

Claims (2)

[Claims] 1. A method of forming a diffusion resistance layer using a diffusion region of a source and a drain of an N-channel MOS transistor as a wiring, comprising:
× 10 ²⁰ / cm ³ or more forming methods of the diffusion resistance layer, characterized in that the formation of the P-type impurity diffusion region. 2. The method for forming a diffusion resistance layer according to claim 1, wherein the wiring is a bit line of a memory integrated circuit.